2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
36 compatible = "arm,cortex-a7";
42 compatible = "arm,cortex-a7";
49 reg = <0x40000000 0x80000000>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>;
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
84 compatible = "fixed-clock";
85 clock-frequency = <0>;
90 compatible = "allwinner,sun4i-cpu-clk";
91 reg = <0x01c20050 0x4>;
94 * PLL1 is listed twice here.
95 * While it looks suspicious, it's actually documented
96 * that way both in the datasheet and in the code from
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
104 compatible = "allwinner,sun4i-axi-clk";
105 reg = <0x01c20050 0x4>;
109 ahb1_mux: ahb1_mux@01c20054 {
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
116 ahb1: ahb1@01c20054 {
118 compatible = "allwinner,sun4i-ahb-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>;
123 ahb1_gates: ahb1_gates@01c20060 {
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>;
128 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
129 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
130 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
131 "ahb1_nand0", "ahb1_sdram",
132 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
133 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
134 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
135 "ahb1_ehci1", "ahb1_ohci0",
136 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
137 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
138 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
139 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
140 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
141 "ahb1_drc0", "ahb1_drc1";
144 apb1: apb1@01c20054 {
146 compatible = "allwinner,sun4i-apb0-clk";
147 reg = <0x01c20054 0x4>;
151 apb1_gates: apb1_gates@01c20060 {
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>;
156 clock-output-names = "apb1_codec", "apb1_digital_mic",
157 "apb1_pio", "apb1_daudio0",
161 apb2_mux: apb2_mux@01c20058 {
163 compatible = "allwinner,sun4i-apb1-mux-clk";
164 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
168 apb2: apb2@01c20058 {
170 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>;
175 apb2_gates: apb2_gates@01c2006c {
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x4>;
180 clock-output-names = "apb2_i2c0", "apb2_i2c1",
181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
182 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5";
188 compatible = "simple-bus";
189 #address-cells = <1>;
193 pio: pinctrl@01c20800 {
194 compatible = "allwinner,sun6i-a31-pinctrl";
195 reg = <0x01c20800 0x400>;
196 interrupts = <0 11 4>,
200 clocks = <&apb1_gates 5>;
202 interrupt-controller;
203 #address-cells = <1>;
207 uart0_pins_a: uart0@0 {
208 allwinner,pins = "PH20", "PH21";
209 allwinner,function = "uart0";
210 allwinner,drive = <0>;
211 allwinner,pull = <0>;
216 compatible = "allwinner,sun4i-timer";
217 reg = <0x01c20c00 0xa0>;
218 interrupts = <0 18 4>,
226 wdt1: watchdog@01c20ca0 {
227 compatible = "allwinner,sun6i-wdt";
228 reg = <0x01c20ca0 0x20>;
231 uart0: serial@01c28000 {
232 compatible = "snps,dw-apb-uart";
233 reg = <0x01c28000 0x400>;
234 interrupts = <0 0 4>;
237 clocks = <&apb2_gates 16>;
241 uart1: serial@01c28400 {
242 compatible = "snps,dw-apb-uart";
243 reg = <0x01c28400 0x400>;
244 interrupts = <0 1 4>;
247 clocks = <&apb2_gates 17>;
251 uart2: serial@01c28800 {
252 compatible = "snps,dw-apb-uart";
253 reg = <0x01c28800 0x400>;
254 interrupts = <0 2 4>;
257 clocks = <&apb2_gates 18>;
261 uart3: serial@01c28c00 {
262 compatible = "snps,dw-apb-uart";
263 reg = <0x01c28c00 0x400>;
264 interrupts = <0 3 4>;
267 clocks = <&apb2_gates 19>;
271 uart4: serial@01c29000 {
272 compatible = "snps,dw-apb-uart";
273 reg = <0x01c29000 0x400>;
274 interrupts = <0 4 4>;
277 clocks = <&apb2_gates 20>;
281 uart5: serial@01c29400 {
282 compatible = "snps,dw-apb-uart";
283 reg = <0x01c29400 0x400>;
284 interrupts = <0 5 4>;
287 clocks = <&apb2_gates 21>;
291 gic: interrupt-controller@01c81000 {
292 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
293 reg = <0x01c81000 0x1000>,
297 interrupt-controller;
298 #interrupt-cells = <3>;
299 interrupts = <1 9 0xf04>;