arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  49 #include <dt-bindings/clock/sun6i-rtc.h>
  50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54         #address-cells = <1>;
  55         #size-cells = <1>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59         };
  60
  61         chosen {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 simplefb_hdmi: framebuffer-lcd0-hdmi {
  67                         compatible = "allwinner,simple-framebuffer",
  68                                      "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  71                                  <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  72                                  <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  73                                  <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  74                         status = "disabled";
  75                 };
  76
  77                 simplefb_lcd: framebuffer-lcd0 {
  78                         compatible = "allwinner,simple-framebuffer",
  79                                      "simple-framebuffer";
  80                         allwinner,pipeline = "de_be0-lcd0";
  81                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  82                                  <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  83                                  <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  84                         status = "disabled";
  85                 };
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv7-timer";
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  93                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  94                 clock-frequency = <24000000>;
  95                 arm,cpu-registers-not-fw-configured;
  96         };
  97
  98         cpus {
  99                 enable-method = "allwinner,sun6i-a31";
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102
 103                 cpu0: cpu@0 {
 104                         compatible = "arm,cortex-a7";
 105                         device_type = "cpu";
 106                         reg = <0>;
 107                         clocks = <&ccu CLK_CPU>;
 108                         clock-latency = <244144>; /* 8 32k periods */
 109                         operating-points =
 110                                 /* kHz    uV */
 111                                 <1008000 1200000>,
 112                                 <864000 1200000>,
 113                                 <720000 1100000>,
 114                                 <480000 1000000>;
 115                         #cooling-cells = <2>;
 116                 };
 117
 118                 cpu1: cpu@1 {
 119                         compatible = "arm,cortex-a7";
 120                         device_type = "cpu";
 121                         reg = <1>;
 122                         clocks = <&ccu CLK_CPU>;
 123                         clock-latency = <244144>; /* 8 32k periods */
 124                         operating-points =
 125                                 /* kHz    uV */
 126                                 <1008000 1200000>,
 127                                 <864000 1200000>,
 128                                 <720000 1100000>,
 129                                 <480000 1000000>;
 130                         #cooling-cells = <2>;
 131                 };
 132
 133                 cpu2: cpu@2 {
 134                         compatible = "arm,cortex-a7";
 135                         device_type = "cpu";
 136                         reg = <2>;
 137                         clocks = <&ccu CLK_CPU>;
 138                         clock-latency = <244144>; /* 8 32k periods */
 139                         operating-points =
 140                                 /* kHz    uV */
 141                                 <1008000 1200000>,
 142                                 <864000 1200000>,
 143                                 <720000 1100000>,
 144                                 <480000 1000000>;
 145                         #cooling-cells = <2>;
 146                 };
 147
 148                 cpu3: cpu@3 {
 149                         compatible = "arm,cortex-a7";
 150                         device_type = "cpu";
 151                         reg = <3>;
 152                         clocks = <&ccu CLK_CPU>;
 153                         clock-latency = <244144>; /* 8 32k periods */
 154                         operating-points =
 155                                 /* kHz    uV */
 156                                 <1008000 1200000>,
 157                                 <864000 1200000>,
 158                                 <720000 1100000>,
 159                                 <480000 1000000>;
 160                         #cooling-cells = <2>;
 161                 };
 162         };
 163
 164         thermal-zones {
 165                 cpu-thermal {
 166                         /* milliseconds */
 167                         polling-delay-passive = <250>;
 168                         polling-delay = <1000>;
 169                         thermal-sensors = <&rtp>;
 170
 171                         cooling-maps {
 172                                 map0 {
 173                                         trip = <&cpu_alert0>;
 174                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 175                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 176                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 177                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 178                                 };
 179                         };
 180
 181                         trips {
 182                                 cpu_alert0: cpu_alert0 {
 183                                         /* milliCelsius */
 184                                         temperature = <70000>;
 185                                         hysteresis = <2000>;
 186                                         type = "passive";
 187                                 };
 188
 189                                 cpu_crit: cpu_crit {
 190                                         /* milliCelsius */
 191                                         temperature = <100000>;
 192                                         hysteresis = <2000>;
 193                                         type = "critical";
 194                                 };
 195                         };
 196                 };
 197         };
 198
 199         pmu {
 200                 compatible = "arm,cortex-a7-pmu";
 201                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 205         };
 206
 207         clocks {
 208                 #address-cells = <1>;
 209                 #size-cells = <1>;
 210                 ranges;
 211
 212                 osc24M: clk-24M {
 213                         #clock-cells = <0>;
 214                         compatible = "fixed-clock";
 215                         clock-frequency = <24000000>;
 216                         clock-accuracy = <50000>;
 217                         clock-output-names = "osc24M";
 218                 };
 219
 220                 osc32k: clk-32k {
 221                         #clock-cells = <0>;
 222                         compatible = "fixed-clock";
 223                         clock-frequency = <32768>;
 224                         clock-accuracy = <50000>;
 225                         clock-output-names = "ext_osc32k";
 226                 };
 227
 228                 /*
 229                  * The following two are dummy clocks, placeholders
 230                  * used in the gmac_tx clock. The gmac driver will
 231                  * choose one parent depending on the PHY interface
 232                  * mode, using clk_set_rate auto-reparenting.
 233                  *
 234                  * The actual TX clock rate is not controlled by the
 235                  * gmac_tx clock.
 236                  */
 237                 mii_phy_tx_clk: clk-mii-phy-tx {
 238                         #clock-cells = <0>;
 239                         compatible = "fixed-clock";
 240                         clock-frequency = <25000000>;
 241                         clock-output-names = "mii_phy_tx";
 242                 };
 243
 244                 gmac_int_tx_clk: clk-gmac-int-tx {
 245                         #clock-cells = <0>;
 246                         compatible = "fixed-clock";
 247                         clock-frequency = <125000000>;
 248                         clock-output-names = "gmac_int_tx";
 249                 };
 250
 251                 gmac_tx_clk: clk@1c200d0 {
 252                         #clock-cells = <0>;
 253                         compatible = "allwinner,sun7i-a20-gmac-clk";
 254                         reg = <0x01c200d0 0x4>;
 255                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 256                         clock-output-names = "gmac_tx";
 257                 };
 258         };
 259
 260         de: display-engine {
 261                 compatible = "allwinner,sun6i-a31-display-engine";
 262                 allwinner,pipelines = <&fe0>, <&fe1>;
 263                 status = "disabled";
 264         };
 265
 266         soc {
 267                 compatible = "simple-bus";
 268                 #address-cells = <1>;
 269                 #size-cells = <1>;
 270                 ranges;
 271
 272                 dma: dma-controller@1c02000 {
 273                         compatible = "allwinner,sun6i-a31-dma";
 274                         reg = <0x01c02000 0x1000>;
 275                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&ccu CLK_AHB1_DMA>;
 277                         resets = <&ccu RST_AHB1_DMA>;
 278                         #dma-cells = <1>;
 279                 };
 280
 281                 tcon0: lcd-controller@1c0c000 {
 282                         compatible = "allwinner,sun6i-a31-tcon";
 283                         reg = <0x01c0c000 0x1000>;
 284                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 285                         dmas = <&dma 11>;
 286                         resets = <&ccu RST_AHB1_LCD0>,
 287                                  <&ccu RST_AHB1_LVDS>;
 288                         reset-names = "lcd",
 289                                       "lvds";
 290                         clocks = <&ccu CLK_AHB1_LCD0>,
 291                                  <&ccu CLK_LCD0_CH0>,
 292                                  <&ccu CLK_LCD0_CH1>,
 293                                  <&ccu 15>;
 294                         clock-names = "ahb",
 295                                       "tcon-ch0",
 296                                       "tcon-ch1",
 297                                       "lvds-alt";
 298                         clock-output-names = "tcon0-pixel-clock";
 299                         #clock-cells = <0>;
 300
 301                         ports {
 302                                 #address-cells = <1>;
 303                                 #size-cells = <0>;
 304
 305                                 tcon0_in: port@0 {
 306                                         #address-cells = <1>;
 307                                         #size-cells = <0>;
 308                                         reg = <0>;
 309
 310                                         tcon0_in_drc0: endpoint@0 {
 311                                                 reg = <0>;
 312                                                 remote-endpoint = <&drc0_out_tcon0>;
 313                                         };
 314
 315                                         tcon0_in_drc1: endpoint@1 {
 316                                                 reg = <1>;
 317                                                 remote-endpoint = <&drc1_out_tcon0>;
 318                                         };
 319                                 };
 320
 321                                 tcon0_out: port@1 {
 322                                         #address-cells = <1>;
 323                                         #size-cells = <0>;
 324                                         reg = <1>;
 325
 326                                         tcon0_out_hdmi: endpoint@1 {
 327                                                 reg = <1>;
 328                                                 remote-endpoint = <&hdmi_in_tcon0>;
 329                                                 allwinner,tcon-channel = <1>;
 330                                         };
 331                                 };
 332                         };
 333                 };
 334
 335                 tcon1: lcd-controller@1c0d000 {
 336                         compatible = "allwinner,sun6i-a31-tcon";
 337                         reg = <0x01c0d000 0x1000>;
 338                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 339                         dmas = <&dma 12>;
 340                         resets = <&ccu RST_AHB1_LCD1>,
 341                                  <&ccu RST_AHB1_LVDS>;
 342                         reset-names = "lcd", "lvds";
 343                         clocks = <&ccu CLK_AHB1_LCD1>,
 344                                  <&ccu CLK_LCD1_CH0>,
 345                                  <&ccu CLK_LCD1_CH1>,
 346                                  <&ccu 15>;
 347                         clock-names = "ahb",
 348                                       "tcon-ch0",
 349                                       "tcon-ch1",
 350                                       "lvds-alt";
 351                         clock-output-names = "tcon1-pixel-clock";
 352                         #clock-cells = <0>;
 353
 354                         ports {
 355                                 #address-cells = <1>;
 356                                 #size-cells = <0>;
 357
 358                                 tcon1_in: port@0 {
 359                                         #address-cells = <1>;
 360                                         #size-cells = <0>;
 361                                         reg = <0>;
 362
 363                                         tcon1_in_drc0: endpoint@0 {
 364                                                 reg = <0>;
 365                                                 remote-endpoint = <&drc0_out_tcon1>;
 366                                         };
 367
 368                                         tcon1_in_drc1: endpoint@1 {
 369                                                 reg = <1>;
 370                                                 remote-endpoint = <&drc1_out_tcon1>;
 371                                         };
 372                                 };
 373
 374                                 tcon1_out: port@1 {
 375                                         #address-cells = <1>;
 376                                         #size-cells = <0>;
 377                                         reg = <1>;
 378
 379                                         tcon1_out_hdmi: endpoint@1 {
 380                                                 reg = <1>;
 381                                                 remote-endpoint = <&hdmi_in_tcon1>;
 382                                                 allwinner,tcon-channel = <1>;
 383                                         };
 384                                 };
 385                         };
 386                 };
 387
 388                 mmc0: mmc@1c0f000 {
 389                         compatible = "allwinner,sun7i-a20-mmc";
 390                         reg = <0x01c0f000 0x1000>;
 391                         clocks = <&ccu CLK_AHB1_MMC0>,
 392                                  <&ccu CLK_MMC0>,
 393                                  <&ccu CLK_MMC0_OUTPUT>,
 394                                  <&ccu CLK_MMC0_SAMPLE>;
 395                         clock-names = "ahb",
 396                                       "mmc",
 397                                       "output",
 398                                       "sample";
 399                         resets = <&ccu RST_AHB1_MMC0>;
 400                         reset-names = "ahb";
 401                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 402                         pinctrl-names = "default";
 403                         pinctrl-0 = <&mmc0_pins>;
 404                         status = "disabled";
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                 };
 408
 409                 mmc1: mmc@1c10000 {
 410                         compatible = "allwinner,sun7i-a20-mmc";
 411                         reg = <0x01c10000 0x1000>;
 412                         clocks = <&ccu CLK_AHB1_MMC1>,
 413                                  <&ccu CLK_MMC1>,
 414                                  <&ccu CLK_MMC1_OUTPUT>,
 415                                  <&ccu CLK_MMC1_SAMPLE>;
 416                         clock-names = "ahb",
 417                                       "mmc",
 418                                       "output",
 419                                       "sample";
 420                         resets = <&ccu RST_AHB1_MMC1>;
 421                         reset-names = "ahb";
 422                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 423                         pinctrl-names = "default";
 424                         pinctrl-0 = <&mmc1_pins>;
 425                         status = "disabled";
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                 };
 429
 430                 mmc2: mmc@1c11000 {
 431                         compatible = "allwinner,sun7i-a20-mmc";
 432                         reg = <0x01c11000 0x1000>;
 433                         clocks = <&ccu CLK_AHB1_MMC2>,
 434                                  <&ccu CLK_MMC2>,
 435                                  <&ccu CLK_MMC2_OUTPUT>,
 436                                  <&ccu CLK_MMC2_SAMPLE>;
 437                         clock-names = "ahb",
 438                                       "mmc",
 439                                       "output",
 440                                       "sample";
 441                         resets = <&ccu RST_AHB1_MMC2>;
 442                         reset-names = "ahb";
 443                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 444                         status = "disabled";
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                 };
 448
 449                 mmc3: mmc@1c12000 {
 450                         compatible = "allwinner,sun7i-a20-mmc";
 451                         reg = <0x01c12000 0x1000>;
 452                         clocks = <&ccu CLK_AHB1_MMC3>,
 453                                  <&ccu CLK_MMC3>,
 454                                  <&ccu CLK_MMC3_OUTPUT>,
 455                                  <&ccu CLK_MMC3_SAMPLE>;
 456                         clock-names = "ahb",
 457                                       "mmc",
 458                                       "output",
 459                                       "sample";
 460                         resets = <&ccu RST_AHB1_MMC3>;
 461                         reset-names = "ahb";
 462                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 463                         status = "disabled";
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                 };
 467
 468                 hdmi: hdmi@1c16000 {
 469                         compatible = "allwinner,sun6i-a31-hdmi";
 470                         reg = <0x01c16000 0x1000>;
 471                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 472                         clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
 473                                  <&ccu CLK_HDMI_DDC>,
 474                                  <&ccu CLK_PLL_VIDEO0_2X>,
 475                                  <&ccu CLK_PLL_VIDEO1_2X>;
 476                         clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
 477                         resets = <&ccu RST_AHB1_HDMI>;
 478                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 479                         dmas = <&dma 13>, <&dma 13>, <&dma 14>;
 480                         status = "disabled";
 481
 482                         ports {
 483                                 #address-cells = <1>;
 484                                 #size-cells = <0>;
 485
 486                                 hdmi_in: port@0 {
 487                                         #address-cells = <1>;
 488                                         #size-cells = <0>;
 489                                         reg = <0>;
 490
 491                                         hdmi_in_tcon0: endpoint@0 {
 492                                                 reg = <0>;
 493                                                 remote-endpoint = <&tcon0_out_hdmi>;
 494                                         };
 495
 496                                         hdmi_in_tcon1: endpoint@1 {
 497                                                 reg = <1>;
 498                                                 remote-endpoint = <&tcon1_out_hdmi>;
 499                                         };
 500                                 };
 501
 502                                 hdmi_out: port@1 {
 503                                         reg = <1>;
 504                                 };
 505                         };
 506                 };
 507
 508                 usb_otg: usb@1c19000 {
 509                         compatible = "allwinner,sun6i-a31-musb";
 510                         reg = <0x01c19000 0x0400>;
 511                         clocks = <&ccu CLK_AHB1_OTG>;
 512                         resets = <&ccu RST_AHB1_OTG>;
 513                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 514                         interrupt-names = "mc";
 515                         phys = <&usbphy 0>;
 516                         phy-names = "usb";
 517                         extcon = <&usbphy 0>;
 518                         dr_mode = "otg";
 519                         status = "disabled";
 520                 };
 521
 522                 usbphy: phy@1c19400 {
 523                         compatible = "allwinner,sun6i-a31-usb-phy";
 524                         reg = <0x01c19400 0x10>,
 525                               <0x01c1a800 0x4>,
 526                               <0x01c1b800 0x4>;
 527                         reg-names = "phy_ctrl",
 528                                     "pmu1",
 529                                     "pmu2";
 530                         clocks = <&ccu CLK_USB_PHY0>,
 531                                  <&ccu CLK_USB_PHY1>,
 532                                  <&ccu CLK_USB_PHY2>;
 533                         clock-names = "usb0_phy",
 534                                       "usb1_phy",
 535                                       "usb2_phy";
 536                         resets = <&ccu RST_USB_PHY0>,
 537                                  <&ccu RST_USB_PHY1>,
 538                                  <&ccu RST_USB_PHY2>;
 539                         reset-names = "usb0_reset",
 540                                       "usb1_reset",
 541                                       "usb2_reset";
 542                         status = "disabled";
 543                         #phy-cells = <1>;
 544                 };
 545
 546                 ehci0: usb@1c1a000 {
 547                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 548                         reg = <0x01c1a000 0x100>;
 549                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 550                         clocks = <&ccu CLK_AHB1_EHCI0>;
 551                         resets = <&ccu RST_AHB1_EHCI0>;
 552                         phys = <&usbphy 1>;
 553                         phy-names = "usb";
 554                         status = "disabled";
 555                 };
 556
 557                 ohci0: usb@1c1a400 {
 558                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 559                         reg = <0x01c1a400 0x100>;
 560                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
 562                         resets = <&ccu RST_AHB1_OHCI0>;
 563                         phys = <&usbphy 1>;
 564                         phy-names = "usb";
 565                         status = "disabled";
 566                 };
 567
 568                 ehci1: usb@1c1b000 {
 569                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 570                         reg = <0x01c1b000 0x100>;
 571                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&ccu CLK_AHB1_EHCI1>;
 573                         resets = <&ccu RST_AHB1_EHCI1>;
 574                         phys = <&usbphy 2>;
 575                         phy-names = "usb";
 576                         status = "disabled";
 577                 };
 578
 579                 ohci1: usb@1c1b400 {
 580                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 581                         reg = <0x01c1b400 0x100>;
 582                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 583                         clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
 584                         resets = <&ccu RST_AHB1_OHCI1>;
 585                         phys = <&usbphy 2>;
 586                         phy-names = "usb";
 587                         status = "disabled";
 588                 };
 589
 590                 ohci2: usb@1c1c400 {
 591                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 592                         reg = <0x01c1c400 0x100>;
 593                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 594                         clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
 595                         resets = <&ccu RST_AHB1_OHCI2>;
 596                         status = "disabled";
 597                 };
 598
 599                 ccu: clock@1c20000 {
 600                         compatible = "allwinner,sun6i-a31-ccu";
 601                         reg = <0x01c20000 0x400>;
 602                         clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 603                         clock-names = "hosc", "losc";
 604                         #clock-cells = <1>;
 605                         #reset-cells = <1>;
 606                 };
 607
 608                 pio: pinctrl@1c20800 {
 609                         compatible = "allwinner,sun6i-a31-pinctrl";
 610                         reg = <0x01c20800 0x400>;
 611                         interrupt-parent = <&r_intc>;
 612                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 613                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 614                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
 617                                  <&rtc CLK_OSC32K>;
 618                         clock-names = "apb", "hosc", "losc";
 619                         gpio-controller;
 620                         interrupt-controller;
 621                         #interrupt-cells = <3>;
 622                         #gpio-cells = <3>;
 623
 624                         gmac_gmii_pins: gmac-gmii-pins {
 625                                 pins = "PA0", "PA1", "PA2", "PA3",
 626                                                 "PA4", "PA5", "PA6", "PA7",
 627                                                 "PA8", "PA9", "PA10", "PA11",
 628                                                 "PA12", "PA13", "PA14", "PA15",
 629                                                 "PA16", "PA17", "PA18", "PA19",
 630                                                 "PA20", "PA21", "PA22", "PA23",
 631                                                 "PA24", "PA25", "PA26", "PA27";
 632                                 function = "gmac";
 633                                 /*
 634                                  * data lines in GMII mode run at 125MHz and
 635                                  * might need a higher signal drive strength
 636                                  */
 637                                 drive-strength = <30>;
 638                         };
 639
 640                         gmac_mii_pins: gmac-mii-pins {
 641                                 pins = "PA0", "PA1", "PA2", "PA3",
 642                                                 "PA8", "PA9", "PA11",
 643                                                 "PA12", "PA13", "PA14", "PA19",
 644                                                 "PA20", "PA21", "PA22", "PA23",
 645                                                 "PA24", "PA26", "PA27";
 646                                 function = "gmac";
 647                         };
 648
 649                         gmac_rgmii_pins: gmac-rgmii-pins {
 650                                 pins = "PA0", "PA1", "PA2", "PA3",
 651                                                 "PA9", "PA10", "PA11",
 652                                                 "PA12", "PA13", "PA14", "PA19",
 653                                                 "PA20", "PA25", "PA26", "PA27";
 654                                 function = "gmac";
 655                                 /*
 656                                  * data lines in RGMII mode use DDR mode
 657                                  * and need a higher signal drive strength
 658                                  */
 659                                 drive-strength = <40>;
 660                         };
 661
 662                         i2c0_pins: i2c0-pins {
 663                                 pins = "PH14", "PH15";
 664                                 function = "i2c0";
 665                         };
 666
 667                         i2c1_pins: i2c1-pins {
 668                                 pins = "PH16", "PH17";
 669                                 function = "i2c1";
 670                         };
 671
 672                         i2c2_pins: i2c2-pins {
 673                                 pins = "PH18", "PH19";
 674                                 function = "i2c2";
 675                         };
 676
 677                         lcd0_rgb888_pins: lcd0-rgb888-pins {
 678                                 pins = "PD0", "PD1", "PD2", "PD3",
 679                                                  "PD4", "PD5", "PD6", "PD7",
 680                                                  "PD8", "PD9", "PD10", "PD11",
 681                                                  "PD12", "PD13", "PD14", "PD15",
 682                                                  "PD16", "PD17", "PD18", "PD19",
 683                                                  "PD20", "PD21", "PD22", "PD23",
 684                                                  "PD24", "PD25", "PD26", "PD27";
 685                                 function = "lcd0";
 686                         };
 687
 688                         mmc0_pins: mmc0-pins {
 689                                 pins = "PF0", "PF1", "PF2",
 690                                                  "PF3", "PF4", "PF5";
 691                                 function = "mmc0";
 692                                 drive-strength = <30>;
 693                                 bias-pull-up;
 694                         };
 695
 696                         mmc1_pins: mmc1-pins {
 697                                 pins = "PG0", "PG1", "PG2", "PG3",
 698                                                  "PG4", "PG5";
 699                                 function = "mmc1";
 700                                 drive-strength = <30>;
 701                                 bias-pull-up;
 702                         };
 703
 704                         mmc2_4bit_pins: mmc2-4bit-pins {
 705                                 pins = "PC6", "PC7", "PC8", "PC9",
 706                                                  "PC10", "PC11";
 707                                 function = "mmc2";
 708                                 drive-strength = <30>;
 709                                 bias-pull-up;
 710                         };
 711
 712                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 713                                 pins = "PC6", "PC7", "PC8", "PC9",
 714                                                  "PC10", "PC11", "PC12",
 715                                                  "PC13", "PC14", "PC15",
 716                                                  "PC24";
 717                                 function = "mmc2";
 718                                 drive-strength = <30>;
 719                                 bias-pull-up;
 720                         };
 721
 722                         mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
 723                                 pins = "PC6", "PC7", "PC8", "PC9",
 724                                                  "PC10", "PC11", "PC12",
 725                                                  "PC13", "PC14", "PC15",
 726                                                  "PC24";
 727                                 function = "mmc3";
 728                                 drive-strength = <40>;
 729                                 bias-pull-up;
 730                         };
 731
 732                         spdif_tx_pin: spdif-tx-pin {
 733                                 pins = "PH28";
 734                                 function = "spdif";
 735                         };
 736
 737                         uart0_ph_pins: uart0-ph-pins {
 738                                 pins = "PH20", "PH21";
 739                                 function = "uart0";
 740                         };
 741                 };
 742
 743                 timer@1c20c00 {
 744                         compatible = "allwinner,sun4i-a10-timer";
 745                         reg = <0x01c20c00 0xa0>;
 746                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&osc24M>;
 753                 };
 754
 755                 wdt1: watchdog@1c20ca0 {
 756                         compatible = "allwinner,sun6i-a31-wdt";
 757                         reg = <0x01c20ca0 0x20>;
 758                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 759                         clocks = <&osc24M>;
 760                 };
 761
 762                 spdif: spdif@1c21000 {
 763                         #sound-dai-cells = <0>;
 764                         compatible = "allwinner,sun6i-a31-spdif";
 765                         reg = <0x01c21000 0x400>;
 766                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 767                         clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
 768                         resets = <&ccu RST_APB1_SPDIF>;
 769                         clock-names = "apb", "spdif";
 770                         dmas = <&dma 2>, <&dma 2>;
 771                         dma-names = "rx", "tx";
 772                         status = "disabled";
 773                 };
 774
 775                 i2s0: i2s@1c22000 {
 776                         #sound-dai-cells = <0>;
 777                         compatible = "allwinner,sun6i-a31-i2s";
 778                         reg = <0x01c22000 0x400>;
 779                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 780                         clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
 781                         resets = <&ccu RST_APB1_DAUDIO0>;
 782                         clock-names = "apb", "mod";
 783                         dmas = <&dma 3>, <&dma 3>;
 784                         dma-names = "rx", "tx";
 785                         status = "disabled";
 786                 };
 787
 788                 i2s1: i2s@1c22400 {
 789                         #sound-dai-cells = <0>;
 790                         compatible = "allwinner,sun6i-a31-i2s";
 791                         reg = <0x01c22400 0x400>;
 792                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 793                         clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
 794                         resets = <&ccu RST_APB1_DAUDIO1>;
 795                         clock-names = "apb", "mod";
 796                         dmas = <&dma 4>, <&dma 4>;
 797                         dma-names = "rx", "tx";
 798                         status = "disabled";
 799                 };
 800
 801                 lradc: lradc@1c22800 {
 802                         compatible = "allwinner,sun4i-a10-lradc-keys";
 803                         reg = <0x01c22800 0x100>;
 804                         interrupt-parent = <&r_intc>;
 805                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 806                         status = "disabled";
 807                 };
 808
 809                 rtp: rtp@1c25000 {
 810                         compatible = "allwinner,sun6i-a31-ts";
 811                         reg = <0x01c25000 0x100>;
 812                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 813                         #thermal-sensor-cells = <0>;
 814                 };
 815
 816                 uart0: serial@1c28000 {
 817                         compatible = "snps,dw-apb-uart";
 818                         reg = <0x01c28000 0x400>;
 819                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 820                         reg-shift = <2>;
 821                         reg-io-width = <4>;
 822                         clocks = <&ccu CLK_APB2_UART0>;
 823                         resets = <&ccu RST_APB2_UART0>;
 824                         dmas = <&dma 6>, <&dma 6>;
 825                         dma-names = "rx", "tx";
 826                         status = "disabled";
 827                 };
 828
 829                 uart1: serial@1c28400 {
 830                         compatible = "snps,dw-apb-uart";
 831                         reg = <0x01c28400 0x400>;
 832                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 833                         reg-shift = <2>;
 834                         reg-io-width = <4>;
 835                         clocks = <&ccu CLK_APB2_UART1>;
 836                         resets = <&ccu RST_APB2_UART1>;
 837                         dmas = <&dma 7>, <&dma 7>;
 838                         dma-names = "rx", "tx";
 839                         status = "disabled";
 840                 };
 841
 842                 uart2: serial@1c28800 {
 843                         compatible = "snps,dw-apb-uart";
 844                         reg = <0x01c28800 0x400>;
 845                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 846                         reg-shift = <2>;
 847                         reg-io-width = <4>;
 848                         clocks = <&ccu CLK_APB2_UART2>;
 849                         resets = <&ccu RST_APB2_UART2>;
 850                         dmas = <&dma 8>, <&dma 8>;
 851                         dma-names = "rx", "tx";
 852                         status = "disabled";
 853                 };
 854
 855                 uart3: serial@1c28c00 {
 856                         compatible = "snps,dw-apb-uart";
 857                         reg = <0x01c28c00 0x400>;
 858                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 859                         reg-shift = <2>;
 860                         reg-io-width = <4>;
 861                         clocks = <&ccu CLK_APB2_UART3>;
 862                         resets = <&ccu RST_APB2_UART3>;
 863                         dmas = <&dma 9>, <&dma 9>;
 864                         dma-names = "rx", "tx";
 865                         status = "disabled";
 866                 };
 867
 868                 uart4: serial@1c29000 {
 869                         compatible = "snps,dw-apb-uart";
 870                         reg = <0x01c29000 0x400>;
 871                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 872                         reg-shift = <2>;
 873                         reg-io-width = <4>;
 874                         clocks = <&ccu CLK_APB2_UART4>;
 875                         resets = <&ccu RST_APB2_UART4>;
 876                         dmas = <&dma 10>, <&dma 10>;
 877                         dma-names = "rx", "tx";
 878                         status = "disabled";
 879                 };
 880
 881                 uart5: serial@1c29400 {
 882                         compatible = "snps,dw-apb-uart";
 883                         reg = <0x01c29400 0x400>;
 884                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 885                         reg-shift = <2>;
 886                         reg-io-width = <4>;
 887                         clocks = <&ccu CLK_APB2_UART5>;
 888                         resets = <&ccu RST_APB2_UART5>;
 889                         dmas = <&dma 22>, <&dma 22>;
 890                         dma-names = "rx", "tx";
 891                         status = "disabled";
 892                 };
 893
 894                 i2c0: i2c@1c2ac00 {
 895                         compatible = "allwinner,sun6i-a31-i2c";
 896                         reg = <0x01c2ac00 0x400>;
 897                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 898                         clocks = <&ccu CLK_APB2_I2C0>;
 899                         resets = <&ccu RST_APB2_I2C0>;
 900                         pinctrl-names = "default";
 901                         pinctrl-0 = <&i2c0_pins>;
 902                         status = "disabled";
 903                         #address-cells = <1>;
 904                         #size-cells = <0>;
 905                 };
 906
 907                 i2c1: i2c@1c2b000 {
 908                         compatible = "allwinner,sun6i-a31-i2c";
 909                         reg = <0x01c2b000 0x400>;
 910                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&ccu CLK_APB2_I2C1>;
 912                         resets = <&ccu RST_APB2_I2C1>;
 913                         pinctrl-names = "default";
 914                         pinctrl-0 = <&i2c1_pins>;
 915                         status = "disabled";
 916                         #address-cells = <1>;
 917                         #size-cells = <0>;
 918                 };
 919
 920                 i2c2: i2c@1c2b400 {
 921                         compatible = "allwinner,sun6i-a31-i2c";
 922                         reg = <0x01c2b400 0x400>;
 923                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 924                         clocks = <&ccu CLK_APB2_I2C2>;
 925                         resets = <&ccu RST_APB2_I2C2>;
 926                         pinctrl-names = "default";
 927                         pinctrl-0 = <&i2c2_pins>;
 928                         status = "disabled";
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931                 };
 932
 933                 i2c3: i2c@1c2b800 {
 934                         compatible = "allwinner,sun6i-a31-i2c";
 935                         reg = <0x01c2b800 0x400>;
 936                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 937                         clocks = <&ccu CLK_APB2_I2C3>;
 938                         resets = <&ccu RST_APB2_I2C3>;
 939                         status = "disabled";
 940                         #address-cells = <1>;
 941                         #size-cells = <0>;
 942                 };
 943
 944                 gmac: ethernet@1c30000 {
 945                         compatible = "allwinner,sun7i-a20-gmac";
 946                         reg = <0x01c30000 0x1054>;
 947                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 948                         interrupt-names = "macirq";
 949                         clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
 950                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 951                         resets = <&ccu RST_AHB1_EMAC>;
 952                         reset-names = "stmmaceth";
 953                         snps,pbl = <2>;
 954                         snps,fixed-burst;
 955                         snps,force_sf_dma_mode;
 956                         status = "disabled";
 957
 958                         mdio: mdio {
 959                                 compatible = "snps,dwmac-mdio";
 960                                 #address-cells = <1>;
 961                                 #size-cells = <0>;
 962                         };
 963                 };
 964
 965                 crypto: crypto-engine@1c15000 {
 966                         compatible = "allwinner,sun6i-a31-crypto",
 967                                      "allwinner,sun4i-a10-crypto";
 968                         reg = <0x01c15000 0x1000>;
 969                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 970                         clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
 971                         clock-names = "ahb", "mod";
 972                         resets = <&ccu RST_AHB1_SS>;
 973                         reset-names = "ahb";
 974                 };
 975
 976                 codec: codec@1c22c00 {
 977                         #sound-dai-cells = <0>;
 978                         compatible = "allwinner,sun6i-a31-codec";
 979                         reg = <0x01c22c00 0x400>;
 980                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 981                         clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
 982                         clock-names = "apb", "codec";
 983                         resets = <&ccu RST_APB1_CODEC>;
 984                         dmas = <&dma 15>, <&dma 15>;
 985                         dma-names = "rx", "tx";
 986                         status = "disabled";
 987                 };
 988
 989                 timer@1c60000 {
 990                         compatible = "allwinner,sun6i-a31-hstimer",
 991                                      "allwinner,sun7i-a20-hstimer";
 992                         reg = <0x01c60000 0x1000>;
 993                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 994                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 995                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 996                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 997                         clocks = <&ccu CLK_AHB1_HSTIMER>;
 998                         resets = <&ccu RST_AHB1_HSTIMER>;
 999                 };
1000
1001                 spi0: spi@1c68000 {
1002                         compatible = "allwinner,sun6i-a31-spi";
1003                         reg = <0x01c68000 0x1000>;
1004                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1005                         clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
1006                         clock-names = "ahb", "mod";
1007                         dmas = <&dma 23>, <&dma 23>;
1008                         dma-names = "rx", "tx";
1009                         resets = <&ccu RST_AHB1_SPI0>;
1010                         status = "disabled";
1011                         #address-cells = <1>;
1012                         #size-cells = <0>;
1013                 };
1014
1015                 spi1: spi@1c69000 {
1016                         compatible = "allwinner,sun6i-a31-spi";
1017                         reg = <0x01c69000 0x1000>;
1018                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1019                         clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1020                         clock-names = "ahb", "mod";
1021                         dmas = <&dma 24>, <&dma 24>;
1022                         dma-names = "rx", "tx";
1023                         resets = <&ccu RST_AHB1_SPI1>;
1024                         status = "disabled";
1025                         #address-cells = <1>;
1026                         #size-cells = <0>;
1027                 };
1028
1029                 spi2: spi@1c6a000 {
1030                         compatible = "allwinner,sun6i-a31-spi";
1031                         reg = <0x01c6a000 0x1000>;
1032                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1033                         clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1034                         clock-names = "ahb", "mod";
1035                         dmas = <&dma 25>, <&dma 25>;
1036                         dma-names = "rx", "tx";
1037                         resets = <&ccu RST_AHB1_SPI2>;
1038                         status = "disabled";
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041                 };
1042
1043                 spi3: spi@1c6b000 {
1044                         compatible = "allwinner,sun6i-a31-spi";
1045                         reg = <0x01c6b000 0x1000>;
1046                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1047                         clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1048                         clock-names = "ahb", "mod";
1049                         dmas = <&dma 26>, <&dma 26>;
1050                         dma-names = "rx", "tx";
1051                         resets = <&ccu RST_AHB1_SPI3>;
1052                         status = "disabled";
1053                         #address-cells = <1>;
1054                         #size-cells = <0>;
1055                 };
1056
1057                 gic: interrupt-controller@1c81000 {
1058                         compatible = "arm,gic-400";
1059                         reg = <0x01c81000 0x1000>,
1060                               <0x01c82000 0x2000>,
1061                               <0x01c84000 0x2000>,
1062                               <0x01c86000 0x2000>;
1063                         interrupt-controller;
1064                         #interrupt-cells = <3>;
1065                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1066                 };
1067
1068                 fe0: display-frontend@1e00000 {
1069                         compatible = "allwinner,sun6i-a31-display-frontend";
1070                         reg = <0x01e00000 0x20000>;
1071                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1072                         clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1073                                  <&ccu CLK_DRAM_FE0>;
1074                         clock-names = "ahb", "mod",
1075                                       "ram";
1076                         resets = <&ccu RST_AHB1_FE0>;
1077
1078                         ports {
1079                                 #address-cells = <1>;
1080                                 #size-cells = <0>;
1081
1082                                 fe0_out: port@1 {
1083                                         #address-cells = <1>;
1084                                         #size-cells = <0>;
1085                                         reg = <1>;
1086
1087                                         fe0_out_be0: endpoint@0 {
1088                                                 reg = <0>;
1089                                                 remote-endpoint = <&be0_in_fe0>;
1090                                         };
1091
1092                                         fe0_out_be1: endpoint@1 {
1093                                                 reg = <1>;
1094                                                 remote-endpoint = <&be1_in_fe0>;
1095                                         };
1096                                 };
1097                         };
1098                 };
1099
1100                 fe1: display-frontend@1e20000 {
1101                         compatible = "allwinner,sun6i-a31-display-frontend";
1102                         reg = <0x01e20000 0x20000>;
1103                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1104                         clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1105                                  <&ccu CLK_DRAM_FE1>;
1106                         clock-names = "ahb", "mod",
1107                                       "ram";
1108                         resets = <&ccu RST_AHB1_FE1>;
1109
1110                         ports {
1111                                 #address-cells = <1>;
1112                                 #size-cells = <0>;
1113
1114                                 fe1_out: port@1 {
1115                                         #address-cells = <1>;
1116                                         #size-cells = <0>;
1117                                         reg = <1>;
1118
1119                                         fe1_out_be0: endpoint@0 {
1120                                                 reg = <0>;
1121                                                 remote-endpoint = <&be0_in_fe1>;
1122                                         };
1123
1124                                         fe1_out_be1: endpoint@1 {
1125                                                 reg = <1>;
1126                                                 remote-endpoint = <&be1_in_fe1>;
1127                                         };
1128                                 };
1129                         };
1130                 };
1131
1132                 be1: display-backend@1e40000 {
1133                         compatible = "allwinner,sun6i-a31-display-backend";
1134                         reg = <0x01e40000 0x10000>;
1135                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1136                         clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1137                                  <&ccu CLK_DRAM_BE1>;
1138                         clock-names = "ahb", "mod",
1139                                       "ram";
1140                         resets = <&ccu RST_AHB1_BE1>;
1141
1142                         ports {
1143                                 #address-cells = <1>;
1144                                 #size-cells = <0>;
1145
1146                                 be1_in: port@0 {
1147                                         #address-cells = <1>;
1148                                         #size-cells = <0>;
1149                                         reg = <0>;
1150
1151                                         be1_in_fe0: endpoint@0 {
1152                                                 reg = <0>;
1153                                                 remote-endpoint = <&fe0_out_be1>;
1154                                         };
1155
1156                                         be1_in_fe1: endpoint@1 {
1157                                                 reg = <1>;
1158                                                 remote-endpoint = <&fe1_out_be1>;
1159                                         };
1160                                 };
1161
1162                                 be1_out: port@1 {
1163                                         #address-cells = <1>;
1164                                         #size-cells = <0>;
1165                                         reg = <1>;
1166
1167                                         be1_out_drc1: endpoint@1 {
1168                                                 reg = <1>;
1169                                                 remote-endpoint = <&drc1_in_be1>;
1170                                         };
1171                                 };
1172                         };
1173                 };
1174
1175                 drc1: drc@1e50000 {
1176                         compatible = "allwinner,sun6i-a31-drc";
1177                         reg = <0x01e50000 0x10000>;
1178                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1179                         clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1180                                  <&ccu CLK_DRAM_DRC1>;
1181                         clock-names = "ahb", "mod",
1182                                       "ram";
1183                         resets = <&ccu RST_AHB1_DRC1>;
1184
1185                         ports {
1186                                 #address-cells = <1>;
1187                                 #size-cells = <0>;
1188
1189                                 drc1_in: port@0 {
1190                                         #address-cells = <1>;
1191                                         #size-cells = <0>;
1192                                         reg = <0>;
1193
1194                                         drc1_in_be1: endpoint@1 {
1195                                                 reg = <1>;
1196                                                 remote-endpoint = <&be1_out_drc1>;
1197                                         };
1198                                 };
1199
1200                                 drc1_out: port@1 {
1201                                         #address-cells = <1>;
1202                                         #size-cells = <0>;
1203                                         reg = <1>;
1204
1205                                         drc1_out_tcon0: endpoint@0 {
1206                                                 reg = <0>;
1207                                                 remote-endpoint = <&tcon0_in_drc1>;
1208                                         };
1209
1210                                         drc1_out_tcon1: endpoint@1 {
1211                                                 reg = <1>;
1212                                                 remote-endpoint = <&tcon1_in_drc1>;
1213                                         };
1214                                 };
1215                         };
1216                 };
1217
1218                 be0: display-backend@1e60000 {
1219                         compatible = "allwinner,sun6i-a31-display-backend";
1220                         reg = <0x01e60000 0x10000>;
1221                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1222                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1223                                  <&ccu CLK_DRAM_BE0>;
1224                         clock-names = "ahb", "mod",
1225                                       "ram";
1226                         resets = <&ccu RST_AHB1_BE0>;
1227
1228                         ports {
1229                                 #address-cells = <1>;
1230                                 #size-cells = <0>;
1231
1232                                 be0_in: port@0 {
1233                                         #address-cells = <1>;
1234                                         #size-cells = <0>;
1235                                         reg = <0>;
1236
1237                                         be0_in_fe0: endpoint@0 {
1238                                                 reg = <0>;
1239                                                 remote-endpoint = <&fe0_out_be0>;
1240                                         };
1241
1242                                         be0_in_fe1: endpoint@1 {
1243                                                 reg = <1>;
1244                                                 remote-endpoint = <&fe1_out_be0>;
1245                                         };
1246                                 };
1247
1248                                 be0_out: port@1 {
1249                                         reg = <1>;
1250
1251                                         be0_out_drc0: endpoint {
1252                                                 remote-endpoint = <&drc0_in_be0>;
1253                                         };
1254                                 };
1255                         };
1256                 };
1257
1258                 drc0: drc@1e70000 {
1259                         compatible = "allwinner,sun6i-a31-drc";
1260                         reg = <0x01e70000 0x10000>;
1261                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1262                         clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1263                                  <&ccu CLK_DRAM_DRC0>;
1264                         clock-names = "ahb", "mod",
1265                                       "ram";
1266                         resets = <&ccu RST_AHB1_DRC0>;
1267
1268                         ports {
1269                                 #address-cells = <1>;
1270                                 #size-cells = <0>;
1271
1272                                 drc0_in: port@0 {
1273                                         reg = <0>;
1274
1275                                         drc0_in_be0: endpoint {
1276                                                 remote-endpoint = <&be0_out_drc0>;
1277                                         };
1278                                 };
1279
1280                                 drc0_out: port@1 {
1281                                         #address-cells = <1>;
1282                                         #size-cells = <0>;
1283                                         reg = <1>;
1284
1285                                         drc0_out_tcon0: endpoint@0 {
1286                                                 reg = <0>;
1287                                                 remote-endpoint = <&tcon0_in_drc0>;
1288                                         };
1289
1290                                         drc0_out_tcon1: endpoint@1 {
1291                                                 reg = <1>;
1292                                                 remote-endpoint = <&tcon1_in_drc0>;
1293                                         };
1294                                 };
1295                         };
1296                 };
1297
1298                 rtc: rtc@1f00000 {
1299                         #clock-cells = <1>;
1300                         compatible = "allwinner,sun6i-a31-rtc";
1301                         reg = <0x01f00000 0x54>;
1302                         interrupt-parent = <&r_intc>;
1303                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1304                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1305                         clocks = <&osc32k>;
1306                         clock-output-names = "osc32k";
1307                 };
1308
1309                 r_intc: interrupt-controller@1f00c00 {
1310                         compatible = "allwinner,sun6i-a31-r-intc";
1311                         interrupt-controller;
1312                         #interrupt-cells = <3>;
1313                         reg = <0x01f00c00 0x400>;
1314                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1315                 };
1316
1317                 prcm@1f01400 {
1318                         compatible = "allwinner,sun6i-a31-prcm";
1319                         reg = <0x01f01400 0x200>;
1320
1321                         ar100: ar100_clk {
1322                                 compatible = "allwinner,sun6i-a31-ar100-clk";
1323                                 #clock-cells = <0>;
1324                                 clocks = <&rtc CLK_OSC32K>, <&osc24M>,
1325                                          <&ccu CLK_PLL_PERIPH>,
1326                                          <&ccu CLK_PLL_PERIPH>;
1327                                 clock-output-names = "ar100";
1328                         };
1329
1330                         ahb0: ahb0_clk {
1331                                 compatible = "fixed-factor-clock";
1332                                 #clock-cells = <0>;
1333                                 clock-div = <1>;
1334                                 clock-mult = <1>;
1335                                 clocks = <&ar100>;
1336                                 clock-output-names = "ahb0";
1337                         };
1338
1339                         apb0: apb0_clk {
1340                                 compatible = "allwinner,sun6i-a31-apb0-clk";
1341                                 #clock-cells = <0>;
1342                                 clocks = <&ahb0>;
1343                                 clock-output-names = "apb0";
1344                         };
1345
1346                         apb0_gates: apb0_gates_clk {
1347                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1348                                 #clock-cells = <1>;
1349                                 clocks = <&apb0>;
1350                                 clock-output-names = "apb0_pio", "apb0_ir",
1351                                                 "apb0_timer", "apb0_p2wi",
1352                                                 "apb0_uart", "apb0_1wire",
1353                                                 "apb0_i2c";
1354                         };
1355
1356                         ir_clk: ir_clk {
1357                                 #clock-cells = <0>;
1358                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1359                                 clocks = <&rtc CLK_OSC32K>, <&osc24M>;
1360                                 clock-output-names = "ir";
1361                         };
1362
1363                         apb0_rst: apb0_rst {
1364                                 compatible = "allwinner,sun6i-a31-clock-reset";
1365                                 #reset-cells = <1>;
1366                         };
1367                 };
1368
1369                 cpucfg@1f01c00 {
1370                         compatible = "allwinner,sun6i-a31-cpuconfig";
1371                         reg = <0x01f01c00 0x300>;
1372                 };
1373
1374                 ir: ir@1f02000 {
1375                         compatible = "allwinner,sun6i-a31-ir";
1376                         clocks = <&apb0_gates 1>, <&ir_clk>;
1377                         clock-names = "apb", "ir";
1378                         resets = <&apb0_rst 1>;
1379                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1380                         reg = <0x01f02000 0x40>;
1381                         status = "disabled";
1382                 };
1383
1384                 r_pio: pinctrl@1f02c00 {
1385                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1386                         reg = <0x01f02c00 0x400>;
1387                         interrupt-parent = <&r_intc>;
1388                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1389                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1390                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
1391                         clock-names = "apb", "hosc", "losc";
1392                         gpio-controller;
1393                         interrupt-controller;
1394                         #interrupt-cells = <3>;
1395                         #gpio-cells = <3>;
1396
1397                         s_ir_rx_pin: s-ir-rx-pin {
1398                                 pins = "PL4";
1399                                 function = "s_ir";
1400                         };
1401
1402                         s_p2wi_pins: s-p2wi-pins {
1403                                 pins = "PL0", "PL1";
1404                                 function = "s_p2wi";
1405                         };
1406                 };
1407
1408                 p2wi: i2c@1f03400 {
1409                         compatible = "allwinner,sun6i-a31-p2wi";
1410                         reg = <0x01f03400 0x400>;
1411                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1412                         clocks = <&apb0_gates 3>;
1413                         clock-frequency = <100000>;
1414                         resets = <&apb0_rst 3>;
1415                         pinctrl-names = "default";
1416                         pinctrl-0 = <&s_p2wi_pins>;
1417                         status = "disabled";
1418                         #address-cells = <1>;
1419                         #size-cells = <0>;
1420                 };
1421         };
1422 };