arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 #include <dt-bindings/dma/sun4i-a10.h>
  19 #include <dt-bindings/pinctrl/sun4i-a10.h>
  20
  21 / {
  22         interrupt-parent = <&intc>;
  23
  24         aliases {
  25                 serial0 = &uart1;
  26                 serial1 = &uart3;
  27         };
  28
  29         chosen {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 ranges;
  33
  34                 framebuffer@0 {
  35                         compatible = "allwinner,simple-framebuffer",
  36                                      "simple-framebuffer";
  37                         allwinner,pipeline = "de_be0-lcd0";
  38                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  39                         status = "disabled";
  40                 };
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a8";
  50                         reg = <0x0>;
  51                         clocks = <&cpu>;
  52                         clock-latency = <244144>; /* 8 32k periods */
  53                         operating-points = <
  54                                 /* kHz    uV */
  55                                 1104000 1500000
  56                                 1008000 1400000
  57                                 912000  1350000
  58                                 864000  1300000
  59                                 624000  1200000
  60                                 576000  1200000
  61                                 432000  1200000
  62                                 >;
  63                         #cooling-cells = <2>;
  64                         cooling-min-level = <0>;
  65                         cooling-max-level = <6>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 cpu_thermal {
  71                         /* milliseconds */
  72                         polling-delay-passive = <250>;
  73                         polling-delay = <1000>;
  74                         thermal-sensors = <&rtp>;
  75
  76                         cooling-maps {
  77                                 map0 {
  78                                         trip = <&cpu_alert0>;
  79                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  80                                 };
  81                         };
  82
  83                         trips {
  84                                 cpu_alert0: cpu_alert0 {
  85                                         /* milliCelsius */
  86                                         temperature = <850000>;
  87                                         hysteresis = <2000>;
  88                                         type = "passive";
  89                                 };
  90
  91                                 cpu_crit: cpu_crit {
  92                                         /* milliCelsius */
  93                                         temperature = <100000>;
  94                                         hysteresis = <2000>;
  95                                         type = "critical";
  96                                 };
  97                         };
  98                 };
  99         };
 100
 101         memory {
 102                 reg = <0x40000000 0x20000000>;
 103         };
 104
 105         clocks {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 /*
 111                  * This is a dummy clock, to be used as placeholder on
 112                  * other mux clocks when a specific parent clock is not
 113                  * yet implemented. It should be dropped when the driver
 114                  * is complete.
 115                  */
 116                 dummy: dummy {
 117                         #clock-cells = <0>;
 118                         compatible = "fixed-clock";
 119                         clock-frequency = <0>;
 120                 };
 121
 122                 osc24M: clk@01c20050 {
 123                         #clock-cells = <0>;
 124                         compatible = "allwinner,sun4i-a10-osc-clk";
 125                         reg = <0x01c20050 0x4>;
 126                         clock-frequency = <24000000>;
 127                         clock-output-names = "osc24M";
 128                 };
 129
 130                 osc32k: clk@0 {
 131                         #clock-cells = <0>;
 132                         compatible = "fixed-clock";
 133                         clock-frequency = <32768>;
 134                         clock-output-names = "osc32k";
 135                 };
 136
 137                 pll1: clk@01c20000 {
 138                         #clock-cells = <0>;
 139                         compatible = "allwinner,sun4i-a10-pll1-clk";
 140                         reg = <0x01c20000 0x4>;
 141                         clocks = <&osc24M>;
 142                         clock-output-names = "pll1";
 143                 };
 144
 145                 pll4: clk@01c20018 {
 146                         #clock-cells = <0>;
 147                         compatible = "allwinner,sun4i-a10-pll1-clk";
 148                         reg = <0x01c20018 0x4>;
 149                         clocks = <&osc24M>;
 150                         clock-output-names = "pll4";
 151                 };
 152
 153                 pll5: clk@01c20020 {
 154                         #clock-cells = <1>;
 155                         compatible = "allwinner,sun4i-a10-pll5-clk";
 156                         reg = <0x01c20020 0x4>;
 157                         clocks = <&osc24M>;
 158                         clock-output-names = "pll5_ddr", "pll5_other";
 159                 };
 160
 161                 pll6: clk@01c20028 {
 162                         #clock-cells = <1>;
 163                         compatible = "allwinner,sun4i-a10-pll6-clk";
 164                         reg = <0x01c20028 0x4>;
 165                         clocks = <&osc24M>;
 166                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 167                 };
 168
 169                 /* dummy is 200M */
 170                 cpu: cpu@01c20054 {
 171                         #clock-cells = <0>;
 172                         compatible = "allwinner,sun4i-a10-cpu-clk";
 173                         reg = <0x01c20054 0x4>;
 174                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 175                         clock-output-names = "cpu";
 176                 };
 177
 178                 axi: axi@01c20054 {
 179                         #clock-cells = <0>;
 180                         compatible = "allwinner,sun4i-a10-axi-clk";
 181                         reg = <0x01c20054 0x4>;
 182                         clocks = <&cpu>;
 183                         clock-output-names = "axi";
 184                 };
 185
 186                 axi_gates: clk@01c2005c {
 187                         #clock-cells = <1>;
 188                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 189                         reg = <0x01c2005c 0x4>;
 190                         clocks = <&axi>;
 191                         clock-output-names = "axi_dram";
 192                 };
 193
 194                 ahb: ahb@01c20054 {
 195                         #clock-cells = <0>;
 196                         compatible = "allwinner,sun4i-a10-ahb-clk";
 197                         reg = <0x01c20054 0x4>;
 198                         clocks = <&axi>;
 199                         clock-output-names = "ahb";
 200                 };
 201
 202                 ahb_gates: clk@01c20060 {
 203                         #clock-cells = <1>;
 204                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 205                         reg = <0x01c20060 0x8>;
 206                         clocks = <&ahb>;
 207                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 208                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 209                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 210                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
 211                                 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
 212                                 "ahb_de_fe", "ahb_iep", "ahb_mali400";
 213                 };
 214
 215                 apb0: apb0@01c20054 {
 216                         #clock-cells = <0>;
 217                         compatible = "allwinner,sun4i-a10-apb0-clk";
 218                         reg = <0x01c20054 0x4>;
 219                         clocks = <&ahb>;
 220                         clock-output-names = "apb0";
 221                 };
 222
 223                 apb0_gates: clk@01c20068 {
 224                         #clock-cells = <1>;
 225                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 226                         reg = <0x01c20068 0x4>;
 227                         clocks = <&apb0>;
 228                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 229                 };
 230
 231                 apb1: clk@01c20058 {
 232                         #clock-cells = <0>;
 233                         compatible = "allwinner,sun4i-a10-apb1-clk";
 234                         reg = <0x01c20058 0x4>;
 235                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 236                         clock-output-names = "apb1";
 237                 };
 238
 239                 apb1_gates: clk@01c2006c {
 240                         #clock-cells = <1>;
 241                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 242                         reg = <0x01c2006c 0x4>;
 243                         clocks = <&apb1>;
 244                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 245                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
 246                 };
 247
 248                 nand_clk: clk@01c20080 {
 249                         #clock-cells = <0>;
 250                         compatible = "allwinner,sun4i-a10-mod0-clk";
 251                         reg = <0x01c20080 0x4>;
 252                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 253                         clock-output-names = "nand";
 254                 };
 255
 256                 ms_clk: clk@01c20084 {
 257                         #clock-cells = <0>;
 258                         compatible = "allwinner,sun4i-a10-mod0-clk";
 259                         reg = <0x01c20084 0x4>;
 260                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 261                         clock-output-names = "ms";
 262                 };
 263
 264                 mmc0_clk: clk@01c20088 {
 265                         #clock-cells = <0>;
 266                         compatible = "allwinner,sun4i-a10-mod0-clk";
 267                         reg = <0x01c20088 0x4>;
 268                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 269                         clock-output-names = "mmc0";
 270                 };
 271
 272                 mmc1_clk: clk@01c2008c {
 273                         #clock-cells = <0>;
 274                         compatible = "allwinner,sun4i-a10-mod0-clk";
 275                         reg = <0x01c2008c 0x4>;
 276                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 277                         clock-output-names = "mmc1";
 278                 };
 279
 280                 mmc2_clk: clk@01c20090 {
 281                         #clock-cells = <0>;
 282                         compatible = "allwinner,sun4i-a10-mod0-clk";
 283                         reg = <0x01c20090 0x4>;
 284                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 285                         clock-output-names = "mmc2";
 286                 };
 287
 288                 ts_clk: clk@01c20098 {
 289                         #clock-cells = <0>;
 290                         compatible = "allwinner,sun4i-a10-mod0-clk";
 291                         reg = <0x01c20098 0x4>;
 292                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 293                         clock-output-names = "ts";
 294                 };
 295
 296                 ss_clk: clk@01c2009c {
 297                         #clock-cells = <0>;
 298                         compatible = "allwinner,sun4i-a10-mod0-clk";
 299                         reg = <0x01c2009c 0x4>;
 300                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 301                         clock-output-names = "ss";
 302                 };
 303
 304                 spi0_clk: clk@01c200a0 {
 305                         #clock-cells = <0>;
 306                         compatible = "allwinner,sun4i-a10-mod0-clk";
 307                         reg = <0x01c200a0 0x4>;
 308                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 309                         clock-output-names = "spi0";
 310                 };
 311
 312                 spi1_clk: clk@01c200a4 {
 313                         #clock-cells = <0>;
 314                         compatible = "allwinner,sun4i-a10-mod0-clk";
 315                         reg = <0x01c200a4 0x4>;
 316                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 317                         clock-output-names = "spi1";
 318                 };
 319
 320                 spi2_clk: clk@01c200a8 {
 321                         #clock-cells = <0>;
 322                         compatible = "allwinner,sun4i-a10-mod0-clk";
 323                         reg = <0x01c200a8 0x4>;
 324                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 325                         clock-output-names = "spi2";
 326                 };
 327
 328                 ir0_clk: clk@01c200b0 {
 329                         #clock-cells = <0>;
 330                         compatible = "allwinner,sun4i-a10-mod0-clk";
 331                         reg = <0x01c200b0 0x4>;
 332                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 333                         clock-output-names = "ir0";
 334                 };
 335
 336                 usb_clk: clk@01c200cc {
 337                         #clock-cells = <1>;
 338                         #reset-cells = <1>;
 339                         compatible = "allwinner,sun5i-a13-usb-clk";
 340                         reg = <0x01c200cc 0x4>;
 341                         clocks = <&pll6 1>;
 342                         clock-output-names = "usb_ohci0", "usb_phy";
 343                 };
 344
 345                 mbus_clk: clk@01c2015c {
 346                         #clock-cells = <0>;
 347                         compatible = "allwinner,sun5i-a13-mbus-clk";
 348                         reg = <0x01c2015c 0x4>;
 349                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 350                         clock-output-names = "mbus";
 351                 };
 352         };
 353
 354         soc@01c00000 {
 355                 compatible = "simple-bus";
 356                 #address-cells = <1>;
 357                 #size-cells = <1>;
 358                 ranges;
 359
 360                 dma: dma-controller@01c02000 {
 361                         compatible = "allwinner,sun4i-a10-dma";
 362                         reg = <0x01c02000 0x1000>;
 363                         interrupts = <27>;
 364                         clocks = <&ahb_gates 6>;
 365                         #dma-cells = <2>;
 366                 };
 367
 368                 spi0: spi@01c05000 {
 369                         compatible = "allwinner,sun4i-a10-spi";
 370                         reg = <0x01c05000 0x1000>;
 371                         interrupts = <10>;
 372                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 373                         clock-names = "ahb", "mod";
 374                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 375                                <&dma SUN4I_DMA_DEDICATED 26>;
 376                         dma-names = "rx", "tx";
 377                         status = "disabled";
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                 };
 381
 382                 spi1: spi@01c06000 {
 383                         compatible = "allwinner,sun4i-a10-spi";
 384                         reg = <0x01c06000 0x1000>;
 385                         interrupts = <11>;
 386                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 387                         clock-names = "ahb", "mod";
 388                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 389                                <&dma SUN4I_DMA_DEDICATED 8>;
 390                         dma-names = "rx", "tx";
 391                         status = "disabled";
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                 };
 395
 396                 mmc0: mmc@01c0f000 {
 397                         compatible = "allwinner,sun5i-a13-mmc";
 398                         reg = <0x01c0f000 0x1000>;
 399                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 400                         clock-names = "ahb", "mmc";
 401                         interrupts = <32>;
 402                         status = "disabled";
 403                 };
 404
 405                 mmc2: mmc@01c11000 {
 406                         compatible = "allwinner,sun5i-a13-mmc";
 407                         reg = <0x01c11000 0x1000>;
 408                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 409                         clock-names = "ahb", "mmc";
 410                         interrupts = <34>;
 411                         status = "disabled";
 412                 };
 413
 414                 usbphy: phy@01c13400 {
 415                         #phy-cells = <1>;
 416                         compatible = "allwinner,sun5i-a13-usb-phy";
 417                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 418                         reg-names = "phy_ctrl", "pmu1";
 419                         clocks = <&usb_clk 8>;
 420                         clock-names = "usb_phy";
 421                         resets = <&usb_clk 0>, <&usb_clk 1>;
 422                         reset-names = "usb0_reset", "usb1_reset";
 423                         status = "disabled";
 424                 };
 425
 426                 ehci0: usb@01c14000 {
 427                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 428                         reg = <0x01c14000 0x100>;
 429                         interrupts = <39>;
 430                         clocks = <&ahb_gates 1>;
 431                         phys = <&usbphy 1>;
 432                         phy-names = "usb";
 433                         status = "disabled";
 434                 };
 435
 436                 ohci0: usb@01c14400 {
 437                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 438                         reg = <0x01c14400 0x100>;
 439                         interrupts = <40>;
 440                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 441                         phys = <&usbphy 1>;
 442                         phy-names = "usb";
 443                         status = "disabled";
 444                 };
 445
 446                 spi2: spi@01c17000 {
 447                         compatible = "allwinner,sun4i-a10-spi";
 448                         reg = <0x01c17000 0x1000>;
 449                         interrupts = <12>;
 450                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 451                         clock-names = "ahb", "mod";
 452                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 453                                <&dma SUN4I_DMA_DEDICATED 28>;
 454                         dma-names = "rx", "tx";
 455                         status = "disabled";
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                 };
 459
 460                 intc: interrupt-controller@01c20400 {
 461                         compatible = "allwinner,sun4i-a10-ic";
 462                         reg = <0x01c20400 0x400>;
 463                         interrupt-controller;
 464                         #interrupt-cells = <1>;
 465                 };
 466
 467                 pio: pinctrl@01c20800 {
 468                         compatible = "allwinner,sun5i-a13-pinctrl";
 469                         reg = <0x01c20800 0x400>;
 470                         interrupts = <28>;
 471                         clocks = <&apb0_gates 5>;
 472                         gpio-controller;
 473                         interrupt-controller;
 474                         #interrupt-cells = <2>;
 475                         #size-cells = <0>;
 476                         #gpio-cells = <3>;
 477
 478                         uart1_pins_a: uart1@0 {
 479                                 allwinner,pins = "PE10", "PE11";
 480                                 allwinner,function = "uart1";
 481                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 482                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 483                         };
 484
 485                         uart1_pins_b: uart1@1 {
 486                                 allwinner,pins = "PG3", "PG4";
 487                                 allwinner,function = "uart1";
 488                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 489                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 490                         };
 491
 492                         i2c0_pins_a: i2c0@0 {
 493                                 allwinner,pins = "PB0", "PB1";
 494                                 allwinner,function = "i2c0";
 495                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 496                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 497                         };
 498
 499                         i2c1_pins_a: i2c1@0 {
 500                                 allwinner,pins = "PB15", "PB16";
 501                                 allwinner,function = "i2c1";
 502                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 503                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 504                         };
 505
 506                         i2c2_pins_a: i2c2@0 {
 507                                 allwinner,pins = "PB17", "PB18";
 508                                 allwinner,function = "i2c2";
 509                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 510                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 511                         };
 512
 513                         mmc0_pins_a: mmc0@0 {
 514                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 515                                 allwinner,function = "mmc0";
 516                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 517                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 518                         };
 519                 };
 520
 521                 timer@01c20c00 {
 522                         compatible = "allwinner,sun4i-a10-timer";
 523                         reg = <0x01c20c00 0x90>;
 524                         interrupts = <22>;
 525                         clocks = <&osc24M>;
 526                 };
 527
 528                 wdt: watchdog@01c20c90 {
 529                         compatible = "allwinner,sun4i-a10-wdt";
 530                         reg = <0x01c20c90 0x10>;
 531                 };
 532
 533                 lradc: lradc@01c22800 {
 534                         compatible = "allwinner,sun4i-a10-lradc-keys";
 535                         reg = <0x01c22800 0x100>;
 536                         interrupts = <31>;
 537                         status = "disabled";
 538                 };
 539
 540                 sid: eeprom@01c23800 {
 541                         compatible = "allwinner,sun4i-a10-sid";
 542                         reg = <0x01c23800 0x10>;
 543                 };
 544
 545                 rtp: rtp@01c25000 {
 546                         compatible = "allwinner,sun4i-a10-ts";
 547                         reg = <0x01c25000 0x100>;
 548                         interrupts = <29>;
 549                         #thermal-sensor-cells = <0>;
 550                 };
 551
 552                 uart1: serial@01c28400 {
 553                         compatible = "snps,dw-apb-uart";
 554                         reg = <0x01c28400 0x400>;
 555                         interrupts = <2>;
 556                         reg-shift = <2>;
 557                         reg-io-width = <4>;
 558                         clocks = <&apb1_gates 17>;
 559                         status = "disabled";
 560                 };
 561
 562                 uart3: serial@01c28c00 {
 563                         compatible = "snps,dw-apb-uart";
 564                         reg = <0x01c28c00 0x400>;
 565                         interrupts = <4>;
 566                         reg-shift = <2>;
 567                         reg-io-width = <4>;
 568                         clocks = <&apb1_gates 19>;
 569                         status = "disabled";
 570                 };
 571
 572                 i2c0: i2c@01c2ac00 {
 573                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 574                         reg = <0x01c2ac00 0x400>;
 575                         interrupts = <7>;
 576                         clocks = <&apb1_gates 0>;
 577                         status = "disabled";
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                 };
 581
 582                 i2c1: i2c@01c2b000 {
 583                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 584                         reg = <0x01c2b000 0x400>;
 585                         interrupts = <8>;
 586                         clocks = <&apb1_gates 1>;
 587                         status = "disabled";
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                 };
 591
 592                 i2c2: i2c@01c2b400 {
 593                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 594                         reg = <0x01c2b400 0x400>;
 595                         interrupts = <9>;
 596                         clocks = <&apb1_gates 2>;
 597                         status = "disabled";
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                 };
 601
 602                 timer@01c60000 {
 603                         compatible = "allwinner,sun5i-a13-hstimer";
 604                         reg = <0x01c60000 0x1000>;
 605                         interrupts = <82>, <83>;
 606                         clocks = <&ahb_gates 28>;
 607                 };
 608         };
 609 };