arch/arm/boot/dts/stm32mp157c.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci";
  33                 method = "smc";
  34                 cpu_off = <0x84000002>;
  35                 cpu_on = <0x84000003>;
  36         };
  37
  38         intc: interrupt-controller@a0021000 {
  39                 compatible = "arm,cortex-a7-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xa0021000 0x1000>,
  43                       <0xa0022000 0x2000>;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&intc>;
  53         };
  54
  55         clocks {
  56                 clk_hse: clk-hse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61
  62                 clk_hsi: clk-hsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <64000000>;
  66                 };
  67
  68                 clk_lse: clk-lse {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                 };
  73
  74                 clk_lsi: clk-lsi {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <32000>;
  78                 };
  79
  80                 clk_csi: clk-csi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <4000000>;
  84                 };
  85         };
  86
  87         soc {
  88                 compatible = "simple-bus";
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 interrupt-parent = <&intc>;
  92                 ranges;
  93
  94                 timers2: timer@40000000 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         compatible = "st,stm32-timers";
  98                         reg = <0x40000000 0x400>;
  99                         clocks = <&rcc TIM2_K>;
 100                         clock-names = "int";
 101                         dmas = <&dmamux1 18 0x400 0x1>,
 102                                <&dmamux1 19 0x400 0x1>,
 103                                <&dmamux1 20 0x400 0x1>,
 104                                <&dmamux1 21 0x400 0x1>,
 105                                <&dmamux1 22 0x400 0x1>;
 106                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 107                         status = "disabled";
 108
 109                         pwm {
 110                                 compatible = "st,stm32-pwm";
 111                                 status = "disabled";
 112                         };
 113
 114                         timer@1 {
 115                                 compatible = "st,stm32h7-timer-trigger";
 116                                 reg = <1>;
 117                                 status = "disabled";
 118                         };
 119                 };
 120
 121                 timers3: timer@40001000 {
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         compatible = "st,stm32-timers";
 125                         reg = <0x40001000 0x400>;
 126                         clocks = <&rcc TIM3_K>;
 127                         clock-names = "int";
 128                         dmas = <&dmamux1 23 0x400 0x1>,
 129                                <&dmamux1 24 0x400 0x1>,
 130                                <&dmamux1 25 0x400 0x1>,
 131                                <&dmamux1 26 0x400 0x1>,
 132                                <&dmamux1 27 0x400 0x1>,
 133                                <&dmamux1 28 0x400 0x1>;
 134                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 135                         status = "disabled";
 136
 137                         pwm {
 138                                 compatible = "st,stm32-pwm";
 139                                 status = "disabled";
 140                         };
 141
 142                         timer@2 {
 143                                 compatible = "st,stm32h7-timer-trigger";
 144                                 reg = <2>;
 145                                 status = "disabled";
 146                         };
 147                 };
 148
 149                 timers4: timer@40002000 {
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152                         compatible = "st,stm32-timers";
 153                         reg = <0x40002000 0x400>;
 154                         clocks = <&rcc TIM4_K>;
 155                         clock-names = "int";
 156                         dmas = <&dmamux1 29 0x400 0x1>,
 157                                <&dmamux1 30 0x400 0x1>,
 158                                <&dmamux1 31 0x400 0x1>,
 159                                <&dmamux1 32 0x400 0x1>;
 160                         dma-names = "ch1", "ch2", "ch3", "ch4";
 161                         status = "disabled";
 162
 163                         pwm {
 164                                 compatible = "st,stm32-pwm";
 165                                 status = "disabled";
 166                         };
 167
 168                         timer@3 {
 169                                 compatible = "st,stm32h7-timer-trigger";
 170                                 reg = <3>;
 171                                 status = "disabled";
 172                         };
 173                 };
 174
 175                 timers5: timer@40003000 {
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         compatible = "st,stm32-timers";
 179                         reg = <0x40003000 0x400>;
 180                         clocks = <&rcc TIM5_K>;
 181                         clock-names = "int";
 182                         dmas = <&dmamux1 55 0x400 0x1>,
 183                                <&dmamux1 56 0x400 0x1>,
 184                                <&dmamux1 57 0x400 0x1>,
 185                                <&dmamux1 58 0x400 0x1>,
 186                                <&dmamux1 59 0x400 0x1>,
 187                                <&dmamux1 60 0x400 0x1>;
 188                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 189                         status = "disabled";
 190
 191                         pwm {
 192                                 compatible = "st,stm32-pwm";
 193                                 status = "disabled";
 194                         };
 195
 196                         timer@4 {
 197                                 compatible = "st,stm32h7-timer-trigger";
 198                                 reg = <4>;
 199                                 status = "disabled";
 200                         };
 201                 };
 202
 203                 timers6: timer@40004000 {
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         compatible = "st,stm32-timers";
 207                         reg = <0x40004000 0x400>;
 208                         clocks = <&rcc TIM6_K>;
 209                         clock-names = "int";
 210                         dmas = <&dmamux1 69 0x400 0x1>;
 211                         dma-names = "up";
 212                         status = "disabled";
 213
 214                         timer@5 {
 215                                 compatible = "st,stm32h7-timer-trigger";
 216                                 reg = <5>;
 217                                 status = "disabled";
 218                         };
 219                 };
 220
 221                 timers7: timer@40005000 {
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224                         compatible = "st,stm32-timers";
 225                         reg = <0x40005000 0x400>;
 226                         clocks = <&rcc TIM7_K>;
 227                         clock-names = "int";
 228                         dmas = <&dmamux1 70 0x400 0x1>;
 229                         dma-names = "up";
 230                         status = "disabled";
 231
 232                         timer@6 {
 233                                 compatible = "st,stm32h7-timer-trigger";
 234                                 reg = <6>;
 235                                 status = "disabled";
 236                         };
 237                 };
 238
 239                 timers12: timer@40006000 {
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         compatible = "st,stm32-timers";
 243                         reg = <0x40006000 0x400>;
 244                         clocks = <&rcc TIM12_K>;
 245                         clock-names = "int";
 246                         status = "disabled";
 247
 248                         pwm {
 249                                 compatible = "st,stm32-pwm";
 250                                 status = "disabled";
 251                         };
 252
 253                         timer@11 {
 254                                 compatible = "st,stm32h7-timer-trigger";
 255                                 reg = <11>;
 256                                 status = "disabled";
 257                         };
 258                 };
 259
 260                 timers13: timer@40007000 {
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         compatible = "st,stm32-timers";
 264                         reg = <0x40007000 0x400>;
 265                         clocks = <&rcc TIM13_K>;
 266                         clock-names = "int";
 267                         status = "disabled";
 268
 269                         pwm {
 270                                 compatible = "st,stm32-pwm";
 271                                 status = "disabled";
 272                         };
 273
 274                         timer@12 {
 275                                 compatible = "st,stm32h7-timer-trigger";
 276                                 reg = <12>;
 277                                 status = "disabled";
 278                         };
 279                 };
 280
 281                 timers14: timer@40008000 {
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         compatible = "st,stm32-timers";
 285                         reg = <0x40008000 0x400>;
 286                         clocks = <&rcc TIM14_K>;
 287                         clock-names = "int";
 288                         status = "disabled";
 289
 290                         pwm {
 291                                 compatible = "st,stm32-pwm";
 292                                 status = "disabled";
 293                         };
 294
 295                         timer@13 {
 296                                 compatible = "st,stm32h7-timer-trigger";
 297                                 reg = <13>;
 298                                 status = "disabled";
 299                         };
 300                 };
 301
 302                 lptimer1: timer@40009000 {
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         compatible = "st,stm32-lptimer";
 306                         reg = <0x40009000 0x400>;
 307                         clocks = <&rcc LPTIM1_K>;
 308                         clock-names = "mux";
 309                         status = "disabled";
 310
 311                         pwm {
 312                                 compatible = "st,stm32-pwm-lp";
 313                                 #pwm-cells = <3>;
 314                                 status = "disabled";
 315                         };
 316
 317                         trigger@0 {
 318                                 compatible = "st,stm32-lptimer-trigger";
 319                                 reg = <0>;
 320                                 status = "disabled";
 321                         };
 322
 323                         counter {
 324                                 compatible = "st,stm32-lptimer-counter";
 325                                 status = "disabled";
 326                         };
 327                 };
 328
 329                 spi2: spi@4000b000 {
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         compatible = "st,stm32h7-spi";
 333                         reg = <0x4000b000 0x400>;
 334                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&rcc SPI2_K>;
 336                         resets = <&rcc SPI2_R>;
 337                         dmas = <&dmamux1 39 0x400 0x05>,
 338                                <&dmamux1 40 0x400 0x05>;
 339                         dma-names = "rx", "tx";
 340                         status = "disabled";
 341                 };
 342
 343                 spi3: spi@4000c000 {
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         compatible = "st,stm32h7-spi";
 347                         reg = <0x4000c000 0x400>;
 348                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 349                         clocks = <&rcc SPI3_K>;
 350                         resets = <&rcc SPI3_R>;
 351                         dmas = <&dmamux1 61 0x400 0x05>,
 352                                <&dmamux1 62 0x400 0x05>;
 353                         dma-names = "rx", "tx";
 354                         status = "disabled";
 355                 };
 356
 357                 usart2: serial@4000e000 {
 358                         compatible = "st,stm32h7-uart";
 359                         reg = <0x4000e000 0x400>;
 360                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 361                         clocks = <&rcc USART2_K>;
 362                         status = "disabled";
 363                 };
 364
 365                 usart3: serial@4000f000 {
 366                         compatible = "st,stm32h7-uart";
 367                         reg = <0x4000f000 0x400>;
 368                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&rcc USART3_K>;
 370                         status = "disabled";
 371                 };
 372
 373                 uart4: serial@40010000 {
 374                         compatible = "st,stm32h7-uart";
 375                         reg = <0x40010000 0x400>;
 376                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 377                         clocks = <&rcc UART4_K>;
 378                         status = "disabled";
 379                 };
 380
 381                 uart5: serial@40011000 {
 382                         compatible = "st,stm32h7-uart";
 383                         reg = <0x40011000 0x400>;
 384                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 385                         clocks = <&rcc UART5_K>;
 386                         status = "disabled";
 387                 };
 388
 389                 i2c1: i2c@40012000 {
 390                         compatible = "st,stm32f7-i2c";
 391                         reg = <0x40012000 0x400>;
 392                         interrupt-names = "event", "error";
 393                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 394                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 395                         clocks = <&rcc I2C1_K>;
 396                         resets = <&rcc I2C1_R>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         status = "disabled";
 400                 };
 401
 402                 i2c2: i2c@40013000 {
 403                         compatible = "st,stm32f7-i2c";
 404                         reg = <0x40013000 0x400>;
 405                         interrupt-names = "event", "error";
 406                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 407                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&rcc I2C2_K>;
 409                         resets = <&rcc I2C2_R>;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         status = "disabled";
 413                 };
 414
 415                 i2c3: i2c@40014000 {
 416                         compatible = "st,stm32f7-i2c";
 417                         reg = <0x40014000 0x400>;
 418                         interrupt-names = "event", "error";
 419                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 420                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&rcc I2C3_K>;
 422                         resets = <&rcc I2C3_R>;
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                         status = "disabled";
 426                 };
 427
 428                 i2c5: i2c@40015000 {
 429                         compatible = "st,stm32f7-i2c";
 430                         reg = <0x40015000 0x400>;
 431                         interrupt-names = "event", "error";
 432                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 433                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&rcc I2C5_K>;
 435                         resets = <&rcc I2C5_R>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         status = "disabled";
 439                 };
 440
 441                 cec: cec@40016000 {
 442                         compatible = "st,stm32-cec";
 443                         reg = <0x40016000 0x400>;
 444                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&rcc CEC_K>, <&clk_lse>;
 446                         clock-names = "cec", "hdmi-cec";
 447                         status = "disabled";
 448                 };
 449
 450                 dac: dac@40017000 {
 451                         compatible = "st,stm32h7-dac-core";
 452                         reg = <0x40017000 0x400>;
 453                         clocks = <&rcc DAC12>;
 454                         clock-names = "pclk";
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         status = "disabled";
 458
 459                         dac1: dac@1 {
 460                                 compatible = "st,stm32-dac";
 461                                 #io-channels-cells = <1>;
 462                                 reg = <1>;
 463                                 status = "disabled";
 464                         };
 465
 466                         dac2: dac@2 {
 467                                 compatible = "st,stm32-dac";
 468                                 #io-channels-cells = <1>;
 469                                 reg = <2>;
 470                                 status = "disabled";
 471                         };
 472                 };
 473
 474                 uart7: serial@40018000 {
 475                         compatible = "st,stm32h7-uart";
 476                         reg = <0x40018000 0x400>;
 477                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&rcc UART7_K>;
 479                         status = "disabled";
 480                 };
 481
 482                 uart8: serial@40019000 {
 483                         compatible = "st,stm32h7-uart";
 484                         reg = <0x40019000 0x400>;
 485                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 486                         clocks = <&rcc UART8_K>;
 487                         status = "disabled";
 488                 };
 489
 490                 timers1: timer@44000000 {
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         compatible = "st,stm32-timers";
 494                         reg = <0x44000000 0x400>;
 495                         clocks = <&rcc TIM1_K>;
 496                         clock-names = "int";
 497                         dmas = <&dmamux1 11 0x400 0x1>,
 498                                <&dmamux1 12 0x400 0x1>,
 499                                <&dmamux1 13 0x400 0x1>,
 500                                <&dmamux1 14 0x400 0x1>,
 501                                <&dmamux1 15 0x400 0x1>,
 502                                <&dmamux1 16 0x400 0x1>,
 503                                <&dmamux1 17 0x400 0x1>;
 504                         dma-names = "ch1", "ch2", "ch3", "ch4",
 505                                     "up", "trig", "com";
 506                         status = "disabled";
 507
 508                         pwm {
 509                                 compatible = "st,stm32-pwm";
 510                                 status = "disabled";
 511                         };
 512
 513                         timer@0 {
 514                                 compatible = "st,stm32h7-timer-trigger";
 515                                 reg = <0>;
 516                                 status = "disabled";
 517                         };
 518                 };
 519
 520                 timers8: timer@44001000 {
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         compatible = "st,stm32-timers";
 524                         reg = <0x44001000 0x400>;
 525                         clocks = <&rcc TIM8_K>;
 526                         clock-names = "int";
 527                         dmas = <&dmamux1 47 0x400 0x1>,
 528                                <&dmamux1 48 0x400 0x1>,
 529                                <&dmamux1 49 0x400 0x1>,
 530                                <&dmamux1 50 0x400 0x1>,
 531                                <&dmamux1 51 0x400 0x1>,
 532                                <&dmamux1 52 0x400 0x1>,
 533                                <&dmamux1 53 0x400 0x1>;
 534                         dma-names = "ch1", "ch2", "ch3", "ch4",
 535                                     "up", "trig", "com";
 536                         status = "disabled";
 537
 538                         pwm {
 539                                 compatible = "st,stm32-pwm";
 540                                 status = "disabled";
 541                         };
 542
 543                         timer@7 {
 544                                 compatible = "st,stm32h7-timer-trigger";
 545                                 reg = <7>;
 546                                 status = "disabled";
 547                         };
 548                 };
 549
 550                 usart6: serial@44003000 {
 551                         compatible = "st,stm32h7-uart";
 552                         reg = <0x44003000 0x400>;
 553                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&rcc USART6_K>;
 555                         status = "disabled";
 556                 };
 557
 558                 spi1: spi@44004000 {
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         compatible = "st,stm32h7-spi";
 562                         reg = <0x44004000 0x400>;
 563                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&rcc SPI1_K>;
 565                         resets = <&rcc SPI1_R>;
 566                         dmas = <&dmamux1 37 0x400 0x05>,
 567                                <&dmamux1 38 0x400 0x05>;
 568                         dma-names = "rx", "tx";
 569                         status = "disabled";
 570                 };
 571
 572                 spi4: spi@44005000 {
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                         compatible = "st,stm32h7-spi";
 576                         reg = <0x44005000 0x400>;
 577                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&rcc SPI4_K>;
 579                         resets = <&rcc SPI4_R>;
 580                         dmas = <&dmamux1 83 0x400 0x05>,
 581                                <&dmamux1 84 0x400 0x05>;
 582                         dma-names = "rx", "tx";
 583                         status = "disabled";
 584                 };
 585
 586                 timers15: timer@44006000 {
 587                         #address-cells = <1>;
 588                         #size-cells = <0>;
 589                         compatible = "st,stm32-timers";
 590                         reg = <0x44006000 0x400>;
 591                         clocks = <&rcc TIM15_K>;
 592                         clock-names = "int";
 593                         dmas = <&dmamux1 105 0x400 0x1>,
 594                                <&dmamux1 106 0x400 0x1>,
 595                                <&dmamux1 107 0x400 0x1>,
 596                                <&dmamux1 108 0x400 0x1>;
 597                         dma-names = "ch1", "up", "trig", "com";
 598                         status = "disabled";
 599
 600                         pwm {
 601                                 compatible = "st,stm32-pwm";
 602                                 status = "disabled";
 603                         };
 604
 605                         timer@14 {
 606                                 compatible = "st,stm32h7-timer-trigger";
 607                                 reg = <14>;
 608                                 status = "disabled";
 609                         };
 610                 };
 611
 612                 timers16: timer@44007000 {
 613                         #address-cells = <1>;
 614                         #size-cells = <0>;
 615                         compatible = "st,stm32-timers";
 616                         reg = <0x44007000 0x400>;
 617                         clocks = <&rcc TIM16_K>;
 618                         clock-names = "int";
 619                         dmas = <&dmamux1 109 0x400 0x1>,
 620                                <&dmamux1 110 0x400 0x1>;
 621                         dma-names = "ch1", "up";
 622                         status = "disabled";
 623
 624                         pwm {
 625                                 compatible = "st,stm32-pwm";
 626                                 status = "disabled";
 627                         };
 628                         timer@15 {
 629                                 compatible = "st,stm32h7-timer-trigger";
 630                                 reg = <15>;
 631                                 status = "disabled";
 632                         };
 633                 };
 634
 635                 timers17: timer@44008000 {
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                         compatible = "st,stm32-timers";
 639                         reg = <0x44008000 0x400>;
 640                         clocks = <&rcc TIM17_K>;
 641                         clock-names = "int";
 642                         dmas = <&dmamux1 111 0x400 0x1>,
 643                                <&dmamux1 112 0x400 0x1>;
 644                         dma-names = "ch1", "up";
 645                         status = "disabled";
 646
 647                         pwm {
 648                                 compatible = "st,stm32-pwm";
 649                                 status = "disabled";
 650                         };
 651
 652                         timer@16 {
 653                                 compatible = "st,stm32h7-timer-trigger";
 654                                 reg = <16>;
 655                                 status = "disabled";
 656                         };
 657                 };
 658
 659                 spi5: spi@44009000 {
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         compatible = "st,stm32h7-spi";
 663                         reg = <0x44009000 0x400>;
 664                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&rcc SPI5_K>;
 666                         resets = <&rcc SPI5_R>;
 667                         dmas = <&dmamux1 85 0x400 0x05>,
 668                                <&dmamux1 86 0x400 0x05>;
 669                         dma-names = "rx", "tx";
 670                         status = "disabled";
 671                 };
 672
 673                 dfsdm: dfsdm@4400d000 {
 674                         compatible = "st,stm32mp1-dfsdm";
 675                         reg = <0x4400d000 0x800>;
 676                         clocks = <&rcc DFSDM_K>;
 677                         clock-names = "dfsdm";
 678                         #address-cells = <1>;
 679                         #size-cells = <0>;
 680                         status = "disabled";
 681
 682                         dfsdm0: filter@0 {
 683                                 compatible = "st,stm32-dfsdm-adc";
 684                                 #io-channel-cells = <1>;
 685                                 reg = <0>;
 686                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 687                                 dmas = <&dmamux1 101 0x400 0x01>;
 688                                 dma-names = "rx";
 689                                 status = "disabled";
 690                         };
 691
 692                         dfsdm1: filter@1 {
 693                                 compatible = "st,stm32-dfsdm-adc";
 694                                 #io-channel-cells = <1>;
 695                                 reg = <1>;
 696                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 697                                 dmas = <&dmamux1 102 0x400 0x01>;
 698                                 dma-names = "rx";
 699                                 status = "disabled";
 700                         };
 701
 702                         dfsdm2: filter@2 {
 703                                 compatible = "st,stm32-dfsdm-adc";
 704                                 #io-channel-cells = <1>;
 705                                 reg = <2>;
 706                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 707                                 dmas = <&dmamux1 103 0x400 0x01>;
 708                                 dma-names = "rx";
 709                                 status = "disabled";
 710                         };
 711
 712                         dfsdm3: filter@3 {
 713                                 compatible = "st,stm32-dfsdm-adc";
 714                                 #io-channel-cells = <1>;
 715                                 reg = <3>;
 716                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 717                                 dmas = <&dmamux1 104 0x400 0x01>;
 718                                 dma-names = "rx";
 719                                 status = "disabled";
 720                         };
 721
 722                         dfsdm4: filter@4 {
 723                                 compatible = "st,stm32-dfsdm-adc";
 724                                 #io-channel-cells = <1>;
 725                                 reg = <4>;
 726                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 727                                 dmas = <&dmamux1 91 0x400 0x01>;
 728                                 dma-names = "rx";
 729                                 status = "disabled";
 730                         };
 731
 732                         dfsdm5: filter@5 {
 733                                 compatible = "st,stm32-dfsdm-adc";
 734                                 #io-channel-cells = <1>;
 735                                 reg = <5>;
 736                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 737                                 dmas = <&dmamux1 92 0x400 0x01>;
 738                                 dma-names = "rx";
 739                                 status = "disabled";
 740                         };
 741                 };
 742
 743                 m_can1: can@4400e000 {
 744                         compatible = "bosch,m_can";
 745                         reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
 746                         reg-names = "m_can", "message_ram";
 747                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 749                         interrupt-names = "int0", "int1";
 750                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 751                         clock-names = "hclk", "cclk";
 752                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 753                         status = "disabled";
 754                 };
 755
 756                 m_can2: can@4400f000 {
 757                         compatible = "bosch,m_can";
 758                         reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
 759                         reg-names = "m_can", "message_ram";
 760                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 762                         interrupt-names = "int0", "int1";
 763                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 764                         clock-names = "hclk", "cclk";
 765                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 766                         status = "disabled";
 767                 };
 768
 769                 dma1: dma@48000000 {
 770                         compatible = "st,stm32-dma";
 771                         reg = <0x48000000 0x400>;
 772                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 773                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 774                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 775                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 776                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 777                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 778                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 779                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 780                         clocks = <&rcc DMA1>;
 781                         #dma-cells = <4>;
 782                         st,mem2mem;
 783                         dma-requests = <8>;
 784                 };
 785
 786                 dma2: dma@48001000 {
 787                         compatible = "st,stm32-dma";
 788                         reg = <0x48001000 0x400>;
 789                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 791                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 792                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 793                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 794                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 795                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 796                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 797                         clocks = <&rcc DMA2>;
 798                         #dma-cells = <4>;
 799                         st,mem2mem;
 800                         dma-requests = <8>;
 801                 };
 802
 803                 dmamux1: dma-router@48002000 {
 804                         compatible = "st,stm32h7-dmamux";
 805                         reg = <0x48002000 0x1c>;
 806                         #dma-cells = <3>;
 807                         dma-requests = <128>;
 808                         dma-masters = <&dma1 &dma2>;
 809                         dma-channels = <16>;
 810                         clocks = <&rcc DMAMUX>;
 811                 };
 812
 813                 adc: adc@48003000 {
 814                         compatible = "st,stm32mp1-adc-core";
 815                         reg = <0x48003000 0x400>;
 816                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 817                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 818                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
 819                         clock-names = "bus", "adc";
 820                         interrupt-controller;
 821                         #interrupt-cells = <1>;
 822                         #address-cells = <1>;
 823                         #size-cells = <0>;
 824                         status = "disabled";
 825
 826                         adc1: adc@0 {
 827                                 compatible = "st,stm32mp1-adc";
 828                                 #io-channel-cells = <1>;
 829                                 reg = <0x0>;
 830                                 interrupt-parent = <&adc>;
 831                                 interrupts = <0>;
 832                                 dmas = <&dmamux1 9 0x400 0x01>;
 833                                 dma-names = "rx";
 834                                 status = "disabled";
 835                         };
 836
 837                         adc2: adc@100 {
 838                                 compatible = "st,stm32mp1-adc";
 839                                 #io-channel-cells = <1>;
 840                                 reg = <0x100>;
 841                                 interrupt-parent = <&adc>;
 842                                 interrupts = <1>;
 843                                 dmas = <&dmamux1 10 0x400 0x01>;
 844                                 dma-names = "rx";
 845                                 status = "disabled";
 846                         };
 847                 };
 848
 849                 usbotg_hs: usb-otg@49000000 {
 850                         compatible = "snps,dwc2";
 851                         reg = <0x49000000 0x10000>;
 852                         clocks = <&rcc USBO_K>;
 853                         clock-names = "otg";
 854                         resets = <&rcc USBO_R>;
 855                         reset-names = "dwc2";
 856                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 857                         g-rx-fifo-size = <256>;
 858                         g-np-tx-fifo-size = <32>;
 859                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 860                         dr_mode = "otg";
 861                         status = "disabled";
 862                 };
 863
 864                 rcc: rcc@50000000 {
 865                         compatible = "st,stm32mp1-rcc", "syscon";
 866                         reg = <0x50000000 0x1000>;
 867                         #clock-cells = <1>;
 868                         #reset-cells = <1>;
 869                 };
 870
 871                 exti: interrupt-controller@5000d000 {
 872                         compatible = "st,stm32mp1-exti", "syscon";
 873                         interrupt-controller;
 874                         #interrupt-cells = <2>;
 875                         reg = <0x5000d000 0x400>;
 876                 };
 877
 878                 syscfg: syscon@50020000 {
 879                         compatible = "st,stm32mp157-syscfg", "syscon";
 880                         reg = <0x50020000 0x400>;
 881                 };
 882
 883                 lptimer2: timer@50021000 {
 884                         #address-cells = <1>;
 885                         #size-cells = <0>;
 886                         compatible = "st,stm32-lptimer";
 887                         reg = <0x50021000 0x400>;
 888                         clocks = <&rcc LPTIM2_K>;
 889                         clock-names = "mux";
 890                         status = "disabled";
 891
 892                         pwm {
 893                                 compatible = "st,stm32-pwm-lp";
 894                                 #pwm-cells = <3>;
 895                                 status = "disabled";
 896                         };
 897
 898                         trigger@1 {
 899                                 compatible = "st,stm32-lptimer-trigger";
 900                                 reg = <1>;
 901                                 status = "disabled";
 902                         };
 903
 904                         counter {
 905                                 compatible = "st,stm32-lptimer-counter";
 906                                 status = "disabled";
 907                         };
 908                 };
 909
 910                 lptimer3: timer@50022000 {
 911                         #address-cells = <1>;
 912                         #size-cells = <0>;
 913                         compatible = "st,stm32-lptimer";
 914                         reg = <0x50022000 0x400>;
 915                         clocks = <&rcc LPTIM3_K>;
 916                         clock-names = "mux";
 917                         status = "disabled";
 918
 919                         pwm {
 920                                 compatible = "st,stm32-pwm-lp";
 921                                 #pwm-cells = <3>;
 922                                 status = "disabled";
 923                         };
 924
 925                         trigger@2 {
 926                                 compatible = "st,stm32-lptimer-trigger";
 927                                 reg = <2>;
 928                                 status = "disabled";
 929                         };
 930                 };
 931
 932                 lptimer4: timer@50023000 {
 933                         compatible = "st,stm32-lptimer";
 934                         reg = <0x50023000 0x400>;
 935                         clocks = <&rcc LPTIM4_K>;
 936                         clock-names = "mux";
 937                         status = "disabled";
 938
 939                         pwm {
 940                                 compatible = "st,stm32-pwm-lp";
 941                                 #pwm-cells = <3>;
 942                                 status = "disabled";
 943                         };
 944                 };
 945
 946                 lptimer5: timer@50024000 {
 947                         compatible = "st,stm32-lptimer";
 948                         reg = <0x50024000 0x400>;
 949                         clocks = <&rcc LPTIM5_K>;
 950                         clock-names = "mux";
 951                         status = "disabled";
 952
 953                         pwm {
 954                                 compatible = "st,stm32-pwm-lp";
 955                                 #pwm-cells = <3>;
 956                                 status = "disabled";
 957                         };
 958                 };
 959
 960                 vrefbuf: vrefbuf@50025000 {
 961                         compatible = "st,stm32-vrefbuf";
 962                         reg = <0x50025000 0x8>;
 963                         regulator-min-microvolt = <1500000>;
 964                         regulator-max-microvolt = <2500000>;
 965                         clocks = <&rcc VREF>;
 966                         status = "disabled";
 967                 };
 968
 969                 cryp1: cryp@54001000 {
 970                         compatible = "st,stm32mp1-cryp";
 971                         reg = <0x54001000 0x400>;
 972                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 973                         clocks = <&rcc CRYP1>;
 974                         resets = <&rcc CRYP1_R>;
 975                         status = "disabled";
 976                 };
 977
 978                 hash1: hash@54002000 {
 979                         compatible = "st,stm32f756-hash";
 980                         reg = <0x54002000 0x400>;
 981                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 982                         clocks = <&rcc HASH1>;
 983                         resets = <&rcc HASH1_R>;
 984                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
 985                         dma-names = "in";
 986                         dma-maxburst = <2>;
 987                         status = "disabled";
 988                 };
 989
 990                 rng1: rng@54003000 {
 991                         compatible = "st,stm32-rng";
 992                         reg = <0x54003000 0x400>;
 993                         clocks = <&rcc RNG1_K>;
 994                         resets = <&rcc RNG1_R>;
 995                         status = "disabled";
 996                 };
 997
 998                 mdma1: dma@58000000 {
 999                         compatible = "st,stm32h7-mdma";
1000                         reg = <0x58000000 0x1000>;
1001                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1002                         clocks = <&rcc MDMA>;
1003                         #dma-cells = <5>;
1004                         dma-channels = <32>;
1005                         dma-requests = <48>;
1006                 };
1007
1008                 qspi: spi@58003000 {
1009                         compatible = "st,stm32f469-qspi";
1010                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1011                         reg-names = "qspi", "qspi_mm";
1012                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1013                         clocks = <&rcc QSPI_K>;
1014                         resets = <&rcc QSPI_R>;
1015                         status = "disabled";
1016                 };
1017
1018                 crc1: crc@58009000 {
1019                         compatible = "st,stm32f7-crc";
1020                         reg = <0x58009000 0x400>;
1021                         clocks = <&rcc CRC1>;
1022                         status = "disabled";
1023                 };
1024
1025                 stmmac_axi_config_0: stmmac-axi-config {
1026                         snps,wr_osr_lmt = <0x7>;
1027                         snps,rd_osr_lmt = <0x7>;
1028                         snps,blen = <0 0 0 0 16 8 4>;
1029                 };
1030
1031                 ethernet0: ethernet@5800a000 {
1032                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1033                         reg = <0x5800a000 0x2000>;
1034                         reg-names = "stmmaceth";
1035                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1036                         interrupt-names = "macirq";
1037                         clock-names = "stmmaceth",
1038                                       "mac-clk-tx",
1039                                       "mac-clk-rx",
1040                                       "ethstp",
1041                                       "syscfg-clk";
1042                         clocks = <&rcc ETHMAC>,
1043                                  <&rcc ETHTX>,
1044                                  <&rcc ETHRX>,
1045                                  <&rcc ETHSTP>,
1046                                  <&rcc SYSCFG>;
1047                         st,syscon = <&syscfg 0x4>;
1048                         snps,mixed-burst;
1049                         snps,pbl = <2>;
1050                         snps,axi-config = <&stmmac_axi_config_0>;
1051                         snps,tso;
1052                         status = "disabled";
1053                 };
1054
1055                 usbh_ohci: usbh-ohci@5800c000 {
1056                         compatible = "generic-ohci";
1057                         reg = <0x5800c000 0x1000>;
1058                         clocks = <&rcc USBH>;
1059                         resets = <&rcc USBH_R>;
1060                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1061                         status = "disabled";
1062                 };
1063
1064                 usbh_ehci: usbh-ehci@5800d000 {
1065                         compatible = "generic-ehci";
1066                         reg = <0x5800d000 0x1000>;
1067                         clocks = <&rcc USBH>;
1068                         resets = <&rcc USBH_R>;
1069                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1070                         companion = <&usbh_ohci>;
1071                         status = "disabled";
1072                 };
1073
1074                 dsi: dsi@5a000000 {
1075                         compatible = "st,stm32-dsi";
1076                         reg = <0x5a000000 0x800>;
1077                         clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1078                         clock-names = "pclk", "ref", "px_clk";
1079                         resets = <&rcc DSI_R>;
1080                         reset-names = "apb";
1081                         status = "disabled";
1082                 };
1083
1084                 ltdc: display-controller@5a001000 {
1085                         compatible = "st,stm32-ltdc";
1086                         reg = <0x5a001000 0x400>;
1087                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1088                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1089                         clocks = <&rcc LTDC_PX>;
1090                         clock-names = "lcd";
1091                         resets = <&rcc LTDC_R>;
1092                         status = "disabled";
1093                 };
1094
1095                 iwdg2: watchdog@5a002000 {
1096                         compatible = "st,stm32mp1-iwdg";
1097                         reg = <0x5a002000 0x400>;
1098                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1099                         clock-names = "pclk", "lsi";
1100                         status = "disabled";
1101                 };
1102
1103                 usbphyc: usbphyc@5a006000 {
1104                         #address-cells = <1>;
1105                         #size-cells = <0>;
1106                         compatible = "st,stm32mp1-usbphyc";
1107                         reg = <0x5a006000 0x1000>;
1108                         clocks = <&rcc USBPHY_K>;
1109                         resets = <&rcc USBPHY_R>;
1110                         status = "disabled";
1111
1112                         usbphyc_port0: usb-phy@0 {
1113                                 #phy-cells = <0>;
1114                                 reg = <0>;
1115                         };
1116
1117                         usbphyc_port1: usb-phy@1 {
1118                                 #phy-cells = <1>;
1119                                 reg = <1>;
1120                         };
1121                 };
1122
1123                 usart1: serial@5c000000 {
1124                         compatible = "st,stm32h7-uart";
1125                         reg = <0x5c000000 0x400>;
1126                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1127                         clocks = <&rcc USART1_K>;
1128                         status = "disabled";
1129                 };
1130
1131                 spi6: spi@5c001000 {
1132                         #address-cells = <1>;
1133                         #size-cells = <0>;
1134                         compatible = "st,stm32h7-spi";
1135                         reg = <0x5c001000 0x400>;
1136                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1137                         clocks = <&rcc SPI6_K>;
1138                         resets = <&rcc SPI6_R>;
1139                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1140                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1141                         dma-names = "rx", "tx";
1142                         status = "disabled";
1143                 };
1144
1145                 i2c4: i2c@5c002000 {
1146                         compatible = "st,stm32f7-i2c";
1147                         reg = <0x5c002000 0x400>;
1148                         interrupt-names = "event", "error";
1149                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1150                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1151                         clocks = <&rcc I2C4_K>;
1152                         resets = <&rcc I2C4_R>;
1153                         #address-cells = <1>;
1154                         #size-cells = <0>;
1155                         status = "disabled";
1156                 };
1157
1158                 rtc: rtc@5c004000 {
1159                         compatible = "st,stm32mp1-rtc";
1160                         reg = <0x5c004000 0x400>;
1161                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1162                         clock-names = "pclk", "rtc_ck";
1163                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1164                         status = "disabled";
1165                 };
1166
1167                 i2c6: i2c@5c009000 {
1168                         compatible = "st,stm32f7-i2c";
1169                         reg = <0x5c009000 0x400>;
1170                         interrupt-names = "event", "error";
1171                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1172                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1173                         clocks = <&rcc I2C6_K>;
1174                         resets = <&rcc I2C6_R>;
1175                         #address-cells = <1>;
1176                         #size-cells = <0>;
1177                         status = "disabled";
1178                 };
1179         };
1180 };