2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f7-rcc.h>
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
65 compatible = "fixed-clock";
66 clock-frequency = <32000>;
69 clk_i2s_ckin: clk-i2s-ckin {
71 compatible = "fixed-clock";
72 clock-frequency = <48000000>;
77 timer2: timer@40000000 {
78 compatible = "st,stm32-timer";
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
85 timers2: timers@40000000 {
88 compatible = "st,stm32-timers";
89 reg = <0x40000000 0x400>;
90 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
95 compatible = "st,stm32-pwm";
100 compatible = "st,stm32-timer-trigger";
106 timer3: timer@40000400 {
107 compatible = "st,stm32-timer";
108 reg = <0x40000400 0x400>;
110 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
114 timers3: timers@40000400 {
115 #address-cells = <1>;
117 compatible = "st,stm32-timers";
118 reg = <0x40000400 0x400>;
119 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
124 compatible = "st,stm32-pwm";
129 compatible = "st,stm32-timer-trigger";
135 timer4: timer@40000800 {
136 compatible = "st,stm32-timer";
137 reg = <0x40000800 0x400>;
139 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
143 timers4: timers@40000800 {
144 #address-cells = <1>;
146 compatible = "st,stm32-timers";
147 reg = <0x40000800 0x400>;
148 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
153 compatible = "st,stm32-pwm";
158 compatible = "st,stm32-timer-trigger";
164 timer5: timer@40000c00 {
165 compatible = "st,stm32-timer";
166 reg = <0x40000c00 0x400>;
168 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 timers5: timers@40000c00 {
172 #address-cells = <1>;
174 compatible = "st,stm32-timers";
175 reg = <0x40000C00 0x400>;
176 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
181 compatible = "st,stm32-pwm";
186 compatible = "st,stm32-timer-trigger";
192 timer6: timer@40001000 {
193 compatible = "st,stm32-timer";
194 reg = <0x40001000 0x400>;
196 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
200 timers6: timers@40001000 {
201 #address-cells = <1>;
203 compatible = "st,stm32-timers";
204 reg = <0x40001000 0x400>;
205 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
210 compatible = "st,stm32-timer-trigger";
216 timer7: timer@40001400 {
217 compatible = "st,stm32-timer";
218 reg = <0x40001400 0x400>;
220 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
224 timers7: timers@40001400 {
225 #address-cells = <1>;
227 compatible = "st,stm32-timers";
228 reg = <0x40001400 0x400>;
229 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
234 compatible = "st,stm32-timer-trigger";
240 timers12: timers@40001800 {
241 #address-cells = <1>;
243 compatible = "st,stm32-timers";
244 reg = <0x40001800 0x400>;
245 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
250 compatible = "st,stm32-pwm";
255 compatible = "st,stm32-timer-trigger";
261 timers13: timers@40001c00 {
262 #address-cells = <1>;
264 compatible = "st,stm32-timers";
265 reg = <0x40001C00 0x400>;
266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
271 compatible = "st,stm32-pwm";
276 timers14: timers@40002000 {
277 #address-cells = <1>;
279 compatible = "st,stm32-timers";
280 reg = <0x40002000 0x400>;
281 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
286 compatible = "st,stm32-pwm";
292 compatible = "st,stm32-rtc";
293 reg = <0x40002800 0x400>;
294 clocks = <&rcc 1 CLK_RTC>;
295 clock-names = "ck_rtc";
296 assigned-clocks = <&rcc 1 CLK_RTC>;
297 assigned-clock-parents = <&rcc 1 CLK_LSE>;
298 interrupt-parent = <&exti>;
300 interrupt-names = "alarm";
301 st,syscfg = <&pwrcfg>;
305 usart2: serial@40004400 {
306 compatible = "st,stm32f7-uart";
307 reg = <0x40004400 0x400>;
309 clocks = <&rcc 1 CLK_USART2>;
313 usart3: serial@40004800 {
314 compatible = "st,stm32f7-uart";
315 reg = <0x40004800 0x400>;
317 clocks = <&rcc 1 CLK_USART3>;
321 usart4: serial@40004c00 {
322 compatible = "st,stm32f7-uart";
323 reg = <0x40004c00 0x400>;
325 clocks = <&rcc 1 CLK_UART4>;
329 usart5: serial@40005000 {
330 compatible = "st,stm32f7-uart";
331 reg = <0x40005000 0x400>;
333 clocks = <&rcc 1 CLK_UART5>;
338 compatible = "st,stm32f7-i2c";
339 reg = <0x40005400 0x400>;
342 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
343 clocks = <&rcc 1 CLK_I2C1>;
344 #address-cells = <1>;
350 compatible = "st,stm32-cec";
351 reg = <0x40006C00 0x400>;
353 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
354 clock-names = "cec", "hdmi-cec";
358 usart7: serial@40007800 {
359 compatible = "st,stm32f7-uart";
360 reg = <0x40007800 0x400>;
362 clocks = <&rcc 1 CLK_UART7>;
366 usart8: serial@40007c00 {
367 compatible = "st,stm32f7-uart";
368 reg = <0x40007c00 0x400>;
370 clocks = <&rcc 1 CLK_UART8>;
374 timers1: timers@40010000 {
375 #address-cells = <1>;
377 compatible = "st,stm32-timers";
378 reg = <0x40010000 0x400>;
379 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
384 compatible = "st,stm32-pwm";
389 compatible = "st,stm32-timer-trigger";
395 timers8: timers@40010400 {
396 #address-cells = <1>;
398 compatible = "st,stm32-timers";
399 reg = <0x40010400 0x400>;
400 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
405 compatible = "st,stm32-pwm";
410 compatible = "st,stm32-timer-trigger";
416 usart1: serial@40011000 {
417 compatible = "st,stm32f7-uart";
418 reg = <0x40011000 0x400>;
420 clocks = <&rcc 1 CLK_USART1>;
424 usart6: serial@40011400 {
425 compatible = "st,stm32f7-uart";
426 reg = <0x40011400 0x400>;
428 clocks = <&rcc 1 CLK_USART6>;
432 syscfg: system-config@40013800 {
433 compatible = "syscon";
434 reg = <0x40013800 0x400>;
437 exti: interrupt-controller@40013c00 {
438 compatible = "st,stm32-exti";
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 reg = <0x40013C00 0x400>;
442 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
445 timers9: timers@40014000 {
446 #address-cells = <1>;
448 compatible = "st,stm32-timers";
449 reg = <0x40014000 0x400>;
450 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
455 compatible = "st,stm32-pwm";
460 compatible = "st,stm32-timer-trigger";
466 timers10: timers@40014400 {
467 #address-cells = <1>;
469 compatible = "st,stm32-timers";
470 reg = <0x40014400 0x400>;
471 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
476 compatible = "st,stm32-pwm";
481 timers11: timers@40014800 {
482 #address-cells = <1>;
484 compatible = "st,stm32-timers";
485 reg = <0x40014800 0x400>;
486 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
491 compatible = "st,stm32-pwm";
496 pwrcfg: power-config@40007000 {
497 compatible = "syscon";
498 reg = <0x40007000 0x400>;
502 #address-cells = <1>;
504 compatible = "st,stm32f746-pinctrl";
505 ranges = <0 0x40020000 0x3000>;
506 interrupt-parent = <&exti>;
507 st,syscfg = <&syscfg 0x8>;
510 gpioa: gpio@40020000 {
513 interrupt-controller;
514 #interrupt-cells = <2>;
516 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
517 st,bank-name = "GPIOA";
520 gpiob: gpio@40020400 {
523 interrupt-controller;
524 #interrupt-cells = <2>;
526 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
527 st,bank-name = "GPIOB";
530 gpioc: gpio@40020800 {
533 interrupt-controller;
534 #interrupt-cells = <2>;
536 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
537 st,bank-name = "GPIOC";
540 gpiod: gpio@40020c00 {
543 interrupt-controller;
544 #interrupt-cells = <2>;
546 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
547 st,bank-name = "GPIOD";
550 gpioe: gpio@40021000 {
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 reg = <0x1000 0x400>;
556 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
557 st,bank-name = "GPIOE";
560 gpiof: gpio@40021400 {
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 reg = <0x1400 0x400>;
566 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
567 st,bank-name = "GPIOF";
570 gpiog: gpio@40021800 {
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 reg = <0x1800 0x400>;
576 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
577 st,bank-name = "GPIOG";
580 gpioh: gpio@40021c00 {
583 interrupt-controller;
584 #interrupt-cells = <2>;
585 reg = <0x1c00 0x400>;
586 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
587 st,bank-name = "GPIOH";
590 gpioi: gpio@40022000 {
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 reg = <0x2000 0x400>;
596 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
597 st,bank-name = "GPIOI";
600 gpioj: gpio@40022400 {
603 interrupt-controller;
604 #interrupt-cells = <2>;
605 reg = <0x2400 0x400>;
606 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
607 st,bank-name = "GPIOJ";
610 gpiok: gpio@40022800 {
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 reg = <0x2800 0x400>;
616 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
617 st,bank-name = "GPIOK";
622 pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
629 usart1_pins_a: usart1@0 {
631 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
637 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
642 usart1_pins_b: usart1@1 {
644 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
650 pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
655 i2c1_pins_b: i2c1@0 {
657 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
658 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
665 usbotg_hs_pins_a: usbotg-hs@0 {
667 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
668 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
669 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
670 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
671 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
672 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
673 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
674 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
675 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
676 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
677 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
678 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
685 usbotg_hs_pins_b: usbotg-hs@1 {
687 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
688 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
689 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
690 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
691 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
692 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
693 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
694 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
695 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
696 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
697 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
698 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
705 usbotg_fs_pins_a: usbotg-fs@0 {
707 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
708 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
709 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
718 compatible = "st,stm32f7-crc";
719 reg = <0x40023000 0x400>;
720 clocks = <&rcc 0 12>;
727 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
728 reg = <0x40023800 0x400>;
729 clocks = <&clk_hse>, <&clk_i2s_ckin>;
730 st,syscfg = <&pwrcfg>;
731 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
732 assigned-clock-rates = <1000000>;
736 compatible = "st,stm32-dma";
737 reg = <0x40026000 0x400>;
746 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
752 compatible = "st,stm32-dma";
753 reg = <0x40026400 0x400>;
762 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
768 usbotg_hs: usb@40040000 {
769 compatible = "st,stm32f7-hsotg";
770 reg = <0x40040000 0x40000>;
772 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
777 usbotg_fs: usb@50000000 {
778 compatible = "st,stm32f4x9-fsotg";
779 reg = <0x50000000 0x40000>;
781 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;