3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
10 #include "st-pincfg.h"
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 compatible = "st,stih416-sbc-pinctrl";
52 st,syscfg = <&syscfg_sbc>;
53 reg = <0xfe61f080 0x4>;
55 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
56 interrupt-names = "irqmux";
57 ranges = <0 0xfe610000 0x6000>;
63 #interrupt-cells = <2>;
65 st,bank-name = "PIO0";
71 #interrupt-cells = <2>;
73 st,bank-name = "PIO1";
79 #interrupt-cells = <2>;
81 st,bank-name = "PIO2";
87 #interrupt-cells = <2>;
89 st,bank-name = "PIO3";
95 #interrupt-cells = <2>;
97 st,bank-name = "PIO4";
99 PIO40: gpio@fe615000 {
102 interrupt-controller;
103 #interrupt-cells = <2>;
104 reg = <0x5000 0x100>;
105 st,bank-name = "PIO40";
106 st,retime-pin-mask = <0x7f>;
112 ir = <&PIO4 0 ALT2 IN>;
117 pinctrl_sbc_serial1: sbc_serial1 {
119 tx = <&PIO2 6 ALT3 OUT>;
120 rx = <&PIO2 7 ALT3 IN>;
126 pinctrl_keyscan: keyscan {
128 keyin0 = <&PIO0 2 ALT2 IN>;
129 keyin1 = <&PIO0 3 ALT2 IN>;
130 keyin2 = <&PIO0 4 ALT2 IN>;
131 keyin3 = <&PIO2 6 ALT2 IN>;
133 keyout0 = <&PIO1 6 ALT2 OUT>;
134 keyout1 = <&PIO1 7 ALT2 OUT>;
135 keyout2 = <&PIO0 6 ALT2 OUT>;
136 keyout3 = <&PIO2 7 ALT2 OUT>;
142 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
144 sda = <&PIO4 6 ALT1 BIDIR>;
145 scl = <&PIO4 5 ALT1 BIDIR>;
151 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
153 sda = <&PIO3 2 ALT2 BIDIR>;
154 scl = <&PIO3 1 ALT2 BIDIR>;
162 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
163 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
164 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
165 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
166 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
167 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
168 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
169 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
171 mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
172 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
173 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
174 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
175 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
176 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
177 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
178 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
180 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
181 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
182 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
183 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
186 pinctrl_rgmii1: rgmii1-0 {
188 txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
189 txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
190 txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
191 txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
192 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
193 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
195 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
196 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
197 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
198 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
199 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
200 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
202 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
203 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
204 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
206 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
212 pin-controller-front {
213 #address-cells = <1>;
215 compatible = "st,stih416-front-pinctrl";
216 st,syscfg = <&syscfg_front>;
217 reg = <0xfee0f080 0x4>;
218 reg-names = "irqmux";
219 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
220 interrupt-names = "irqmux";
221 ranges = <0 0xfee00000 0x10000>;
223 PIO5: gpio@fee00000 {
226 interrupt-controller;
227 #interrupt-cells = <2>;
229 st,bank-name = "PIO5";
231 PIO6: gpio@fee01000 {
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 reg = <0x1000 0x100>;
237 st,bank-name = "PIO6";
239 PIO7: gpio@fee02000 {
242 interrupt-controller;
243 #interrupt-cells = <2>;
244 reg = <0x2000 0x100>;
245 st,bank-name = "PIO7";
247 PIO8: gpio@fee03000 {
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 reg = <0x3000 0x100>;
253 st,bank-name = "PIO8";
255 PIO9: gpio@fee04000 {
258 interrupt-controller;
259 #interrupt-cells = <2>;
260 reg = <0x4000 0x100>;
261 st,bank-name = "PIO9";
263 PIO10: gpio@fee05000 {
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 reg = <0x5000 0x100>;
269 st,bank-name = "PIO10";
271 PIO11: gpio@fee06000 {
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 reg = <0x6000 0x100>;
277 st,bank-name = "PIO11";
279 PIO12: gpio@fee07000 {
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 reg = <0x7000 0x100>;
285 st,bank-name = "PIO12";
287 PIO30: gpio@fee08000 {
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 reg = <0x8000 0x100>;
293 st,bank-name = "PIO30";
295 PIO31: gpio@fee09000 {
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 reg = <0x9000 0x100>;
301 st,bank-name = "PIO31";
305 pinctrl_serial2_oe: serial2-1 {
307 output-enable = <&PIO11 3 ALT2 OUT>;
313 pinctrl_i2c0_default: i2c0-default {
315 sda = <&PIO9 3 ALT1 BIDIR>;
316 scl = <&PIO9 2 ALT1 BIDIR>;
322 pinctrl_i2c1_default: i2c1-default {
324 sda = <&PIO12 1 ALT1 BIDIR>;
325 scl = <&PIO12 0 ALT1 BIDIR>;
333 spi-fsm-clk = <&PIO12 2 ALT1 OUT>;
334 spi-fsm-cs = <&PIO12 3 ALT1 OUT>;
335 spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
336 spi-fsm-miso = <&PIO12 5 ALT1 IN>;
337 spi-fsm-hol = <&PIO12 6 ALT1 OUT>;
338 spi-fsm-wp = <&PIO12 7 ALT1 OUT>;
344 pin-controller-rear {
345 #address-cells = <1>;
347 compatible = "st,stih416-rear-pinctrl";
348 st,syscfg = <&syscfg_rear>;
349 reg = <0xfe82f080 0x4>;
350 reg-names = "irqmux";
351 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
352 interrupt-names = "irqmux";
353 ranges = <0 0xfe820000 0x6000>;
355 PIO13: gpio@fe820000 {
358 interrupt-controller;
359 #interrupt-cells = <2>;
361 st,bank-name = "PIO13";
363 PIO14: gpio@fe821000 {
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 reg = <0x1000 0x100>;
369 st,bank-name = "PIO14";
371 PIO15: gpio@fe822000 {
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 reg = <0x2000 0x100>;
377 st,bank-name = "PIO15";
379 PIO16: gpio@fe823000 {
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 reg = <0x3000 0x100>;
385 st,bank-name = "PIO16";
387 PIO17: gpio@fe824000 {
390 interrupt-controller;
391 #interrupt-cells = <2>;
392 reg = <0x4000 0x100>;
393 st,bank-name = "PIO17";
395 PIO18: gpio@fe825000 {
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 reg = <0x5000 0x100>;
401 st,bank-name = "PIO18";
402 st,retime-pin-mask = <0xf>;
406 pinctrl_serial2: serial2-0 {
408 tx = <&PIO17 4 ALT2 OUT>;
409 rx = <&PIO17 5 ALT2 IN>;
417 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
418 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
419 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
420 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
421 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
422 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
424 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
425 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
426 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
427 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
428 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
429 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
431 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
432 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
433 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
434 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
435 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
436 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
437 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
438 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
442 pinctrl_gmii0: gmii0 {
446 pinctrl_rgmii0: rgmii0 {
448 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
449 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
450 txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
451 txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
452 txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
453 txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
454 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
456 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
457 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
459 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
460 rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
461 rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
462 rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
463 rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
464 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
466 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
472 pin-controller-fvdp-fe {
473 #address-cells = <1>;
475 compatible = "st,stih416-fvdp-fe-pinctrl";
476 st,syscfg = <&syscfg_fvdp_fe>;
477 reg = <0xfd6bf080 0x4>;
478 reg-names = "irqmux";
479 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
480 interrupt-names = "irqmux";
481 ranges = <0 0xfd6b0000 0x3000>;
483 PIO100: gpio@fd6b0000 {
486 interrupt-controller;
487 #interrupt-cells = <2>;
489 st,bank-name = "PIO100";
491 PIO101: gpio@fd6b1000 {
494 interrupt-controller;
495 #interrupt-cells = <2>;
496 reg = <0x1000 0x100>;
497 st,bank-name = "PIO101";
499 PIO102: gpio@fd6b2000 {
502 interrupt-controller;
503 #interrupt-cells = <2>;
504 reg = <0x2000 0x100>;
505 st,bank-name = "PIO102";
509 pin-controller-fvdp-lite {
510 #address-cells = <1>;
512 compatible = "st,stih416-fvdp-lite-pinctrl";
513 st,syscfg = <&syscfg_fvdp_lite>;
514 reg = <0xfd33f080 0x4>;
515 reg-names = "irqmux";
516 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
517 interrupt-names = "irqmux";
518 ranges = <0 0xfd330000 0x5000>;
520 PIO103: gpio@fd330000 {
523 interrupt-controller;
524 #interrupt-cells = <2>;
526 st,bank-name = "PIO103";
528 PIO104: gpio@fd331000 {
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 reg = <0x1000 0x100>;
534 st,bank-name = "PIO104";
536 PIO105: gpio@fd332000 {
539 interrupt-controller;
540 #interrupt-cells = <2>;
541 reg = <0x2000 0x100>;
542 st,bank-name = "PIO105";
544 PIO106: gpio@fd333000 {
547 interrupt-controller;
548 #interrupt-cells = <2>;
549 reg = <0x3000 0x100>;
550 st,bank-name = "PIO106";
553 PIO107: gpio@fd334000 {
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 reg = <0x4000 0x100>;
559 st,bank-name = "PIO107";
560 st,retime-pin-mask = <0xf>;