2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include "skeleton.dtsi"
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
33 enable-method = "altr,socfpga-a10-smp";
36 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a9";
45 next-level-cache = <&L2>;
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
53 reg = <0xffffd000 0x1000>,
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffda1000 0x1000>;
74 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
75 <0 84 IRQ_TYPE_LEVEL_HIGH>,
76 <0 85 IRQ_TYPE_LEVEL_HIGH>,
77 <0 86 IRQ_TYPE_LEVEL_HIGH>,
78 <0 87 IRQ_TYPE_LEVEL_HIGH>,
79 <0 88 IRQ_TYPE_LEVEL_HIGH>,
80 <0 89 IRQ_TYPE_LEVEL_HIGH>,
81 <0 90 IRQ_TYPE_LEVEL_HIGH>,
82 <0 91 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&l4_main_clk>;
87 clock-names = "apb_pclk";
92 compatible = "altr,clk-mgr";
93 reg = <0xffd04000 0x1000>;
99 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
101 compatible = "fixed-clock";
104 cb_intosc_ls_clk: cb_intosc_ls_clk {
106 compatible = "fixed-clock";
109 f2s_free_clk: f2s_free_clk {
111 compatible = "fixed-clock";
116 compatible = "fixed-clock";
120 #address-cells = <1>;
123 compatible = "altr,socfpga-a10-pll-clock";
124 clocks = <&osc1>, <&cb_intosc_ls_clk>,
128 main_mpu_base_clk: main_mpu_base_clk {
130 compatible = "altr,socfpga-a10-perip-clk";
131 clocks = <&main_pll>;
132 div-reg = <0x140 0 11>;
135 main_noc_base_clk: main_noc_base_clk {
137 compatible = "altr,socfpga-a10-perip-clk";
138 clocks = <&main_pll>;
139 div-reg = <0x144 0 11>;
142 main_emaca_clk: main_emaca_clk {
144 compatible = "altr,socfpga-a10-perip-clk";
145 clocks = <&main_pll>;
149 main_emacb_clk: main_emacb_clk {
151 compatible = "altr,socfpga-a10-perip-clk";
152 clocks = <&main_pll>;
156 main_emac_ptp_clk: main_emac_ptp_clk {
158 compatible = "altr,socfpga-a10-perip-clk";
159 clocks = <&main_pll>;
163 main_gpio_db_clk: main_gpio_db_clk {
165 compatible = "altr,socfpga-a10-perip-clk";
166 clocks = <&main_pll>;
170 main_sdmmc_clk: main_sdmmc_clk {
172 compatible = "altr,socfpga-a10-perip-clk"
174 clocks = <&main_pll>;
178 main_s2f_usr0_clk: main_s2f_usr0_clk {
180 compatible = "altr,socfpga-a10-perip-clk";
181 clocks = <&main_pll>;
185 main_s2f_usr1_clk: main_s2f_usr1_clk {
187 compatible = "altr,socfpga-a10-perip-clk";
188 clocks = <&main_pll>;
192 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
194 compatible = "altr,socfpga-a10-perip-clk";
195 clocks = <&main_pll>;
199 main_periph_ref_clk: main_periph_ref_clk {
201 compatible = "altr,socfpga-a10-perip-clk";
202 clocks = <&main_pll>;
207 periph_pll: periph_pll {
208 #address-cells = <1>;
211 compatible = "altr,socfpga-a10-pll-clock";
212 clocks = <&osc1>, <&cb_intosc_ls_clk>,
213 <&f2s_free_clk>, <&main_periph_ref_clk>;
216 peri_mpu_base_clk: peri_mpu_base_clk {
218 compatible = "altr,socfpga-a10-perip-clk";
219 clocks = <&periph_pll>;
220 div-reg = <0x140 16 11>;
223 peri_noc_base_clk: peri_noc_base_clk {
225 compatible = "altr,socfpga-a10-perip-clk";
226 clocks = <&periph_pll>;
227 div-reg = <0x144 16 11>;
230 peri_emaca_clk: peri_emaca_clk {
232 compatible = "altr,socfpga-a10-perip-clk";
233 clocks = <&periph_pll>;
237 peri_emacb_clk: peri_emacb_clk {
239 compatible = "altr,socfpga-a10-perip-clk";
240 clocks = <&periph_pll>;
244 peri_emac_ptp_clk: peri_emac_ptp_clk {
246 compatible = "altr,socfpga-a10-perip-clk";
247 clocks = <&periph_pll>;
251 peri_gpio_db_clk: peri_gpio_db_clk {
253 compatible = "altr,socfpga-a10-perip-clk";
254 clocks = <&periph_pll>;
258 peri_sdmmc_clk: peri_sdmmc_clk {
260 compatible = "altr,socfpga-a10-perip-clk";
261 clocks = <&periph_pll>;
265 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
267 compatible = "altr,socfpga-a10-perip-clk";
268 clocks = <&periph_pll>;
272 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
274 compatible = "altr,socfpga-a10-perip-clk";
275 clocks = <&periph_pll>;
279 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
281 compatible = "altr,socfpga-a10-perip-clk";
282 clocks = <&periph_pll>;
287 mpu_free_clk: mpu_free_clk {
289 compatible = "altr,socfpga-a10-perip-clk";
290 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
291 <&osc1>, <&cb_intosc_hs_div2_clk>,
296 noc_free_clk: noc_free_clk {
298 compatible = "altr,socfpga-a10-perip-clk";
299 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
300 <&osc1>, <&cb_intosc_hs_div2_clk>,
305 s2f_user1_free_clk: s2f_user1_free_clk {
307 compatible = "altr,socfpga-a10-perip-clk";
308 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
309 <&osc1>, <&cb_intosc_hs_div2_clk>,
314 sdmmc_free_clk: sdmmc_free_clk {
316 compatible = "altr,socfpga-a10-perip-clk";
317 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
318 <&osc1>, <&cb_intosc_hs_div2_clk>,
324 l4_sys_free_clk: l4_sys_free_clk {
326 compatible = "altr,socfpga-a10-perip-clk";
327 clocks = <&noc_free_clk>;
331 l4_main_clk: l4_main_clk {
333 compatible = "altr,socfpga-a10-gate-clk";
334 clocks = <&noc_free_clk>;
335 div-reg = <0xA8 0 2>;
339 l4_mp_clk: l4_mp_clk {
341 compatible = "altr,socfpga-a10-gate-clk";
342 clocks = <&noc_free_clk>;
343 div-reg = <0xA8 8 2>;
347 l4_sp_clk: l4_sp_clk {
349 compatible = "altr,socfpga-a10-gate-clk";
350 clocks = <&noc_free_clk>;
351 div-reg = <0xA8 16 2>;
355 mpu_periph_clk: mpu_periph_clk {
357 compatible = "altr,socfpga-a10-gate-clk";
358 clocks = <&mpu_free_clk>;
363 sdmmc_clk: sdmmc_clk {
365 compatible = "altr,socfpga-a10-gate-clk";
366 clocks = <&sdmmc_free_clk>;
373 compatible = "altr,socfpga-a10-gate-clk";
374 clocks = <&l4_main_clk>;
375 clk-gate = <0xC8 11>;
380 compatible = "altr,socfpga-a10-gate-clk";
381 clocks = <&l4_mp_clk>;
382 clk-gate = <0xC8 10>;
385 spi_m_clk: spi_m_clk {
387 compatible = "altr,socfpga-a10-gate-clk";
388 clocks = <&l4_main_clk>;
394 compatible = "altr,socfpga-a10-gate-clk";
395 clocks = <&l4_mp_clk>;
399 s2f_usr1_clk: s2f_usr1_clk {
401 compatible = "altr,socfpga-a10-gate-clk";
402 clocks = <&peri_s2f_usr1_clk>;
408 gmac0: ethernet@ff800000 {
409 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
410 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
411 reg = <0xff800000 0x2000>;
412 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "macirq";
414 /* Filled in by bootloader */
415 mac-address = [00 00 00 00 00 00];
416 snps,multicast-filter-bins = <256>;
417 snps,perfect-filter-entries = <128>;
418 tx-fifo-depth = <4096>;
419 rx-fifo-depth = <16384>;
420 clocks = <&l4_mp_clk>;
421 clock-names = "stmmaceth";
422 resets = <&rst EMAC0_RESET>;
423 reset-names = "stmmaceth";
427 gmac1: ethernet@ff802000 {
428 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
429 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
430 reg = <0xff802000 0x2000>;
431 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-names = "macirq";
433 /* Filled in by bootloader */
434 mac-address = [00 00 00 00 00 00];
435 snps,multicast-filter-bins = <256>;
436 snps,perfect-filter-entries = <128>;
437 tx-fifo-depth = <4096>;
438 rx-fifo-depth = <16384>;
439 clocks = <&l4_mp_clk>;
440 clock-names = "stmmaceth";
441 resets = <&rst EMAC1_RESET>;
442 reset-names = "stmmaceth";
446 gmac2: ethernet@ff804000 {
447 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
448 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
449 reg = <0xff804000 0x2000>;
450 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-names = "macirq";
452 /* Filled in by bootloader */
453 mac-address = [00 00 00 00 00 00];
454 snps,multicast-filter-bins = <256>;
455 snps,perfect-filter-entries = <128>;
456 tx-fifo-depth = <4096>;
457 rx-fifo-depth = <16384>;
458 clocks = <&l4_mp_clk>;
459 clock-names = "stmmaceth";
463 gpio0: gpio@ffc02900 {
464 #address-cells = <1>;
466 compatible = "snps,dw-apb-gpio";
467 reg = <0xffc02900 0x100>;
470 porta: gpio-controller@0 {
471 compatible = "snps,dw-apb-gpio-port";
474 snps,nr-gpios = <29>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
482 gpio1: gpio@ffc02a00 {
483 #address-cells = <1>;
485 compatible = "snps,dw-apb-gpio";
486 reg = <0xffc02a00 0x100>;
489 portb: gpio-controller@0 {
490 compatible = "snps,dw-apb-gpio-port";
493 snps,nr-gpios = <29>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
501 gpio2: gpio@ffc02b00 {
502 #address-cells = <1>;
504 compatible = "snps,dw-apb-gpio";
505 reg = <0xffc02b00 0x100>;
508 portc: gpio-controller@0 {
509 compatible = "snps,dw-apb-gpio-port";
512 snps,nr-gpios = <27>;
514 interrupt-controller;
515 #interrupt-cells = <2>;
516 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
523 compatible = "snps,designware-i2c";
524 reg = <0xffc02200 0x100>;
525 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&l4_sp_clk>;
531 #address-cells = <1>;
533 compatible = "snps,designware-i2c";
534 reg = <0xffc02300 0x100>;
535 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&l4_sp_clk>;
541 #address-cells = <1>;
543 compatible = "snps,designware-i2c";
544 reg = <0xffc02400 0x100>;
545 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&l4_sp_clk>;
551 #address-cells = <1>;
553 compatible = "snps,designware-i2c";
554 reg = <0xffc02500 0x100>;
555 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&l4_sp_clk>;
561 #address-cells = <1>;
563 compatible = "snps,designware-i2c";
564 reg = <0xffc02600 0x100>;
565 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&l4_sp_clk>;
571 compatible = "syscon";
572 reg = <0xffcfb100 0x80>;
576 compatible = "altr,sdram-edac-a10";
577 altr,sdr-syscon = <&sdr>;
578 interrupts = <0 2 4>, <0 0 4>;
581 L2: l2-cache@fffff000 {
582 compatible = "arm,pl310-cache";
583 reg = <0xfffff000 0x1000>;
584 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
589 mmc: dwmmc0@ff808000 {
590 #address-cells = <1>;
592 compatible = "altr,socfpga-dw-mshc";
593 reg = <0xff808000 0x1000>;
594 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
595 fifo-depth = <0x400>;
596 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
597 clock-names = "biu", "ciu";
601 ocram: sram@ffe00000 {
602 compatible = "mmio-sram";
603 reg = <0xffe00000 0x40000>;
606 eccmgr: eccmgr@ffd06000 {
607 compatible = "altr,socfpga-a10-ecc-manager";
608 altr,sysmgr-syscon = <&sysmgr>;
609 #address-cells = <1>;
611 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
612 <0 0 IRQ_TYPE_LEVEL_HIGH>;
616 compatible = "altr,socfpga-a10-l2-ecc";
617 reg = <0xffd06010 0x4>;
621 compatible = "altr,socfpga-a10-ocram-ecc";
622 reg = <0xff8c3000 0x400>;
626 rst: rstmgr@ffd05000 {
628 compatible = "altr,rst-mgr";
629 reg = <0xffd05000 0x100>;
630 altr,modrst-offset = <0x20>;
633 scu: snoop-control-unit@ffffc000 {
634 compatible = "arm,cortex-a9-scu";
635 reg = <0xffffc000 0x100>;
638 sysmgr: sysmgr@ffd06000 {
639 compatible = "altr,sys-mgr", "syscon";
640 reg = <0xffd06000 0x300>;
641 cpu1-start-addr = <0xffd06230>;
646 compatible = "arm,cortex-a9-twd-timer";
647 reg = <0xffffc600 0x100>;
648 interrupts = <1 13 0xf04>;
649 clocks = <&mpu_periph_clk>;
652 timer0: timer0@ffc02700 {
653 compatible = "snps,dw-apb-timer";
654 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
655 reg = <0xffc02700 0x100>;
656 clocks = <&l4_sp_clk>;
657 clock-names = "timer";
660 timer1: timer1@ffc02800 {
661 compatible = "snps,dw-apb-timer";
662 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
663 reg = <0xffc02800 0x100>;
664 clocks = <&l4_sp_clk>;
665 clock-names = "timer";
668 timer2: timer2@ffd00000 {
669 compatible = "snps,dw-apb-timer";
670 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
671 reg = <0xffd00000 0x100>;
672 clocks = <&l4_sys_free_clk>;
673 clock-names = "timer";
676 timer3: timer3@ffd00100 {
677 compatible = "snps,dw-apb-timer";
678 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
679 reg = <0xffd01000 0x100>;
680 clocks = <&l4_sys_free_clk>;
681 clock-names = "timer";
684 uart0: serial0@ffc02000 {
685 compatible = "snps,dw-apb-uart";
686 reg = <0xffc02000 0x100>;
687 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&l4_sp_clk>;
694 uart1: serial1@ffc02100 {
695 compatible = "snps,dw-apb-uart";
696 reg = <0xffc02100 0x100>;
697 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&l4_sp_clk>;
706 compatible = "usb-nop-xceiv";
711 compatible = "snps,dwc2";
712 reg = <0xffb00000 0xffff>;
713 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
716 resets = <&rst USB0_RESET>;
717 reset-names = "dwc2";
719 phy-names = "usb2-phy";
724 compatible = "snps,dwc2";
725 reg = <0xffb40000 0xffff>;
726 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
729 resets = <&rst USB1_RESET>;
730 reset-names = "dwc2";
732 phy-names = "usb2-phy";
736 watchdog0: watchdog@ffd00200 {
737 compatible = "snps,dw-wdt";
738 reg = <0xffd00200 0x100>;
739 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&l4_sys_free_clk>;
744 watchdog1: watchdog@ffd00300 {
745 compatible = "snps,dw-wdt";
746 reg = <0xffd00300 0x100>;
747 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&l4_sys_free_clk>;