2 * Device Tree Source for the SH73A0 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/sh73a0-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,sh73a0";
17 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a9";
29 clock-frequency = <1196000000>;
30 clocks = <&cpg_clocks SH73A0_CLK_Z>;
31 power-domains = <&pd_a2sl>;
32 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
38 clock-frequency = <1196000000>;
39 clocks = <&cpg_clocks SH73A0_CLK_Z>;
40 power-domains = <&pd_a2sl>;
41 next-level-cache = <&L2>;
46 compatible = "arm,cortex-a9-twd-timer";
47 reg = <0xf0000600 0x20>;
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
52 gic: interrupt-controller@f0001000 {
53 compatible = "arm,cortex-a9-gic";
54 #interrupt-cells = <3>;
56 reg = <0xf0001000 0x1000>,
60 L2: cache-controller@f0100000 {
61 compatible = "arm,pl310-cache";
62 reg = <0xf0100000 0x1000>;
63 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
64 power-domains = <&pd_a3sm>;
65 arm,data-latency = <3 3 3>;
66 arm,tag-latency = <2 2 2>;
72 sbsc2: memory-controller@fb400000 {
73 compatible = "renesas,sbsc-sh73a0";
74 reg = <0xfb400000 0x400>;
75 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-names = "sec", "temp";
78 power-domains = <&pd_a4bc1>;
81 sbsc1: memory-controller@fe400000 {
82 compatible = "renesas,sbsc-sh73a0";
83 reg = <0xfe400000 0x400>;
84 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "sec", "temp";
87 power-domains = <&pd_a4bc0>;
91 compatible = "arm,cortex-a9-pmu";
92 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
96 cmt1: timer@e6138000 {
97 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
98 reg = <0xe6138000 0x200>;
99 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
102 power-domains = <&pd_c5>;
104 renesas,channels-mask = <0x3f>;
109 irqpin0: interrupt-controller@e6900000 {
110 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
111 #interrupt-cells = <2>;
112 interrupt-controller;
113 reg = <0xe6900000 4>,
118 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
123 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
124 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
125 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
127 power-domains = <&pd_a4s>;
131 irqpin1: interrupt-controller@e6900004 {
132 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 reg = <0xe6900004 4>,
140 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
145 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
146 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
147 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
149 power-domains = <&pd_a4s>;
153 irqpin2: interrupt-controller@e6900008 {
154 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
155 #interrupt-cells = <2>;
156 interrupt-controller;
157 reg = <0xe6900008 4>,
162 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
167 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
168 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
169 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
171 power-domains = <&pd_a4s>;
175 irqpin3: interrupt-controller@e690000c {
176 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
177 #interrupt-cells = <2>;
178 interrupt-controller;
179 reg = <0xe690000c 4>,
184 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
185 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
186 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
187 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
188 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
189 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
190 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
191 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
193 power-domains = <&pd_a4s>;
198 #address-cells = <1>;
200 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
201 reg = <0xe6820000 0x425>;
202 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
203 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
204 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
205 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
207 power-domains = <&pd_a3sp>;
212 #address-cells = <1>;
214 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
215 reg = <0xe6822000 0x425>;
216 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
217 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
218 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
219 GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
221 power-domains = <&pd_a3sp>;
226 #address-cells = <1>;
228 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
229 reg = <0xe6824000 0x425>;
230 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
231 GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
232 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
233 GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
235 power-domains = <&pd_a3sp>;
240 #address-cells = <1>;
242 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
243 reg = <0xe6826000 0x425>;
244 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
247 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
249 power-domains = <&pd_a3sp>;
254 #address-cells = <1>;
256 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
257 reg = <0xe6828000 0x425>;
258 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
259 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
260 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
261 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
263 power-domains = <&pd_c5>;
267 mmcif: mmc@e6bd0000 {
268 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
269 reg = <0xe6bd0000 0x100>;
270 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
273 power-domains = <&pd_a3sp>;
278 msiof0: spi@e6e20000 {
279 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
280 reg = <0xe6e20000 0x0064>;
281 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
283 power-domains = <&pd_a3sp>;
284 #address-cells = <1>;
289 msiof1: spi@e6e10000 {
290 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
291 reg = <0xe6e10000 0x0064>;
292 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
294 power-domains = <&pd_a3sp>;
295 #address-cells = <1>;
300 msiof2: spi@e6e00000 {
301 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
302 reg = <0xe6e00000 0x0064>;
303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
305 power-domains = <&pd_a3sp>;
306 #address-cells = <1>;
311 msiof3: spi@e6c90000 {
312 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
313 reg = <0xe6c90000 0x0064>;
314 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
316 power-domains = <&pd_a3sp>;
317 #address-cells = <1>;
323 compatible = "renesas,sdhi-sh73a0";
324 reg = <0xee100000 0x100>;
325 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
329 power-domains = <&pd_a3sp>;
334 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
336 compatible = "renesas,sdhi-sh73a0";
337 reg = <0xee120000 0x100>;
338 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
341 power-domains = <&pd_a3sp>;
342 toshiba,mmc-wrprotect-disable;
348 compatible = "renesas,sdhi-sh73a0";
349 reg = <0xee140000 0x100>;
350 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
353 power-domains = <&pd_a3sp>;
354 toshiba,mmc-wrprotect-disable;
359 scifa0: serial@e6c40000 {
360 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
361 reg = <0xe6c40000 0x100>;
362 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
365 power-domains = <&pd_a3sp>;
369 scifa1: serial@e6c50000 {
370 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
371 reg = <0xe6c50000 0x100>;
372 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
375 power-domains = <&pd_a3sp>;
379 scifa2: serial@e6c60000 {
380 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
381 reg = <0xe6c60000 0x100>;
382 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
385 power-domains = <&pd_a3sp>;
389 scifa3: serial@e6c70000 {
390 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
391 reg = <0xe6c70000 0x100>;
392 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
395 power-domains = <&pd_a3sp>;
399 scifa4: serial@e6c80000 {
400 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
401 reg = <0xe6c80000 0x100>;
402 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
405 power-domains = <&pd_a3sp>;
409 scifa5: serial@e6cb0000 {
410 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
411 reg = <0xe6cb0000 0x100>;
412 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
415 power-domains = <&pd_a3sp>;
419 scifa6: serial@e6cc0000 {
420 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
421 reg = <0xe6cc0000 0x100>;
422 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
425 power-domains = <&pd_a3sp>;
429 scifa7: serial@e6cd0000 {
430 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
431 reg = <0xe6cd0000 0x100>;
432 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
435 power-domains = <&pd_a3sp>;
439 scifb: serial@e6c30000 {
440 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
441 reg = <0xe6c30000 0x100>;
442 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
445 power-domains = <&pd_a3sp>;
449 pfc: pin-controller@e6050000 {
450 compatible = "renesas,pfc-sh73a0";
451 reg = <0xe6050000 0x8000>,
456 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
458 interrupts-extended =
459 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
460 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
461 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
462 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
463 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
464 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
465 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
466 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
467 power-domains = <&pd_c5>;
470 sysc: system-controller@e6180000 {
471 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
472 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
476 #address-cells = <1>;
478 #power-domain-cells = <0>;
482 #power-domain-cells = <0>;
487 #power-domain-cells = <0>;
492 #power-domain-cells = <0>;
497 #power-domain-cells = <0>;
502 #power-domain-cells = <0>;
507 #power-domain-cells = <0>;
512 #address-cells = <1>;
514 #power-domain-cells = <0>;
518 #power-domain-cells = <0>;
523 #power-domain-cells = <0>;
529 #address-cells = <1>;
531 #power-domain-cells = <0>;
535 #address-cells = <1>;
537 #power-domain-cells = <0>;
541 #address-cells = <1>;
543 #power-domain-cells = <0>;
550 #address-cells = <1>;
552 #power-domain-cells = <0>;
556 #power-domain-cells = <0>;
561 #power-domain-cells = <0>;
566 #address-cells = <1>;
568 #power-domain-cells = <0>;
572 #power-domain-cells = <0>;
580 sh_fsi2: sound@ec230000 {
581 #sound-dai-cells = <1>;
582 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
583 reg = <0xec230000 0x400>;
584 interrupts = <GIC_SPI 146 0x4>;
585 power-domains = <&pd_a4mp>;
590 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
592 #address-cells = <1>;
594 ranges = <0 0 0x20000000>;
595 reg = <0xfec10000 0x400>;
596 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
598 power-domains = <&pd_a4s>;
602 #address-cells = <1>;
606 /* External root clocks */
608 compatible = "fixed-clock";
610 clock-frequency = <32768>;
613 compatible = "fixed-clock";
615 clock-frequency = <26000000>;
618 compatible = "fixed-clock";
622 compatible = "fixed-clock";
626 compatible = "fixed-clock";
628 clock-frequency = <0>;
631 compatible = "fixed-clock";
633 clock-frequency = <0>;
636 /* Special CPG clocks */
637 cpg_clocks: cpg_clocks@e6150000 {
638 compatible = "renesas,sh73a0-cpg-clocks";
639 reg = <0xe6150000 0x10000>;
640 clocks = <&extal1_clk>, <&extal2_clk>;
642 clock-output-names = "main", "pll0", "pll1", "pll2",
643 "pll3", "dsi0phy", "dsi1phy",
644 "zg", "m3", "b", "m1", "m2",
648 /* Variable factor clocks (DIV6) */
649 vclk1_clk: vclk1@e6150008 {
650 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
651 reg = <0xe6150008 4>;
652 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
653 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
654 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
658 vclk2_clk: vclk2@e615000c {
659 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
660 reg = <0xe615000c 4>;
661 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
662 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
663 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
667 vclk3_clk: vclk3@e615001c {
668 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
669 reg = <0xe615001c 4>;
670 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
671 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
672 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
676 zb_clk: zb_clk@e6150010 {
677 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
678 reg = <0xe6150010 4>;
679 clocks = <&pll1_div2_clk>, <0>,
680 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
682 clock-output-names = "zb";
684 flctl_clk: flctlck@e6150014 {
685 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
686 reg = <0xe6150014 4>;
687 clocks = <&pll1_div2_clk>, <0>,
688 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
691 sdhi0_clk: sdhi0ck@e6150074 {
692 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
693 reg = <0xe6150074 4>;
694 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
695 <&pll1_div13_clk>, <0>;
698 sdhi1_clk: sdhi1ck@e6150078 {
699 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
700 reg = <0xe6150078 4>;
701 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
702 <&pll1_div13_clk>, <0>;
705 sdhi2_clk: sdhi2ck@e615007c {
706 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
707 reg = <0xe615007c 4>;
708 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
709 <&pll1_div13_clk>, <0>;
712 fsia_clk: fsia@e6150018 {
713 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
714 reg = <0xe6150018 4>;
715 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
716 <&fsiack_clk>, <&fsiack_clk>;
719 fsib_clk: fsib@e6150090 {
720 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
721 reg = <0xe6150090 4>;
722 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
723 <&fsibck_clk>, <&fsibck_clk>;
726 sub_clk: sub@e6150080 {
727 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
728 reg = <0xe6150080 4>;
729 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
730 <&extal2_clk>, <&extal2_clk>;
733 spua_clk: spua@e6150084 {
734 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
735 reg = <0xe6150084 4>;
736 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
737 <&extal2_clk>, <&extal2_clk>;
740 spuv_clk: spuv@e6150094 {
741 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
742 reg = <0xe6150094 4>;
743 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
744 <&extal2_clk>, <&extal2_clk>;
747 msu_clk: msu@e6150088 {
748 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
749 reg = <0xe6150088 4>;
750 clocks = <&pll1_div2_clk>, <0>,
751 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
754 hsi_clk: hsi@e615008c {
755 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
756 reg = <0xe615008c 4>;
757 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
758 <&pll1_div7_clk>, <0>;
761 mfg1_clk: mfg1@e6150098 {
762 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
763 reg = <0xe6150098 4>;
764 clocks = <&pll1_div2_clk>, <0>,
765 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
768 mfg2_clk: mfg2@e615009c {
769 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
770 reg = <0xe615009c 4>;
771 clocks = <&pll1_div2_clk>, <0>,
772 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
775 dsit_clk: dsit@e6150060 {
776 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
777 reg = <0xe6150060 4>;
778 clocks = <&pll1_div2_clk>, <0>,
779 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
782 dsi0p_clk: dsi0pck@e6150064 {
783 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
784 reg = <0xe6150064 4>;
785 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
786 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
787 <&extcki_clk>, <0>, <0>, <0>;
791 /* Fixed factor clocks */
792 main_div2_clk: main_div2 {
793 compatible = "fixed-factor-clock";
794 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
799 pll1_div2_clk: pll1_div2 {
800 compatible = "fixed-factor-clock";
801 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
806 pll1_div7_clk: pll1_div7 {
807 compatible = "fixed-factor-clock";
808 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
813 pll1_div13_clk: pll1_div13 {
814 compatible = "fixed-factor-clock";
815 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
821 compatible = "fixed-factor-clock";
822 clocks = <&cpg_clocks SH73A0_CLK_Z>;
829 mstp0_clks: mstp0_clks@e6150130 {
830 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
831 reg = <0xe6150130 4>, <0xe6150030 4>;
832 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
835 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
840 mstp1_clks: mstp1_clks@e6150134 {
841 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
842 reg = <0xe6150134 4>, <0xe6150038 4>;
843 clocks = <&cpg_clocks SH73A0_CLK_B>,
844 <&cpg_clocks SH73A0_CLK_B>,
845 <&cpg_clocks SH73A0_CLK_B>,
846 <&cpg_clocks SH73A0_CLK_B>,
847 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
848 <&cpg_clocks SH73A0_CLK_HP>,
849 <&cpg_clocks SH73A0_CLK_ZG>,
850 <&cpg_clocks SH73A0_CLK_B>;
853 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
854 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
855 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
856 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
860 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
861 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
863 mstp2_clks: mstp2_clks@e6150138 {
864 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
865 reg = <0xe6150138 4>, <0xe6150040 4>;
866 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
867 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
868 <&sub_clk>, <&sub_clk>, <&sub_clk>,
869 <&sub_clk>, <&sub_clk>, <&sub_clk>,
870 <&sub_clk>, <&sub_clk>, <&sub_clk>;
873 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
874 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
875 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
876 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
877 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
878 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
882 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
883 "msiof1", "scifa5", "scifb", "msiof2",
884 "scifa0", "scifa1", "scifa2", "scifa3",
887 mstp3_clks: mstp3_clks@e615013c {
888 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
889 reg = <0xe615013c 4>, <0xe6150048 4>;
890 clocks = <&sub_clk>, <&extalr_clk>,
891 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
892 <&cpg_clocks SH73A0_CLK_HP>,
893 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
894 <&sdhi0_clk>, <&sdhi1_clk>,
895 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
896 <&main_div2_clk>, <&main_div2_clk>,
897 <&main_div2_clk>, <&main_div2_clk>,
901 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
902 SH73A0_CLK_FSI SH73A0_CLK_IRDA
903 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
904 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
905 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
906 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
907 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
911 "scifa6", "cmt1", "fsi", "irda", "iic1",
912 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
913 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
915 mstp4_clks: mstp4_clks@e6150140 {
916 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
917 reg = <0xe6150140 4>, <0xe615004c 4>;
918 clocks = <&cpg_clocks SH73A0_CLK_HP>,
919 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
922 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
926 "iic3", "iic4", "keysc";
928 mstp5_clks: mstp5_clks@e6150144 {
929 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
930 reg = <0xe6150144 4>, <0xe615003c 4>;
931 clocks = <&cpg_clocks SH73A0_CLK_HP>;