1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
7 * Author: Eugen Hristev <eugen.hristev@microchip.com>
8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/dma/at91.h>
16 #include <dt-bindings/gpio/gpio.h>
19 model = "Microchip SAMA7G5 family SoC";
20 compatible = "microchip,sama7g5";
23 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a7";
33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
35 operating-points-v2 = <&cpu_opp_table>;
39 cpu_opp_table: opp-table {
40 compatible = "operating-points-v2";
43 opp-hz = /bits/ 64 <90000000>;
44 opp-microvolt = <1050000 1050000 1225000>;
45 clock-latency-ns = <320000>;
49 opp-hz = /bits/ 64 <250000000>;
50 opp-microvolt = <1050000 1050000 1225000>;
51 clock-latency-ns = <320000>;
55 opp-hz = /bits/ 64 <600000000>;
56 opp-microvolt = <1050000 1050000 1225000>;
57 clock-latency-ns = <320000>;
62 opp-hz = /bits/ 64 <800000000>;
63 opp-microvolt = <1150000 1125000 1225000>;
64 clock-latency-ns = <320000>;
68 opp-hz = /bits/ 64 <1000000002>;
69 opp-microvolt = <1250000 1225000 1300000>;
70 clock-latency-ns = <320000>;
75 slow_xtal: slow_xtal {
76 compatible = "fixed-clock";
80 main_xtal: main_xtal {
81 compatible = "fixed-clock";
86 compatible = "fixed-clock";
88 clock-frequency = <48000000>;
92 vddout25: fixed-regulator-vddout25 {
93 compatible = "regulator-fixed";
95 regulator-name = "VDDOUT25";
96 regulator-min-microvolt = <2500000>;
97 regulator-max-microvolt = <2500000>;
102 ns_sram: sram@100000 {
103 compatible = "mmio-sram";
104 #address-cells = <1>;
106 reg = <0x100000 0x20000>;
111 compatible = "simple-bus";
112 #address-cells = <1>;
116 nfc_sram: sram@600000 {
117 compatible = "mmio-sram";
119 reg = <0x00600000 0x2400>;
120 #address-cells = <1>;
122 ranges = <0 0x00600000 0x2400>;
125 nfc_io: nfc-io@10000000 {
126 compatible = "atmel,sama5d3-nfc-io", "syscon";
127 reg = <0x10000000 0x8000000>;
131 compatible = "atmel,sama5d3-ebi";
132 #address-cells = <2>;
135 reg = <0x40000000 0x20000000>;
136 ranges = <0x0 0x0 0x40000000 0x8000000
137 0x1 0x0 0x48000000 0x8000000
138 0x2 0x0 0x50000000 0x8000000
139 0x3 0x0 0x58000000 0x8000000>;
140 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>;
143 nand_controller: nand-controller {
144 compatible = "atmel,sama5d3-nand-controller";
145 atmel,nfc-sram = <&nfc_sram>;
146 atmel,nfc-io = <&nfc_io>;
147 ecc-engine = <&pmecc>;
148 #address-cells = <2>;
155 securam: securam@e0000000 {
156 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
157 reg = <0xe0000000 0x4000>;
158 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
159 #address-cells = <1>;
161 ranges = <0 0xe0000000 0x4000>;
165 secumod: secumod@e0004000 {
166 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
167 reg = <0xe0004000 0x4000>;
172 sfrbu: sfr@e0008000 {
173 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
174 reg = <0xe0008000 0x20>;
177 pioA: pinctrl@e0014000 {
178 compatible = "microchip,sama7g5-pinctrl";
179 reg = <0xe0014000 0x800>;
180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-controller;
186 #interrupt-cells = <2>;
189 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
193 compatible = "microchip,sama7g5-pmc", "syscon";
194 reg = <0xe0018000 0x200>;
195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
198 clock-names = "td_slck", "md_slck", "main_xtal";
201 shdwc: shdwc@e001d010 {
202 compatible = "microchip,sama7g5-shdwc", "syscon";
203 reg = <0xe001d010 0x10>;
204 clocks = <&clk32k 0>;
205 #address-cells = <1>;
207 atmel,wakeup-rtc-timer;
208 atmel,wakeup-rtt-timer;
213 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
214 reg = <0xe001d020 0x30>;
215 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clk32k 0>;
219 clk32k: clock-controller@e001d050 {
220 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
221 reg = <0xe001d050 0x4>;
222 clocks = <&slow_xtal>;
226 gpbr: gpbr@e001d060 {
227 compatible = "microchip,sama7g5-gpbr", "syscon";
228 reg = <0xe001d060 0x48>;
232 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
233 reg = <0xe001d0a8 0x30>;
234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clk32k 1>;
238 ps_wdt: watchdog@e001d180 {
239 compatible = "microchip,sama7g5-wdt";
240 reg = <0xe001d180 0x24>;
241 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clk32k 0>;
246 compatible = "microchip,sama7g5-chipid";
247 reg = <0xe0020000 0x8>;
250 tcb1: timer@e0800000 {
251 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
252 #address-cells = <1>;
254 reg = <0xe0800000 0x100>;
255 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
257 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
260 hsmc: hsmc@e0808000 {
261 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
262 reg = <0xe0808000 0x1000>;
263 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
265 #address-cells = <1>;
269 pmecc: ecc-engine@e0808070 {
270 compatible = "atmel,sama5d2-pmecc";
271 reg = <0xe0808070 0x490>,
276 qspi0: spi@e080c000 {
277 compatible = "microchip,sama7g5-ospi";
278 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
279 reg-names = "qspi_base", "qspi_mmap";
280 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
281 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>,
282 <&dma0 AT91_XDMAC_DT_PERID(40)>;
283 dma-names = "tx", "rx";
284 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
285 clock-names = "pclk", "gclk";
286 #address-cells = <1>;
291 qspi1: spi@e0810000 {
292 compatible = "microchip,sama7g5-qspi";
293 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
294 reg-names = "qspi_base", "qspi_mmap";
295 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
296 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>,
297 <&dma0 AT91_XDMAC_DT_PERID(42)>;
298 dma-names = "tx", "rx";
299 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
300 clock-names = "pclk", "gclk";
301 #address-cells = <1>;
307 compatible = "bosch,m_can";
308 reg = <0xe0828000 0x100>, <0x100000 0x7800>;
309 reg-names = "m_can", "message_ram";
310 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "int0", "int1";
313 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
314 clock-names = "hclk", "cclk";
315 assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
316 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
317 assigned-clock-rates = <40000000>;
318 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
323 compatible = "bosch,m_can";
324 reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
325 reg-names = "m_can", "message_ram";
326 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
328 interrupt-names = "int0", "int1";
329 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
330 clock-names = "hclk", "cclk";
331 assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
332 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
333 assigned-clock-rates = <40000000>;
334 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
339 compatible = "bosch,m_can";
340 reg = <0xe0830000 0x100>, <0x100000 0x10000>;
341 reg-names = "m_can", "message_ram";
342 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-names = "int0", "int1";
345 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
346 clock-names = "hclk", "cclk";
347 assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
348 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
349 assigned-clock-rates = <40000000>;
350 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
355 compatible = "bosch,m_can";
356 reg = <0xe0834000 0x100>, <0x110000 0x4400>;
357 reg-names = "m_can", "message_ram";
358 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "int0", "int1";
361 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
362 clock-names = "hclk", "cclk";
363 assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
364 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
365 assigned-clock-rates = <40000000>;
366 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
371 compatible = "bosch,m_can";
372 reg = <0xe0838000 0x100>, <0x110000 0x8800>;
373 reg-names = "m_can", "message_ram";
374 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
376 interrupt-names = "int0", "int1";
377 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
378 clock-names = "hclk", "cclk";
379 assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
380 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
381 assigned-clock-rates = <40000000>;
382 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
387 compatible = "bosch,m_can";
388 reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
389 reg-names = "m_can", "message_ram";
390 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
392 interrupt-names = "int0", "int1";
393 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
394 clock-names = "hclk", "cclk";
395 assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
396 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
397 assigned-clock-rates = <40000000>;
398 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
403 compatible = "microchip,sama7g5-adc";
404 reg = <0xe1000000 0x200>;
405 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&pmc PMC_TYPE_GCK 26>;
407 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
408 assigned-clock-rates = <100000000>;
409 clock-names = "adc_clk";
410 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
412 atmel,min-sample-rate-hz = <200000>;
413 atmel,max-sample-rate-hz = <20000000>;
414 atmel,startup-time-ms = <4>;
418 sdmmc0: mmc@e1204000 {
419 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
420 reg = <0xe1204000 0x4000>;
421 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
423 clock-names = "hclock", "multclk";
424 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
425 assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
426 assigned-clock-rates = <200000000>;
427 microchip,sdcal-inverted;
431 sdmmc1: mmc@e1208000 {
432 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
433 reg = <0xe1208000 0x4000>;
434 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
436 clock-names = "hclock", "multclk";
437 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
438 assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
439 assigned-clock-rates = <200000000>;
440 microchip,sdcal-inverted;
444 sdmmc2: mmc@e120c000 {
445 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
446 reg = <0xe120c000 0x4000>;
447 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
449 clock-names = "hclock", "multclk";
450 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
451 assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
452 assigned-clock-rates = <200000000>;
453 microchip,sdcal-inverted;
458 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
459 reg = <0xe1604000 0x4000>;
460 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>;
466 spdifrx: spdifrx@e1614000 {
467 #sound-dai-cells = <0>;
468 compatible = "microchip,sama7g5-spdifrx";
469 reg = <0xe1614000 0x4000>;
470 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
471 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;
473 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
474 clock-names = "pclk", "gclk";
478 spdiftx: spdiftx@e1618000 {
479 #sound-dai-cells = <0>;
480 compatible = "microchip,sama7g5-spdiftx";
481 reg = <0xe1618000 0x4000>;
482 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
483 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;
485 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
486 clock-names = "pclk", "gclk";
490 compatible = "microchip,sama7g5-i2smcc";
491 #sound-dai-cells = <0>;
492 reg = <0xe161c000 0x4000>;
493 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
494 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;
495 dma-names = "tx", "rx";
496 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
497 clock-names = "pclk", "gclk";
502 compatible = "microchip,sama7g5-i2smcc";
503 #sound-dai-cells = <0>;
504 reg = <0xe1620000 0x4000>;
505 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
506 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;
507 dma-names = "tx", "rx";
508 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
509 clock-names = "pclk", "gclk";
513 eic: interrupt-controller@e1628000 {
514 compatible = "microchip,sama7g5-eic";
515 reg = <0xe1628000 0xec>;
516 interrupt-parent = <&gic>;
517 interrupt-controller;
518 #interrupt-cells = <2>;
519 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
522 clock-names = "pclk";
526 pit64b0: timer@e1800000 {
527 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
528 reg = <0xe1800000 0x4000>;
529 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
531 clock-names = "pclk", "gclk";
534 pit64b1: timer@e1804000 {
535 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
536 reg = <0xe1804000 0x4000>;
537 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;
539 clock-names = "pclk", "gclk";
542 aes: crypto@e1810000 {
543 compatible = "atmel,at91sam9g46-aes";
544 reg = <0xe1810000 0x100>;
545 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
547 clock-names = "aes_clk";
548 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
549 <&dma0 AT91_XDMAC_DT_PERID(2)>;
550 dma-names = "tx", "rx";
553 sha: crypto@e1814000 {
554 compatible = "atmel,at91sam9g46-sha";
555 reg = <0xe1814000 0x100>;
556 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
558 clock-names = "sha_clk";
559 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
563 flx0: flexcom@e1818000 {
564 compatible = "atmel,sama5d2-flexcom";
565 reg = <0xe1818000 0x200>;
566 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
567 #address-cells = <1>;
569 ranges = <0x0 0xe1818000 0x800>;
573 compatible = "atmel,at91sam9260-usart";
575 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
577 clock-names = "usart";
578 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
579 <&dma1 AT91_XDMAC_DT_PERID(5)>;
580 dma-names = "tx", "rx";
587 flx1: flexcom@e181c000 {
588 compatible = "atmel,sama5d2-flexcom";
589 reg = <0xe181c000 0x200>;
590 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
591 #address-cells = <1>;
593 ranges = <0x0 0xe181c000 0x800>;
597 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
599 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>;
602 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
603 atmel,fifo-size = <32>;
604 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
605 <&dma0 AT91_XDMAC_DT_PERID(7)>;
606 dma-names = "tx", "rx";
611 flx3: flexcom@e1824000 {
612 compatible = "atmel,sama5d2-flexcom";
613 reg = <0xe1824000 0x200>;
614 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
615 #address-cells = <1>;
617 ranges = <0x0 0xe1824000 0x800>;
621 compatible = "atmel,at91sam9260-usart";
623 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
625 clock-names = "usart";
626 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
627 <&dma1 AT91_XDMAC_DT_PERID(11)>;
628 dma-names = "tx", "rx";
636 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
637 reg = <0xe2010000 0x100>;
638 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>;
643 tdes: crypto@e2014000 {
644 compatible = "atmel,at91sam9g46-tdes";
645 reg = <0xe2014000 0x100>;
646 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
648 clock-names = "tdes_clk";
649 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
650 <&dma0 AT91_XDMAC_DT_PERID(53)>;
651 dma-names = "tx", "rx";
654 flx4: flexcom@e2018000 {
655 compatible = "atmel,sama5d2-flexcom";
656 reg = <0xe2018000 0x200>;
657 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
658 #address-cells = <1>;
660 ranges = <0x0 0xe2018000 0x800>;
664 compatible = "atmel,at91sam9260-usart";
666 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
668 clock-names = "usart";
669 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
670 <&dma1 AT91_XDMAC_DT_PERID(13)>;
671 dma-names = "tx", "rx";
674 atmel,fifo-size = <16>;
679 flx7: flexcom@e2024000 {
680 compatible = "atmel,sama5d2-flexcom";
681 reg = <0xe2024000 0x200>;
682 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
683 #address-cells = <1>;
685 ranges = <0x0 0xe2024000 0x800>;
689 compatible = "atmel,at91sam9260-usart";
691 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
693 clock-names = "usart";
694 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
695 <&dma1 AT91_XDMAC_DT_PERID(19)>;
696 dma-names = "tx", "rx";
699 atmel,fifo-size = <16>;
704 gmac0: ethernet@e2800000 {
705 compatible = "microchip,sama7g5-gem";
706 reg = <0xe2800000 0x1000>;
707 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
708 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
709 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
710 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
711 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
712 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
714 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
715 assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
716 assigned-clock-rates = <125000000>;
720 gmac1: ethernet@e2804000 {
721 compatible = "microchip,sama7g5-emac";
722 reg = <0xe2804000 0x1000>;
723 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
724 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
726 clock-names = "pclk", "hclk";
730 dma0: dma-controller@e2808000 {
731 compatible = "microchip,sama7g5-dma";
732 reg = <0xe2808000 0x1000>;
733 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
736 clock-names = "dma_clk";
740 dma1: dma-controller@e280c000 {
741 compatible = "microchip,sama7g5-dma";
742 reg = <0xe280c000 0x1000>;
743 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
746 clock-names = "dma_clk";
750 /* Place dma2 here despite it's address */
751 dma2: dma-controller@e1200000 {
752 compatible = "microchip,sama7g5-dma";
753 reg = <0xe1200000 0x1000>;
754 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
757 clock-names = "dma_clk";
762 tcb0: timer@e2814000 {
763 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
764 #address-cells = <1>;
766 reg = <0xe2814000 0x100>;
767 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
769 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
772 flx8: flexcom@e2818000 {
773 compatible = "atmel,sama5d2-flexcom";
774 reg = <0xe2818000 0x200>;
775 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
776 #address-cells = <1>;
778 ranges = <0x0 0xe2818000 0x800>;
782 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
784 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
785 #address-cells = <1>;
787 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
788 atmel,fifo-size = <32>;
789 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
790 <&dma0 AT91_XDMAC_DT_PERID(21)>;
791 dma-names = "tx", "rx";
796 flx9: flexcom@e281c000 {
797 compatible = "atmel,sama5d2-flexcom";
798 reg = <0xe281c000 0x200>;
799 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
800 #address-cells = <1>;
802 ranges = <0x0 0xe281c000 0x800>;
806 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
808 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
809 #address-cells = <1>;
811 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
812 atmel,fifo-size = <32>;
813 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
814 <&dma0 AT91_XDMAC_DT_PERID(23)>;
815 dma-names = "tx", "rx";
820 flx11: flexcom@e2824000 {
821 compatible = "atmel,sama5d2-flexcom";
822 reg = <0xe2824000 0x200>;
823 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
824 #address-cells = <1>;
826 ranges = <0x0 0xe2824000 0x800>;
830 compatible = "atmel,at91rm9200-spi";
832 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
834 clock-names = "spi_clk";
835 #address-cells = <1>;
837 atmel,fifo-size = <32>;
838 dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
839 <&dma0 AT91_XDMAC_DT_PERID(28)>;
840 dma-names = "rx", "tx";
845 uddrc: uddrc@e3800000 {
846 compatible = "microchip,sama7g5-uddrc";
847 reg = <0xe3800000 0x4000>;
850 ddr3phy: ddr3phy@e3804000 {
851 compatible = "microchip,sama7g5-ddr3phy";
852 reg = <0xe3804000 0x1000>;
855 gic: interrupt-controller@e8c11000 {
856 compatible = "arm,cortex-a7-gic";
857 #interrupt-cells = <3>;
858 #address-cells = <0>;
859 interrupt-controller;
860 reg = <0xe8c11000 0x1000>,