arch/arm/boot/dts/sama5d4.dtsi

   1 /*
   2  * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
   3  *
   4  *  Copyright (C) 2014 Atmel,
   5  *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "skeleton.dtsi"
  47 #include <dt-bindings/clock/at91.h>
  48 #include <dt-bindings/dma/at91.h>
  49 #include <dt-bindings/pinctrl/at91.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/gpio/gpio.h>
  52
  53 / {
  54         model = "Atmel SAMA5D4 family SoC";
  55         compatible = "atmel,sama5d4";
  56         interrupt-parent = <&aic>;
  57
  58         aliases {
  59                 serial0 = &usart3;
  60                 serial1 = &usart4;
  61                 serial2 = &usart2;
  62                 gpio0 = &pioA;
  63                 gpio1 = &pioB;
  64                 gpio2 = &pioC;
  65                 gpio3 = &pioD;
  66                 gpio4 = &pioE;
  67                 pwm0 = &pwm0;
  68                 ssc0 = &ssc0;
  69                 ssc1 = &ssc1;
  70                 tcb0 = &tcb0;
  71                 tcb1 = &tcb1;
  72                 i2c0 = &i2c0;
  73                 i2c1 = &i2c1;
  74                 i2c2 = &i2c2;
  75         };
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a5";
  83                         reg = <0>;
  84                         next-level-cache = <&L2>;
  85                 };
  86         };
  87
  88         memory {
  89                 reg = <0x20000000 0x20000000>;
  90         };
  91
  92         clocks {
  93                 slow_xtal: slow_xtal {
  94                         compatible = "fixed-clock";
  95                         #clock-cells = <0>;
  96                         clock-frequency = <0>;
  97                 };
  98
  99                 main_xtal: main_xtal {
 100                         compatible = "fixed-clock";
 101                         #clock-cells = <0>;
 102                         clock-frequency = <0>;
 103                 };
 104
 105                 adc_op_clk: adc_op_clk{
 106                         compatible = "fixed-clock";
 107                         #clock-cells = <0>;
 108                         clock-frequency = <1000000>;
 109                 };
 110         };
 111
 112         ns_sram: sram@00210000 {
 113                 compatible = "mmio-sram";
 114                 reg = <0x00210000 0x10000>;
 115         };
 116
 117         ahb {
 118                 compatible = "simple-bus";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 ranges;
 122
 123                 usb0: gadget@00400000 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         compatible = "atmel,at91sam9rl-udc";
 127                         reg = <0x00400000 0x100000
 128                                0xfc02c000 0x4000>;
 129                         interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
 130                         clocks = <&udphs_clk>, <&utmi>;
 131                         clock-names = "pclk", "hclk";
 132                         status = "disabled";
 133
 134                         ep0 {
 135                                 reg = <0>;
 136                                 atmel,fifo-size = <64>;
 137                                 atmel,nb-banks = <1>;
 138                         };
 139
 140                         ep1 {
 141                                 reg = <1>;
 142                                 atmel,fifo-size = <1024>;
 143                                 atmel,nb-banks = <3>;
 144                                 atmel,can-dma;
 145                                 atmel,can-isoc;
 146                         };
 147
 148                         ep2 {
 149                                 reg = <2>;
 150                                 atmel,fifo-size = <1024>;
 151                                 atmel,nb-banks = <3>;
 152                                 atmel,can-dma;
 153                                 atmel,can-isoc;
 154                         };
 155
 156                         ep3 {
 157                                 reg = <3>;
 158                                 atmel,fifo-size = <1024>;
 159                                 atmel,nb-banks = <2>;
 160                                 atmel,can-dma;
 161                                 atmel,can-isoc;
 162                         };
 163
 164                         ep4 {
 165                                 reg = <4>;
 166                                 atmel,fifo-size = <1024>;
 167                                 atmel,nb-banks = <2>;
 168                                 atmel,can-dma;
 169                                 atmel,can-isoc;
 170                         };
 171
 172                         ep5 {
 173                                 reg = <5>;
 174                                 atmel,fifo-size = <1024>;
 175                                 atmel,nb-banks = <2>;
 176                                 atmel,can-dma;
 177                                 atmel,can-isoc;
 178                         };
 179
 180                         ep6 {
 181                                 reg = <6>;
 182                                 atmel,fifo-size = <1024>;
 183                                 atmel,nb-banks = <2>;
 184                                 atmel,can-dma;
 185                                 atmel,can-isoc;
 186                         };
 187
 188                         ep7 {
 189                                 reg = <7>;
 190                                 atmel,fifo-size = <1024>;
 191                                 atmel,nb-banks = <2>;
 192                                 atmel,can-dma;
 193                                 atmel,can-isoc;
 194                         };
 195
 196                         ep8 {
 197                                 reg = <8>;
 198                                 atmel,fifo-size = <1024>;
 199                                 atmel,nb-banks = <2>;
 200                                 atmel,can-isoc;
 201                         };
 202
 203                         ep9 {
 204                                 reg = <9>;
 205                                 atmel,fifo-size = <1024>;
 206                                 atmel,nb-banks = <2>;
 207                                 atmel,can-isoc;
 208                         };
 209
 210                         ep10 {
 211                                 reg = <10>;
 212                                 atmel,fifo-size = <1024>;
 213                                 atmel,nb-banks = <2>;
 214                                 atmel,can-isoc;
 215                         };
 216
 217                         ep11 {
 218                                 reg = <11>;
 219                                 atmel,fifo-size = <1024>;
 220                                 atmel,nb-banks = <2>;
 221                                 atmel,can-isoc;
 222                         };
 223
 224                         ep12 {
 225                                 reg = <12>;
 226                                 atmel,fifo-size = <1024>;
 227                                 atmel,nb-banks = <2>;
 228                                 atmel,can-isoc;
 229                         };
 230
 231                         ep13 {
 232                                 reg = <13>;
 233                                 atmel,fifo-size = <1024>;
 234                                 atmel,nb-banks = <2>;
 235                                 atmel,can-isoc;
 236                         };
 237
 238                         ep14 {
 239                                 reg = <14>;
 240                                 atmel,fifo-size = <1024>;
 241                                 atmel,nb-banks = <2>;
 242                                 atmel,can-isoc;
 243                         };
 244
 245                         ep15 {
 246                                 reg = <15>;
 247                                 atmel,fifo-size = <1024>;
 248                                 atmel,nb-banks = <2>;
 249                                 atmel,can-isoc;
 250                         };
 251                 };
 252
 253                 usb1: ohci@00500000 {
 254                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 255                         reg = <0x00500000 0x100000>;
 256                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 257                         clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
 258                                  <&uhpck>;
 259                         clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
 260                         status = "disabled";
 261                 };
 262
 263                 usb2: ehci@00600000 {
 264                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 265                         reg = <0x00600000 0x100000>;
 266                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 267                         clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
 268                         clock-names = "usb_clk", "ehci_clk", "uhpck";
 269                         status = "disabled";
 270                 };
 271
 272                 L2: cache-controller@00a00000 {
 273                         compatible = "arm,pl310-cache";
 274                         reg = <0x00a00000 0x1000>;
 275                         interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
 276                         cache-unified;
 277                         cache-level = <2>;
 278                 };
 279
 280                 nand0: nand@80000000 {
 281                         compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
 282                         #address-cells = <1>;
 283                         #size-cells = <1>;
 284                         ranges;
 285                         reg = < 0x80000000 0x08000000   /* EBI CS3 */
 286                                 0xfc05c070 0x00000490   /* SMC PMECC regs */
 287                                 0xfc05c500 0x00000100   /* SMC PMECC Error Location regs */
 288                                 >;
 289                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
 290                         atmel,nand-addr-offset = <21>;
 291                         atmel,nand-cmd-offset = <22>;
 292                         atmel,nand-has-dma;
 293                         pinctrl-names = "default";
 294                         pinctrl-0 = <&pinctrl_nand>;
 295                         status = "disabled";
 296
 297                         nfc@90000000 {
 298                                 compatible = "atmel,sama5d3-nfc";
 299                                 #address-cells = <1>;
 300                                 #size-cells = <1>;
 301                                 reg = <
 302                                         0x90000000 0x10000000   /* NFC Command Registers */
 303                                         0xfc05c000 0x00000070   /* NFC HSMC regs */
 304                                         0x00100000 0x00100000   /* NFC SRAM banks */
 305                                          >;
 306                                 clocks = <&hsmc_clk>;
 307                                 atmel,write-by-sram;
 308                         };
 309                 };
 310
 311                 apb {
 312                         compatible = "simple-bus";
 313                         #address-cells = <1>;
 314                         #size-cells = <1>;
 315                         ranges;
 316
 317                         dma1: dma-controller@f0004000 {
 318                                 compatible = "atmel,sama5d4-dma";
 319                                 reg = <0xf0004000 0x200>;
 320                                 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
 321                                 #dma-cells = <1>;
 322                                 clocks = <&dma1_clk>;
 323                                 clock-names = "dma_clk";
 324                         };
 325
 326                         isi: isi@f0008000 {
 327                                 compatible = "atmel,at91sam9g45-isi";
 328                                 reg = <0xf0008000 0x4000>;
 329                                 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
 330                                 pinctrl-names = "default";
 331                                 pinctrl-0 = <&pinctrl_isi_data_0_7>;
 332                                 clocks = <&isi_clk>;
 333                                 clock-names = "isi_clk";
 334                                 status = "disabled";
 335                                 port {
 336                                         #address-cells = <1>;
 337                                         #size-cells = <0>;
 338                                 };
 339                         };
 340
 341                         ramc0: ramc@f0010000 {
 342                                 compatible = "atmel,sama5d3-ddramc";
 343                                 reg = <0xf0010000 0x200>;
 344                                 clocks = <&ddrck>, <&mpddr_clk>;
 345                                 clock-names = "ddrck", "mpddr";
 346                         };
 347
 348                         dma0: dma-controller@f0014000 {
 349                                 compatible = "atmel,sama5d4-dma";
 350                                 reg = <0xf0014000 0x200>;
 351                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
 352                                 #dma-cells = <1>;
 353                                 clocks = <&dma0_clk>;
 354                                 clock-names = "dma_clk";
 355                         };
 356
 357                         pmc: pmc@f0018000 {
 358                                 compatible = "atmel,sama5d3-pmc";
 359                                 reg = <0xf0018000 0x120>;
 360                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 361                                 interrupt-controller;
 362                                 #address-cells = <1>;
 363                                 #size-cells = <0>;
 364                                 #interrupt-cells = <1>;
 365
 366                                 main_rc_osc: main_rc_osc {
 367                                         compatible = "atmel,at91sam9x5-clk-main-rc-osc";
 368                                         #clock-cells = <0>;
 369                                         interrupt-parent = <&pmc>;
 370                                         interrupts = <AT91_PMC_MOSCRCS>;
 371                                         clock-frequency = <12000000>;
 372                                         clock-accuracy = <100000000>;
 373                                 };
 374
 375                                 main_osc: main_osc {
 376                                         compatible = "atmel,at91rm9200-clk-main-osc";
 377                                         #clock-cells = <0>;
 378                                         interrupt-parent = <&pmc>;
 379                                         interrupts = <AT91_PMC_MOSCS>;
 380                                         clocks = <&main_xtal>;
 381                                 };
 382
 383                                 main: mainck {
 384                                         compatible = "atmel,at91sam9x5-clk-main";
 385                                         #clock-cells = <0>;
 386                                         interrupt-parent = <&pmc>;
 387                                         interrupts = <AT91_PMC_MOSCSELS>;
 388                                         clocks = <&main_rc_osc &main_osc>;
 389                                 };
 390
 391                                 plla: pllack {
 392                                         compatible = "atmel,sama5d3-clk-pll";
 393                                         #clock-cells = <0>;
 394                                         interrupt-parent = <&pmc>;
 395                                         interrupts = <AT91_PMC_LOCKA>;
 396                                         clocks = <&main>;
 397                                         reg = <0>;
 398                                         atmel,clk-input-range = <12000000 12000000>;
 399                                         #atmel,pll-clk-output-range-cells = <4>;
 400                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 401                                 };
 402
 403                                 plladiv: plladivck {
 404                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 405                                         #clock-cells = <0>;
 406                                         clocks = <&plla>;
 407                                 };
 408
 409                                 utmi: utmick {
 410                                         compatible = "atmel,at91sam9x5-clk-utmi";
 411                                         #clock-cells = <0>;
 412                                         interrupt-parent = <&pmc>;
 413                                         interrupts = <AT91_PMC_LOCKU>;
 414                                         clocks = <&main>;
 415                                 };
 416
 417                                 mck: masterck {
 418                                         compatible = "atmel,at91sam9x5-clk-master";
 419                                         #clock-cells = <0>;
 420                                         interrupt-parent = <&pmc>;
 421                                         interrupts = <AT91_PMC_MCKRDY>;
 422                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
 423                                         atmel,clk-output-range = <125000000 177000000>;
 424                                         atmel,clk-divisors = <1 2 4 3>;
 425                                 };
 426
 427                                 h32ck: h32mxck {
 428                                         #clock-cells = <0>;
 429                                         compatible = "atmel,sama5d4-clk-h32mx";
 430                                         clocks = <&mck>;
 431                                 };
 432
 433                                 usb: usbck {
 434                                         compatible = "atmel,at91sam9x5-clk-usb";
 435                                         #clock-cells = <0>;
 436                                         clocks = <&plladiv>, <&utmi>;
 437                                 };
 438
 439                                 prog: progck {
 440                                         compatible = "atmel,at91sam9x5-clk-programmable";
 441                                         #address-cells = <1>;
 442                                         #size-cells = <0>;
 443                                         interrupt-parent = <&pmc>;
 444                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 445
 446                                         prog0: prog0 {
 447                                                 #clock-cells = <0>;
 448                                                 reg = <0>;
 449                                                 interrupts = <AT91_PMC_PCKRDY(0)>;
 450                                         };
 451
 452                                         prog1: prog1 {
 453                                                 #clock-cells = <0>;
 454                                                 reg = <1>;
 455                                                 interrupts = <AT91_PMC_PCKRDY(1)>;
 456                                         };
 457
 458                                         prog2: prog2 {
 459                                                 #clock-cells = <0>;
 460                                                 reg = <2>;
 461                                                 interrupts = <AT91_PMC_PCKRDY(2)>;
 462                                         };
 463                                 };
 464
 465                                 smd: smdclk {
 466                                         compatible = "atmel,at91sam9x5-clk-smd";
 467                                         #clock-cells = <0>;
 468                                         clocks = <&plladiv>, <&utmi>;
 469                                 };
 470
 471                                 systemck {
 472                                         compatible = "atmel,at91rm9200-clk-system";
 473                                         #address-cells = <1>;
 474                                         #size-cells = <0>;
 475
 476                                         ddrck: ddrck {
 477                                                 #clock-cells = <0>;
 478                                                 reg = <2>;
 479                                                 clocks = <&mck>;
 480                                         };
 481
 482                                         lcdck: lcdck {
 483                                                 #clock-cells = <0>;
 484                                                 reg = <4>;
 485                                                 clocks = <&smd>;
 486                                         };
 487
 488                                         smdck: smdck {
 489                                                 #clock-cells = <0>;
 490                                                 reg = <4>;
 491                                                 clocks = <&smd>;
 492                                         };
 493
 494                                         uhpck: uhpck {
 495                                                 #clock-cells = <0>;
 496                                                 reg = <6>;
 497                                                 clocks = <&usb>;
 498                                         };
 499
 500                                         udpck: udpck {
 501                                                 #clock-cells = <0>;
 502                                                 reg = <7>;
 503                                                 clocks = <&usb>;
 504                                         };
 505
 506                                         pck0: pck0 {
 507                                                 #clock-cells = <0>;
 508                                                 reg = <8>;
 509                                                 clocks = <&prog0>;
 510                                         };
 511
 512                                         pck1: pck1 {
 513                                                 #clock-cells = <0>;
 514                                                 reg = <9>;
 515                                                 clocks = <&prog1>;
 516                                         };
 517
 518                                         pck2: pck2 {
 519                                                 #clock-cells = <0>;
 520                                                 reg = <10>;
 521                                                 clocks = <&prog2>;
 522                                         };
 523                                 };
 524
 525                                 periph32ck {
 526                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 527                                         #address-cells = <1>;
 528                                         #size-cells = <0>;
 529                                         clocks = <&h32ck>;
 530
 531                                         pioD_clk: pioD_clk {
 532                                                 #clock-cells = <0>;
 533                                                 reg = <5>;
 534                                         };
 535
 536                                         usart0_clk: usart0_clk {
 537                                                 #clock-cells = <0>;
 538                                                 reg = <6>;
 539                                         };
 540
 541                                         usart1_clk: usart1_clk {
 542                                                 #clock-cells = <0>;
 543                                                 reg = <7>;
 544                                         };
 545
 546                                         icm_clk: icm_clk {
 547                                                 #clock-cells = <0>;
 548                                                 reg = <9>;
 549                                         };
 550
 551                                         aes_clk: aes_clk {
 552                                                 #clock-cells = <0>;
 553                                                 reg = <12>;
 554                                         };
 555
 556                                         tdes_clk: tdes_clk {
 557                                                 #clock-cells = <0>;
 558                                                 reg = <14>;
 559                                         };
 560
 561                                         sha_clk: sha_clk {
 562                                                 #clock-cells = <0>;
 563                                                 reg = <15>;
 564                                         };
 565
 566                                         matrix1_clk: matrix1_clk {
 567                                                 #clock-cells = <0>;
 568                                                 reg = <17>;
 569                                         };
 570
 571                                         hsmc_clk: hsmc_clk {
 572                                                 #clock-cells = <0>;
 573                                                 reg = <22>;
 574                                         };
 575
 576                                         pioA_clk: pioA_clk {
 577                                                 #clock-cells = <0>;
 578                                                 reg = <23>;
 579                                         };
 580
 581                                         pioB_clk: pioB_clk {
 582                                                 #clock-cells = <0>;
 583                                                 reg = <24>;
 584                                         };
 585
 586                                         pioC_clk: pioC_clk {
 587                                                 #clock-cells = <0>;
 588                                                 reg = <25>;
 589                                         };
 590
 591                                         pioE_clk: pioE_clk {
 592                                                 #clock-cells = <0>;
 593                                                 reg = <26>;
 594                                         };
 595
 596                                         uart0_clk: uart0_clk {
 597                                                 #clock-cells = <0>;
 598                                                 reg = <27>;
 599                                         };
 600
 601                                         uart1_clk: uart1_clk {
 602                                                 #clock-cells = <0>;
 603                                                 reg = <28>;
 604                                         };
 605
 606                                         usart2_clk: usart2_clk {
 607                                                 #clock-cells = <0>;
 608                                                 reg = <29>;
 609                                         };
 610
 611                                         usart3_clk: usart3_clk {
 612                                                 #clock-cells = <0>;
 613                                                 reg = <30>;
 614                                         };
 615
 616                                         usart4_clk: usart4_clk {
 617                                                 #clock-cells = <0>;
 618                                                 reg = <31>;
 619                                         };
 620
 621                                         twi0_clk: twi0_clk {
 622                                                 reg = <32>;
 623                                                 #clock-cells = <0>;
 624                                         };
 625
 626                                         twi1_clk: twi1_clk {
 627                                                 #clock-cells = <0>;
 628                                                 reg = <33>;
 629                                         };
 630
 631                                         twi2_clk: twi2_clk {
 632                                                 #clock-cells = <0>;
 633                                                 reg = <34>;
 634                                         };
 635
 636                                         mci0_clk: mci0_clk {
 637                                                 #clock-cells = <0>;
 638                                                 reg = <35>;
 639                                         };
 640
 641                                         mci1_clk: mci1_clk {
 642                                                 #clock-cells = <0>;
 643                                                 reg = <36>;
 644                                         };
 645
 646                                         spi0_clk: spi0_clk {
 647                                                 #clock-cells = <0>;
 648                                                 reg = <37>;
 649                                         };
 650
 651                                         spi1_clk: spi1_clk {
 652                                                 #clock-cells = <0>;
 653                                                 reg = <38>;
 654                                         };
 655
 656                                         spi2_clk: spi2_clk {
 657                                                 #clock-cells = <0>;
 658                                                 reg = <39>;
 659                                         };
 660
 661                                         tcb0_clk: tcb0_clk {
 662                                                 #clock-cells = <0>;
 663                                                 reg = <40>;
 664                                         };
 665
 666                                         tcb1_clk: tcb1_clk {
 667                                                 #clock-cells = <0>;
 668                                                 reg = <41>;
 669                                         };
 670
 671                                         tcb2_clk: tcb2_clk {
 672                                                 #clock-cells = <0>;
 673                                                 reg = <42>;
 674                                         };
 675
 676                                         pwm_clk: pwm_clk {
 677                                                 #clock-cells = <0>;
 678                                                 reg = <43>;
 679                                         };
 680
 681                                         adc_clk: adc_clk {
 682                                                 #clock-cells = <0>;
 683                                                 reg = <44>;
 684                                         };
 685
 686                                         dbgu_clk: dbgu_clk {
 687                                                 #clock-cells = <0>;
 688                                                 reg = <45>;
 689                                         };
 690
 691                                         uhphs_clk: uhphs_clk {
 692                                                 #clock-cells = <0>;
 693                                                 reg = <46>;
 694                                         };
 695
 696                                         udphs_clk: udphs_clk {
 697                                                 #clock-cells = <0>;
 698                                                 reg = <47>;
 699                                         };
 700
 701                                         ssc0_clk: ssc0_clk {
 702                                                 #clock-cells = <0>;
 703                                                 reg = <48>;
 704                                         };
 705
 706                                         ssc1_clk: ssc1_clk {
 707                                                 #clock-cells = <0>;
 708                                                 reg = <49>;
 709                                         };
 710
 711                                         trng_clk: trng_clk {
 712                                                 #clock-cells = <0>;
 713                                                 reg = <53>;
 714                                         };
 715
 716                                         macb0_clk: macb0_clk {
 717                                                 #clock-cells = <0>;
 718                                                 reg = <54>;
 719                                         };
 720
 721                                         macb1_clk: macb1_clk {
 722                                                 #clock-cells = <0>;
 723                                                 reg = <55>;
 724                                         };
 725
 726                                         fuse_clk: fuse_clk {
 727                                                 #clock-cells = <0>;
 728                                                 reg = <57>;
 729                                         };
 730
 731                                         securam_clk: securam_clk {
 732                                                 #clock-cells = <0>;
 733                                                 reg = <59>;
 734                                         };
 735
 736                                         smd_clk: smd_clk {
 737                                                 #clock-cells = <0>;
 738                                                 reg = <61>;
 739                                         };
 740
 741                                         twi3_clk: twi3_clk {
 742                                                 #clock-cells = <0>;
 743                                                 reg = <62>;
 744                                         };
 745
 746                                         catb_clk: catb_clk {
 747                                                 #clock-cells = <0>;
 748                                                 reg = <63>;
 749                                         };
 750                                 };
 751
 752                                 periph64ck {
 753                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 754                                         #address-cells = <1>;
 755                                         #size-cells = <0>;
 756                                         clocks = <&mck>;
 757
 758                                         dma0_clk: dma0_clk {
 759                                                 #clock-cells = <0>;
 760                                                 reg = <8>;
 761                                         };
 762
 763                                         cpkcc_clk: cpkcc_clk {
 764                                                 #clock-cells = <0>;
 765                                                 reg = <10>;
 766                                         };
 767
 768                                         aesb_clk: aesb_clk {
 769                                                 #clock-cells = <0>;
 770                                                 reg = <13>;
 771                                         };
 772
 773                                         mpddr_clk: mpddr_clk {
 774                                                 #clock-cells = <0>;
 775                                                 reg = <16>;
 776                                         };
 777
 778                                         matrix0_clk: matrix0_clk {
 779                                                 #clock-cells = <0>;
 780                                                 reg = <18>;
 781                                         };
 782
 783                                         vdec_clk: vdec_clk {
 784                                                 #clock-cells = <0>;
 785                                                 reg = <19>;
 786                                         };
 787
 788                                         dma1_clk: dma1_clk {
 789                                                 #clock-cells = <0>;
 790                                                 reg = <50>;
 791                                         };
 792
 793                                         lcd_clk: lcd_clk {
 794                                                 #clock-cells = <0>;
 795                                                 reg = <51>;
 796                                         };
 797
 798                                         isi_clk: isi_clk {
 799                                                 #clock-cells = <0>;
 800                                                 reg = <52>;
 801                                         };
 802                                 };
 803                         };
 804
 805                         mmc0: mmc@f8000000 {
 806                                 compatible = "atmel,hsmci";
 807                                 reg = <0xf8000000 0x600>;
 808                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
 809                                 dmas = <&dma1
 810                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 811                                         | AT91_XDMAC_DT_PERID(0))>;
 812                                 dma-names = "rxtx";
 813                                 pinctrl-names = "default";
 814                                 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
 815                                 status = "disabled";
 816                                 #address-cells = <1>;
 817                                 #size-cells = <0>;
 818                                 clocks = <&mci0_clk>;
 819                                 clock-names = "mci_clk";
 820                         };
 821
 822                         ssc0: ssc@f8008000 {
 823                                 compatible = "atmel,at91sam9g45-ssc";
 824                                 reg = <0xf8008000 0x4000>;
 825                                 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
 826                                 pinctrl-names = "default";
 827                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 828                                 dmas = <&dma1
 829                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 830                                         | AT91_XDMAC_DT_PERID(26))>,
 831                                        <&dma1
 832                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 833                                         | AT91_XDMAC_DT_PERID(27))>;
 834                                 dma-names = "tx", "rx";
 835                                 clocks = <&ssc0_clk>;
 836                                 clock-names = "pclk";
 837                                 status = "disabled";
 838                         };
 839
 840                         pwm0: pwm@f800c000 {
 841                                 compatible = "atmel,sama5d3-pwm";
 842                                 reg = <0xf800c000 0x300>;
 843                                 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
 844                                 #pwm-cells = <3>;
 845                                 clocks = <&pwm_clk>;
 846                                 status = "disabled";
 847                         };
 848
 849                         spi0: spi@f8010000 {
 850                                 #address-cells = <1>;
 851                                 #size-cells = <0>;
 852                                 compatible = "atmel,at91rm9200-spi";
 853                                 reg = <0xf8010000 0x100>;
 854                                 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
 855                                 dmas = <&dma1
 856                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 857                                         | AT91_XDMAC_DT_PERID(10))>,
 858                                        <&dma1
 859                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 860                                         | AT91_XDMAC_DT_PERID(11))>;
 861                                 dma-names = "tx", "rx";
 862                                 pinctrl-names = "default";
 863                                 pinctrl-0 = <&pinctrl_spi0>;
 864                                 clocks = <&spi0_clk>;
 865                                 clock-names = "spi_clk";
 866                                 status = "disabled";
 867                         };
 868
 869                         i2c0: i2c@f8014000 {
 870                                 compatible = "atmel,at91sam9x5-i2c";
 871                                 reg = <0xf8014000 0x4000>;
 872                                 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
 873                                 dmas = <&dma1
 874                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 875                                         | AT91_XDMAC_DT_PERID(2))>,
 876                                        <&dma1
 877                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 878                                         | AT91_XDMAC_DT_PERID(3))>;
 879                                 dma-names = "tx", "rx";
 880                                 pinctrl-names = "default";
 881                                 pinctrl-0 = <&pinctrl_i2c0>;
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 clocks = <&twi0_clk>;
 885                                 status = "disabled";
 886                         };
 887
 888                         i2c1: i2c@f8018000 {
 889                                 compatible = "atmel,at91sam9x5-i2c";
 890                                 reg = <0xf8018000 0x4000>;
 891                                 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
 892                                 dmas = <&dma1
 893                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 894                                         AT91_XDMAC_DT_PERID(4)>,
 895                                        <&dma1
 896                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 897                                         AT91_XDMAC_DT_PERID(5)>;
 898                                 dma-names = "tx", "rx";
 899                                 pinctrl-names = "default";
 900                                 pinctrl-0 = <&pinctrl_i2c1>;
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 clocks = <&twi1_clk>;
 904                                 status = "disabled";
 905                         };
 906
 907                         tcb0: timer@f801c000 {
 908                                 compatible = "atmel,at91sam9x5-tcb";
 909                                 reg = <0xf801c000 0x100>;
 910                                 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
 911                                 clocks = <&tcb0_clk>;
 912                                 clock-names = "t0_clk";
 913                         };
 914
 915                         macb0: ethernet@f8020000 {
 916                                 compatible = "atmel,sama5d4-gem";
 917                                 reg = <0xf8020000 0x100>;
 918                                 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
 919                                 pinctrl-names = "default";
 920                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
 921                                 #address-cells = <1>;
 922                                 #size-cells = <0>;
 923                                 clocks = <&macb0_clk>, <&macb0_clk>;
 924                                 clock-names = "hclk", "pclk";
 925                                 status = "disabled";
 926                         };
 927
 928                         i2c2: i2c@f8024000 {
 929                                 compatible = "atmel,at91sam9x5-i2c";
 930                                 reg = <0xf8024000 0x4000>;
 931                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
 932                                 dmas = <&dma1
 933                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 934                                         | AT91_XDMAC_DT_PERID(6))>,
 935                                        <&dma1
 936                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 937                                         | AT91_XDMAC_DT_PERID(7))>;
 938                                 dma-names = "tx", "rx";
 939                                 pinctrl-names = "default";
 940                                 pinctrl-0 = <&pinctrl_i2c2>;
 941                                 #address-cells = <1>;
 942                                 #size-cells = <0>;
 943                                 clocks = <&twi2_clk>;
 944                                 status = "disabled";
 945                         };
 946
 947                         sfr: sfr@f8028000 {
 948                                 compatible = "atmel,sama5d4-sfr", "syscon";
 949                                 reg = <0xf8028000 0x60>;
 950                         };
 951
 952                         mmc1: mmc@fc000000 {
 953                                 compatible = "atmel,hsmci";
 954                                 reg = <0xfc000000 0x600>;
 955                                 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
 956                                 dmas = <&dma1
 957                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 958                                         | AT91_XDMAC_DT_PERID(1))>;
 959                                 dma-names = "rxtx";
 960                                 pinctrl-names = "default";
 961                                 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
 962                                 status = "disabled";
 963                                 #address-cells = <1>;
 964                                 #size-cells = <0>;
 965                                 clocks = <&mci1_clk>;
 966                                 clock-names = "mci_clk";
 967                         };
 968
 969                         usart2: serial@fc008000 {
 970                                 compatible = "atmel,at91sam9260-usart";
 971                                 reg = <0xfc008000 0x100>;
 972                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
 973                                 dmas = <&dma1
 974                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 975                                         | AT91_XDMAC_DT_PERID(16))>,
 976                                        <&dma1
 977                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 978                                         | AT91_XDMAC_DT_PERID(17))>;
 979                                 dma-names = "tx", "rx";
 980                                 pinctrl-names = "default";
 981                                 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
 982                                 clocks = <&usart2_clk>;
 983                                 clock-names = "usart";
 984                                 status = "disabled";
 985                         };
 986
 987                         usart3: serial@fc00c000 {
 988                                 compatible = "atmel,at91sam9260-usart";
 989                                 reg = <0xfc00c000 0x100>;
 990                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
 991                                 dmas = <&dma1
 992                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 993                                         | AT91_XDMAC_DT_PERID(18))>,
 994                                        <&dma1
 995                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 996                                         | AT91_XDMAC_DT_PERID(19))>;
 997                                 dma-names = "tx", "rx";
 998                                 pinctrl-names = "default";
 999                                 pinctrl-0 = <&pinctrl_usart3>;
1000                                 clocks = <&usart3_clk>;
1001                                 clock-names = "usart";
1002                                 status = "disabled";
1003                         };
1004
1005                         usart4: serial@fc010000 {
1006                                 compatible = "atmel,at91sam9260-usart";
1007                                 reg = <0xfc010000 0x100>;
1008                                 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1009                                 dmas = <&dma1
1010                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1011                                         | AT91_XDMAC_DT_PERID(20))>,
1012                                        <&dma1
1013                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1014                                         | AT91_XDMAC_DT_PERID(21))>;
1015                                 dma-names = "tx", "rx";
1016                                 pinctrl-names = "default";
1017                                 pinctrl-0 = <&pinctrl_usart4>;
1018                                 clocks = <&usart4_clk>;
1019                                 clock-names = "usart";
1020                                 status = "disabled";
1021                         };
1022
1023                         ssc1: ssc@fc014000 {
1024                                 compatible = "atmel,at91sam9g45-ssc";
1025                                 reg = <0xfc014000 0x4000>;
1026                                 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1027                                 pinctrl-names = "default";
1028                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1029                                 dmas = <&dma1
1030                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1031                                         | AT91_XDMAC_DT_PERID(28))>,
1032                                        <&dma1
1033                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1034                                         | AT91_XDMAC_DT_PERID(29))>;
1035                                 dma-names = "tx", "rx";
1036                                 clocks = <&ssc1_clk>;
1037                                 clock-names = "pclk";
1038                                 status = "disabled";
1039                         };
1040
1041                         tcb1: timer@fc020000 {
1042                                 compatible = "atmel,at91sam9x5-tcb";
1043                                 reg = <0xfc020000 0x100>;
1044                                 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1045                                 clocks = <&tcb1_clk>;
1046                                 clock-names = "t0_clk";
1047                         };
1048
1049                         adc0: adc@fc034000 {
1050                                 compatible = "atmel,at91sam9x5-adc";
1051                                 reg = <0xfc034000 0x100>;
1052                                 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1053                                 pinctrl-names = "default";
1054                                 pinctrl-0 = <
1055                                         /* external trigger is conflict with USBA_VBUS */
1056                                         &pinctrl_adc0_ad0
1057                                         &pinctrl_adc0_ad1
1058                                         &pinctrl_adc0_ad2
1059                                         &pinctrl_adc0_ad3
1060                                         &pinctrl_adc0_ad4
1061                                         >;
1062                                 clocks = <&adc_clk>,
1063                                          <&adc_op_clk>;
1064                                 clock-names = "adc_clk", "adc_op_clk";
1065                                 atmel,adc-channels-used = <0x01f>;
1066                                 atmel,adc-startup-time = <40>;
1067                                 atmel,adc-use-external;
1068                                 atmel,adc-vref = <3000>;
1069                                 atmel,adc-res = <8 10>;
1070                                 atmel,adc-sample-hold-time = <11>;
1071                                 atmel,adc-res-names = "lowres", "highres";
1072                                 atmel,adc-ts-pressure-threshold = <10000>;
1073                                 status = "disabled";
1074
1075                                 trigger@0 {
1076                                         trigger-name = "external-rising";
1077                                         trigger-value = <0x1>;
1078                                         trigger-external;
1079                                 };
1080                                 trigger@1 {
1081                                         trigger-name = "external-falling";
1082                                         trigger-value = <0x2>;
1083                                         trigger-external;
1084                                 };
1085                                 trigger@2 {
1086                                         trigger-name = "external-any";
1087                                         trigger-value = <0x3>;
1088                                         trigger-external;
1089                                 };
1090                                 trigger@3 {
1091                                         trigger-name = "continuous";
1092                                         trigger-value = <0x6>;
1093                                 };
1094                         };
1095
1096                         aes@fc044000 {
1097                                 compatible = "atmel,at91sam9g46-aes";
1098                                 reg = <0xfc044000 0x100>;
1099                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1100                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1101                                         AT91_XDMAC_DT_PERID(41)>,
1102                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1103                                         AT91_XDMAC_DT_PERID(40)>;
1104                                 dma-names = "tx", "rx";
1105                                 clocks = <&aes_clk>;
1106                                 clock-names = "aes_clk";
1107                                 status = "disabled";
1108                         };
1109
1110                         tdes@fc04c000 {
1111                                 compatible = "atmel,at91sam9g46-tdes";
1112                                 reg = <0xfc04c000 0x100>;
1113                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1114                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1115                                         AT91_XDMAC_DT_PERID(42)>,
1116                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1117                                         AT91_XDMAC_DT_PERID(43)>;
1118                                 dma-names = "tx", "rx";
1119                                 clocks = <&tdes_clk>;
1120                                 clock-names = "tdes_clk";
1121                                 status = "disabled";
1122                         };
1123
1124                         sha@fc050000 {
1125                                 compatible = "atmel,at91sam9g46-sha";
1126                                 reg = <0xfc050000 0x100>;
1127                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1128                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1129                                         AT91_XDMAC_DT_PERID(44)>;
1130                                 dma-names = "tx";
1131                                 clocks = <&sha_clk>;
1132                                 clock-names = "sha_clk";
1133                                 status = "disabled";
1134                         };
1135
1136                         rstc@fc068600 {
1137                                 compatible = "atmel,at91sam9g45-rstc";
1138                                 reg = <0xfc068600 0x10>;
1139                         };
1140
1141                         shdwc@fc068610 {
1142                                 compatible = "atmel,at91sam9x5-shdwc";
1143                                 reg = <0xfc068610 0x10>;
1144                         };
1145
1146                         pit: timer@fc068630 {
1147                                 compatible = "atmel,at91sam9260-pit";
1148                                 reg = <0xfc068630 0x10>;
1149                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1150                                 clocks = <&h32ck>;
1151                         };
1152
1153                         watchdog@fc068640 {
1154                                 compatible = "atmel,at91sam9260-wdt";
1155                                 reg = <0xfc068640 0x10>;
1156                                 status = "disabled";
1157                         };
1158
1159                         sckc@fc068650 {
1160                                 compatible = "atmel,at91sam9x5-sckc";
1161                                 reg = <0xfc068650 0x4>;
1162
1163                                 slow_rc_osc: slow_rc_osc {
1164                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1165                                         #clock-cells = <0>;
1166                                         clock-frequency = <32768>;
1167                                         clock-accuracy = <250000000>;
1168                                         atmel,startup-time-usec = <75>;
1169                                 };
1170
1171                                 slow_osc: slow_osc {
1172                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
1173                                         #clock-cells = <0>;
1174                                         clocks = <&slow_xtal>;
1175                                         atmel,startup-time-usec = <1200000>;
1176                                 };
1177
1178                                 clk32k: slowck {
1179                                         compatible = "atmel,at91sam9x5-clk-slow";
1180                                         #clock-cells = <0>;
1181                                         clocks = <&slow_rc_osc &slow_osc>;
1182                                 };
1183                         };
1184
1185                         rtc@fc0686b0 {
1186                                 compatible = "atmel,at91rm9200-rtc";
1187                                 reg = <0xfc0686b0 0x30>;
1188                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1189                         };
1190
1191                         dbgu: serial@fc069000 {
1192                                 compatible = "atmel,at91sam9260-usart";
1193                                 reg = <0xfc069000 0x200>;
1194                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1195                                 pinctrl-names = "default";
1196                                 pinctrl-0 = <&pinctrl_dbgu>;
1197                                 clocks = <&dbgu_clk>;
1198                                 clock-names = "usart";
1199                                 status = "disabled";
1200                         };
1201
1202
1203                         pinctrl@fc06a000 {
1204                                 #address-cells = <1>;
1205                                 #size-cells = <1>;
1206                                 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1207                                 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1208                                 /* WARNING: revisit as pin spec has changed */
1209                                 atmel,mux-mask = <
1210                                         /*   A          B          C  */
1211                                         0xffffffff 0x3ffcfe7c 0x1c010101        /* pioA */
1212                                         0x7fffffff 0xfffccc3a 0x3f00cc3a        /* pioB */
1213                                         0xffffffff 0x3ff83fff 0xff00ffff        /* pioC */
1214                                         0x00000000 0x00000000 0x00000000        /* pioD */
1215                                         0xffffffff 0x7fffffff 0x76fff1bf        /* pioE */
1216                                         >;
1217
1218                                 pioA: gpio@fc06a000 {
1219                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1220                                         reg = <0xfc06a000 0x100>;
1221                                         interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1222                                         #gpio-cells = <2>;
1223                                         gpio-controller;
1224                                         interrupt-controller;
1225                                         #interrupt-cells = <2>;
1226                                         clocks = <&pioA_clk>;
1227                                 };
1228
1229                                 pioB: gpio@fc06b000 {
1230                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1231                                         reg = <0xfc06b000 0x100>;
1232                                         interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1233                                         #gpio-cells = <2>;
1234                                         gpio-controller;
1235                                         interrupt-controller;
1236                                         #interrupt-cells = <2>;
1237                                         clocks = <&pioB_clk>;
1238                                 };
1239
1240                                 pioC: gpio@fc06c000 {
1241                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1242                                         reg = <0xfc06c000 0x100>;
1243                                         interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1244                                         #gpio-cells = <2>;
1245                                         gpio-controller;
1246                                         interrupt-controller;
1247                                         #interrupt-cells = <2>;
1248                                         clocks = <&pioC_clk>;
1249                                 };
1250
1251                                 pioD: gpio@fc068000 {
1252                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1253                                         reg = <0xfc068000 0x100>;
1254                                         interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1255                                         #gpio-cells = <2>;
1256                                         gpio-controller;
1257                                         interrupt-controller;
1258                                         #interrupt-cells = <2>;
1259                                         clocks = <&pioD_clk>;
1260                                         status = "disabled";
1261                                 };
1262
1263                                 pioE: gpio@fc06d000 {
1264                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1265                                         reg = <0xfc06d000 0x100>;
1266                                         interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1267                                         #gpio-cells = <2>;
1268                                         gpio-controller;
1269                                         interrupt-controller;
1270                                         #interrupt-cells = <2>;
1271                                         clocks = <&pioE_clk>;
1272                                 };
1273
1274                                 /* pinctrl pin settings */
1275                                 adc0 {
1276                                         pinctrl_adc0_adtrg: adc0_adtrg {
1277                                                 atmel,pins =
1278                                                         <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1279                                         };
1280                                         pinctrl_adc0_ad0: adc0_ad0 {
1281                                                 atmel,pins =
1282                                                         <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1283                                         };
1284                                         pinctrl_adc0_ad1: adc0_ad1 {
1285                                                 atmel,pins =
1286                                                         <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1287                                         };
1288                                         pinctrl_adc0_ad2: adc0_ad2 {
1289                                                 atmel,pins =
1290                                                         <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1291                                         };
1292                                         pinctrl_adc0_ad3: adc0_ad3 {
1293                                                 atmel,pins =
1294                                                         <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1295                                         };
1296                                         pinctrl_adc0_ad4: adc0_ad4 {
1297                                                 atmel,pins =
1298                                                         <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1299                                         };
1300                                 };
1301
1302                                 dbgu {
1303                                         pinctrl_dbgu: dbgu-0 {
1304                                                 atmel,pins =
1305                                                         <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,     /* conflicts with D14 and TDI */
1306                                                         <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;  /* conflicts with D15 and TDO */
1307                                         };
1308                                 };
1309
1310                                 i2c0 {
1311                                         pinctrl_i2c0: i2c0-0 {
1312                                                 atmel,pins =
1313                                                         <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1314                                                          AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1315                                         };
1316                                 };
1317
1318                                 i2c1 {
1319                                         pinctrl_i2c1: i2c1-0 {
1320                                                 atmel,pins =
1321                                                         <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* TWD1, conflicts with UART0 RX and DIBP */
1322                                                          AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1323                                         };
1324                                 };
1325
1326                                 i2c2 {
1327                                         pinctrl_i2c2: i2c2-0 {
1328                                                 atmel,pins =
1329                                                         <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* TWD2, conflicts with RD0 and PWML1 */
1330                                                          AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1331                                         };
1332                                 };
1333
1334                                 isi {
1335                                         pinctrl_isi_data_0_7: isi-0-data-0-7 {
1336                                                 atmel,pins =
1337                                                         <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D0 */
1338                                                          AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D1 */
1339                                                          AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D2 */
1340                                                          AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D3 */
1341                                                          AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D4 */
1342                                                          AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D5 */
1343                                                          AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D6 */
1344                                                          AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D7 */
1345                                                          AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_PCK, conflict with G0_RXCK */
1346                                                          AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_VSYNC */
1347                                                          AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1348                                         };
1349                                         pinctrl_isi_data_8_9: isi-0-data-8-9 {
1350                                                 atmel,pins =
1351                                                         <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1352                                                          AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1353                                         };
1354                                         pinctrl_isi_data_10_11: isi-0-data-10-11 {
1355                                                 atmel,pins =
1356                                                         <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1357                                                          AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1358                                         };
1359                                 };
1360
1361                                 lcd {
1362                                         pinctrl_lcd_base: lcd-base-0 {
1363                                                 atmel,pins =
1364                                                         <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
1365                                                          AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
1366                                                          AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
1367                                                          AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1368                                         };
1369                                         pinctrl_lcd_pwm: lcd-pwm-0 {
1370                                                 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
1371                                         };
1372                                         pinctrl_lcd_rgb444: lcd-rgb-0 {
1373                                                 atmel,pins =
1374                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1375                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1376                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1377                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1378                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1379                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1380                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1381                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1382                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1383                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1384                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1385                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1386                                         };
1387                                         pinctrl_lcd_rgb565: lcd-rgb-1 {
1388                                                 atmel,pins =
1389                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1390                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1391                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1392                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1393                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1394                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1395                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1396                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1397                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1398                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1399                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1400                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1401                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1402                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1403                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1404                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1405                                         };
1406                                         pinctrl_lcd_rgb666: lcd-rgb-2 {
1407                                                 atmel,pins =
1408                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1409                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1410                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1411                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1412                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1413                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1414                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1415                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1416                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1417                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1418                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1419                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1420                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1421                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1422                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1423                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1424                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
1425                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
1426                                         };
1427                                         pinctrl_lcd_rgb888: lcd-rgb-3 {
1428                                                 atmel,pins =
1429                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1430                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1431                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1432                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1433                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1434                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1435                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1436                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1437                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1438                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1439                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1440                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1441                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1442                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1443                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1444                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1445                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
1446                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
1447                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1448                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1449                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1450                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1451                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1452                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1453                                         };
1454                                 };
1455
1456                                 macb0 {
1457                                         pinctrl_macb0_rmii: macb0_rmii-0 {
1458                                                 atmel,pins =
1459                                                         <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX0 */
1460                                                          AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX1 */
1461                                                          AT91_PIOB  8 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX0 */
1462                                                          AT91_PIOB  9 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX1 */
1463                                                          AT91_PIOB  6 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXDV */
1464                                                          AT91_PIOB  7 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXER */
1465                                                          AT91_PIOB  2 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXEN */
1466                                                          AT91_PIOB  0 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXCK */
1467                                                          AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDC */
1468                                                          AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDIO */
1469                                                         >;
1470                                         };
1471                                 };
1472
1473                                 mmc0 {
1474                                         pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1475                                                 atmel,pins =
1476                                                         <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1477                                                          AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1478                                                          AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1479                                                         >;
1480                                         };
1481                                         pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1482                                                 atmel,pins =
1483                                                         <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1484                                                          AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1485                                                          AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1486                                                         >;
1487                                         };
1488                                 };
1489
1490                                 mmc1 {
1491                                         pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1492                                                 atmel,pins =
1493                                                         <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE           /* MCI1_CK */
1494                                                          AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_CDA */
1495                                                          AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA0 */
1496                                                         >;
1497                                         };
1498                                         pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1499                                                 atmel,pins =
1500                                                         <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA1 */
1501                                                          AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA2 */
1502                                                          AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA3 */
1503                                                         >;
1504                                         };
1505                                 };
1506
1507                                 nand0 {
1508                                         pinctrl_nand: nand-0 {
1509                                                 atmel,pins =
1510                                                         <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC13 periph A Read Enable */
1511                                                          AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC14 periph A Write Enable */
1512
1513                                                          AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC17 ALE */
1514                                                          AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC18 CLE */
1515
1516                                                          AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC15 NCS3/Chip Enable */
1517                                                          AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC16 NANDRDY */
1518                                                          AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC5 Data bit 0 */
1519                                                          AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 Data bit 1 */
1520                                                          AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 Data bit 2 */
1521                                                          AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 Data bit 3 */
1522                                                          AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC9 Data bit 4 */
1523                                                          AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC10 Data bit 5 */
1524                                                          AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC11 periph A Data bit 6 */
1525                                                          AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1526                                         };
1527                                 };
1528
1529                                 spi0 {
1530                                         pinctrl_spi0: spi0-0 {
1531                                                 atmel,pins =
1532                                                         <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MISO */
1533                                                          AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MOSI */
1534                                                          AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_SPCK */
1535                                                         >;
1536                                         };
1537                                 };
1538
1539                                 ssc0 {
1540                                         pinctrl_ssc0_tx: ssc0_tx {
1541                                                 atmel,pins =
1542                                                         <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK0 */
1543                                                          AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF0 */
1544                                                          AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1545                                         };
1546
1547                                         pinctrl_ssc0_rx: ssc0_rx {
1548                                                 atmel,pins =
1549                                                         <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK0 */
1550                                                          AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF0 */
1551                                                          AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1552                                         };
1553                                 };
1554
1555                                 ssc1 {
1556                                         pinctrl_ssc1_tx: ssc1_tx {
1557                                                 atmel,pins =
1558                                                         <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK1 */
1559                                                          AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF1 */
1560                                                          AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1561                                         };
1562
1563                                         pinctrl_ssc1_rx: ssc1_rx {
1564                                                 atmel,pins =
1565                                                         <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK1 */
1566                                                          AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF1 */
1567                                                          AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1568                                         };
1569                                 };
1570
1571                                 usart2 {
1572                                         pinctrl_usart2: usart2-0 {
1573                                                 atmel,pins =
1574                                                         <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE            /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1575                                                          AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP         /* TXD - conflicts with G0_COL, PCK2 */
1576                                                         >;
1577                                         };
1578                                         pinctrl_usart2_rts: usart2_rts-0 {
1579                                                 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with G0_RX3, PWMH1 */
1580                                         };
1581                                         pinctrl_usart2_cts: usart2_cts-0 {
1582                                                 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;     /* conflicts with G0_TXER, ISI_VSYNC */
1583                                         };
1584                                 };
1585
1586                                 usart3 {
1587                                         pinctrl_usart3: usart3-0 {
1588                                                 atmel,pins =
1589                                                         <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1590                                                          AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1591                                                         >;
1592                                         };
1593                                 };
1594
1595                                 usart4 {
1596                                         pinctrl_usart4: usart4-0 {
1597                                                 atmel,pins =
1598                                                         <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1599                                                          AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1600                                                         >;
1601                                         };
1602                                         pinctrl_usart4_rts: usart4_rts-0 {
1603                                                 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with NWAIT, A19 */
1604                                         };
1605                                         pinctrl_usart4_cts: usart4_cts-0 {
1606                                                 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>;     /* conflicts with A0/NBS0, MCI0_CDB */
1607                                         };
1608                                 };
1609                         };
1610
1611                         aic: interrupt-controller@fc06e000 {
1612                                 #interrupt-cells = <3>;
1613                                 compatible = "atmel,sama5d4-aic";
1614                                 interrupt-controller;
1615                                 reg = <0xfc06e000 0x200>;
1616                                 atmel,external-irqs = <56>;
1617                         };
1618                 };
1619         };
1620 };