1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/atmel-flexcom.h>
20 model = "Microchip SAM9X60 SoC";
21 compatible = "microchip,sam9x60";
22 interrupt-parent = <&aic>;
39 compatible = "arm,arm926ej-s";
46 device_type = "memory";
47 reg = <0x20000000 0x10000000>;
51 slow_xtal: slow_xtal {
52 compatible = "fixed-clock";
56 main_xtal: main_xtal {
57 compatible = "fixed-clock";
63 compatible = "mmio-sram";
64 reg = <0x00300000 0x100000>;
67 ranges = <0 0x00300000 0x100000>;
71 compatible = "simple-bus";
79 compatible = "microchip,sam9x60-udc";
80 reg = <0x00500000 0x100000
82 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
83 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
84 clock-names = "pclk", "hclk";
85 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
86 assigned-clock-rates = <480000000>;
91 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
92 reg = <0x00600000 0x100000>;
93 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
94 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
95 clock-names = "ohci_clk", "hclk", "uhpck";
100 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
101 reg = <0x00700000 0x100000>;
102 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
103 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
104 clock-names = "usb_clk", "ehci_clk";
105 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
106 assigned-clock-rates = <480000000>;
111 compatible = "microchip,sam9x60-ebi";
112 #address-cells = <2>;
115 microchip,sfr = <&sfr>;
116 reg = <0x10000000 0x60000000>;
117 ranges = <0x0 0x0 0x10000000 0x10000000
118 0x1 0x0 0x20000000 0x10000000
119 0x2 0x0 0x30000000 0x10000000
120 0x3 0x0 0x40000000 0x10000000
121 0x4 0x0 0x50000000 0x10000000
122 0x5 0x0 0x60000000 0x10000000>;
123 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
126 nand_controller: nand-controller {
127 compatible = "microchip,sam9x60-nand-controller";
128 ecc-engine = <&pmecc>;
129 #address-cells = <2>;
136 sdmmc0: sdio-host@80000000 {
137 compatible = "microchip,sam9x60-sdhci";
138 reg = <0x80000000 0x300>;
139 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
141 clock-names = "hclock", "multclk";
142 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
143 assigned-clock-rates = <100000000>;
147 sdmmc1: sdio-host@90000000 {
148 compatible = "microchip,sam9x60-sdhci";
149 reg = <0x90000000 0x300>;
150 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
151 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
152 clock-names = "hclock", "multclk";
153 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
154 assigned-clock-rates = <100000000>;
159 compatible = "simple-bus";
160 #address-cells = <1>;
164 flx4: flexcom@f0000000 {
165 compatible = "atmel,sama5d2-flexcom";
166 reg = <0xf0000000 0x200>;
167 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
168 #address-cells = <1>;
170 ranges = <0x0 0xf0000000 0x800>;
174 flx5: flexcom@f0004000 {
175 compatible = "atmel,sama5d2-flexcom";
176 reg = <0xf0004000 0x200>;
177 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
178 #address-cells = <1>;
180 ranges = <0x0 0xf0004000 0x800>;
184 dma0: dma-controller@f0008000 {
185 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
186 reg = <0xf0008000 0x1000>;
187 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
189 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
190 clock-names = "dma_clk";
194 compatible = "atmel,at91sam9g45-ssc";
195 reg = <0xf0010000 0x4000>;
196 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
198 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
199 AT91_XDMAC_DT_PERID(38))>,
201 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
202 AT91_XDMAC_DT_PERID(39))>;
203 dma-names = "tx", "rx";
204 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
205 clock-names = "pclk";
210 compatible = "microchip,sam9x60-qspi";
211 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
212 reg-names = "qspi_base", "qspi_mmap";
213 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
215 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
216 AT91_XDMAC_DT_PERID(26))>,
218 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
219 AT91_XDMAC_DT_PERID(27))>;
220 dma-names = "tx", "rx";
221 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
222 clock-names = "pclk", "qspick";
224 #address-cells = <1>;
230 compatible = "microchip,sam9x60-i2smcc";
231 reg = <0xf001c000 0x100>;
232 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
234 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
235 AT91_XDMAC_DT_PERID(36))>,
237 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
238 AT91_XDMAC_DT_PERID(37))>;
239 dma-names = "tx", "rx";
240 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
241 clock-names = "pclk", "gclk";
245 flx11: flexcom@f0020000 {
246 compatible = "atmel,sama5d2-flexcom";
247 reg = <0xf0020000 0x200>;
248 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
249 #address-cells = <1>;
251 ranges = <0x0 0xf0020000 0x800>;
255 flx12: flexcom@f0024000 {
256 compatible = "atmel,sama5d2-flexcom";
257 reg = <0xf0024000 0x200>;
258 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
259 #address-cells = <1>;
261 ranges = <0x0 0xf0024000 0x800>;
265 pit64b: timer@f0028000 {
266 compatible = "microchip,sam9x60-pit64b";
267 reg = <0xf0028000 0x100>;
268 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
269 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
270 clock-names = "pclk", "gclk";
273 sha: crypto@f002c000 {
274 compatible = "atmel,at91sam9g46-sha";
275 reg = <0xf002c000 0x100>;
276 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
278 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
279 AT91_XDMAC_DT_PERID(34))>;
281 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
282 clock-names = "sha_clk";
285 trng: trng@f0030000 {
286 compatible = "microchip,sam9x60-trng";
287 reg = <0xf0030000 0x100>;
288 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
289 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
292 aes: crypto@f0034000 {
293 compatible = "atmel,at91sam9g46-aes";
294 reg = <0xf0034000 0x100>;
295 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
297 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
298 AT91_XDMAC_DT_PERID(32))>,
300 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
301 AT91_XDMAC_DT_PERID(33))>;
302 dma-names = "tx", "rx";
303 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
304 clock-names = "aes_clk";
307 tdes: crypto@f0038000 {
308 compatible = "atmel,at91sam9g46-tdes";
309 reg = <0xf0038000 0x100>;
310 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
312 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
313 AT91_XDMAC_DT_PERID(31))>,
315 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
316 AT91_XDMAC_DT_PERID(30))>;
317 dma-names = "tx", "rx";
318 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
319 clock-names = "tdes_clk";
322 classd: classd@f003c000 {
323 compatible = "atmel,sama5d2-classd";
324 reg = <0xf003c000 0x100>;
325 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
327 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
328 AT91_XDMAC_DT_PERID(35))>;
330 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
331 clock-names = "pclk", "gclk";
336 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
337 reg = <0xf8000000 0x300>;
338 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
339 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
340 clock-names = "can_clk";
345 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
346 reg = <0xf8004000 0x300>;
347 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
348 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
349 clock-names = "can_clk";
353 tcb0: timer@f8008000 {
354 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
355 #address-cells = <1>;
357 reg = <0xf8008000 0x100>;
358 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
359 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
360 clock-names = "t0_clk", "slow_clk";
363 tcb1: timer@f800c000 {
364 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
365 #address-cells = <1>;
367 reg = <0xf800c000 0x100>;
368 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
369 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
370 clock-names = "t0_clk", "slow_clk";
373 flx6: flexcom@f8010000 {
374 compatible = "atmel,sama5d2-flexcom";
375 reg = <0xf8010000 0x200>;
376 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
377 #address-cells = <1>;
379 ranges = <0x0 0xf8010000 0x800>;
383 flx7: flexcom@f8014000 {
384 compatible = "atmel,sama5d2-flexcom";
385 reg = <0xf8014000 0x200>;
386 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
387 #address-cells = <1>;
389 ranges = <0x0 0xf8014000 0x800>;
393 flx8: flexcom@f8018000 {
394 compatible = "atmel,sama5d2-flexcom";
395 reg = <0xf8018000 0x200>;
396 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
397 #address-cells = <1>;
399 ranges = <0x0 0xf8018000 0x800>;
403 flx0: flexcom@f801c000 {
404 compatible = "atmel,sama5d2-flexcom";
405 reg = <0xf801c000 0x200>;
406 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
407 #address-cells = <1>;
409 ranges = <0x0 0xf801c000 0x800>;
413 flx1: flexcom@f8020000 {
414 compatible = "atmel,sama5d2-flexcom";
415 reg = <0xf8020000 0x200>;
416 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
417 #address-cells = <1>;
419 ranges = <0x0 0xf8020000 0x800>;
423 flx2: flexcom@f8024000 {
424 compatible = "atmel,sama5d2-flexcom";
425 reg = <0xf8024000 0x200>;
426 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
427 #address-cells = <1>;
429 ranges = <0x0 0xf8024000 0x800>;
433 flx3: flexcom@f8028000 {
434 compatible = "atmel,sama5d2-flexcom";
435 reg = <0xf8028000 0x200>;
436 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
437 #address-cells = <1>;
439 ranges = <0x0 0xf8028000 0x800>;
443 macb0: ethernet@f802c000 {
444 compatible = "cdns,sam9x60-macb", "cdns,macb";
445 reg = <0xf802c000 0x1000>;
446 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
447 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
448 clock-names = "hclk", "pclk";
452 macb1: ethernet@f8030000 {
453 compatible = "cdns,sam9x60-macb", "cdns,macb";
454 reg = <0xf8030000 0x1000>;
455 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
456 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
457 clock-names = "hclk", "pclk";
462 compatible = "microchip,sam9x60-pwm";
463 reg = <0xf8034000 0x300>;
464 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
465 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
470 hlcdc: hlcdc@f8038000 {
471 compatible = "microchip,sam9x60-hlcdc";
472 reg = <0xf8038000 0x4000>;
473 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
474 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
475 clock-names = "periph_clk","sys_clk", "slow_clk";
476 assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
477 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
480 hlcdc-display-controller {
481 compatible = "atmel,hlcdc-display-controller";
482 #address-cells = <1>;
486 #address-cells = <1>;
492 hlcdc_pwm: hlcdc-pwm {
493 compatible = "atmel,hlcdc-pwm";
498 flx9: flexcom@f8040000 {
499 compatible = "atmel,sama5d2-flexcom";
500 reg = <0xf8040000 0x200>;
501 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
502 #address-cells = <1>;
504 ranges = <0x0 0xf8040000 0x800>;
508 flx10: flexcom@f8044000 {
509 compatible = "atmel,sama5d2-flexcom";
510 reg = <0xf8044000 0x200>;
511 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
512 #address-cells = <1>;
514 ranges = <0x0 0xf8044000 0x800>;
519 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
520 reg = <0xf8048000 0x100>;
521 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
522 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
523 clock-names = "isi_clk";
526 #address-cells = <1>;
532 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
533 reg = <0xf804c000 0x100>;
534 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
535 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
536 clock-names = "adc_clk";
537 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
539 atmel,min-sample-rate-hz = <200000>;
540 atmel,max-sample-rate-hz = <20000000>;
541 atmel,startup-time-ms = <4>;
542 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
543 #io-channel-cells = <1>;
548 compatible = "microchip,sam9x60-sfr", "syscon";
549 reg = <0xf8050000 0x100>;
552 matrix: matrix@ffffde00 {
553 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
554 reg = <0xffffde00 0x200>;
557 pmecc: ecc-engine@ffffe000 {
558 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
559 reg = <0xffffe000 0x300>,
563 mpddrc: mpddrc@ffffe800 {
564 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
565 reg = <0xffffe800 0x200>;
566 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
567 clock-names = "ddrck", "mpddr";
571 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
572 reg = <0xffffea00 0x100>;
575 aic: interrupt-controller@fffff100 {
576 compatible = "microchip,sam9x60-aic";
577 #interrupt-cells = <3>;
578 interrupt-controller;
579 reg = <0xfffff100 0x100>;
580 atmel,external-irqs = <31>;
583 dbgu: serial@fffff200 {
584 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
585 reg = <0xfffff200 0x200>;
586 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
588 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
589 AT91_XDMAC_DT_PERID(28))>,
591 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
592 AT91_XDMAC_DT_PERID(29))>;
593 dma-names = "tx", "rx";
594 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
595 clock-names = "usart";
599 pinctrl: pinctrl@fffff400 {
600 #address-cells = <1>;
602 compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
603 ranges = <0xfffff400 0xfffff400 0x800>;
605 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
608 0xffffffff 0xffe03fff 0xef00019d /* pioA */
609 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
610 0xffffffff 0xffffffff 0xf83fffff /* pioC */
611 0x003fffff 0x003f8000 0x00000000 /* pioD */
614 pioA: gpio@fffff400 {
615 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
616 reg = <0xfffff400 0x200>;
617 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
622 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
625 pioB: gpio@fffff600 {
626 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
627 reg = <0xfffff600 0x200>;
628 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
632 interrupt-controller;
633 #interrupt-cells = <2>;
634 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
637 pioC: gpio@fffff800 {
638 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
639 reg = <0xfffff800 0x200>;
640 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
648 pioD: gpio@fffffa00 {
649 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
650 reg = <0xfffffa00 0x200>;
651 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
655 interrupt-controller;
656 #interrupt-cells = <2>;
657 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
662 compatible = "microchip,sam9x60-pmc", "syscon";
663 reg = <0xfffffc00 0x200>;
664 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
666 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
667 clock-names = "td_slck", "md_slck", "main_xtal";
670 reset_controller: reset-controller@fffffe00 {
671 compatible = "microchip,sam9x60-rstc";
672 reg = <0xfffffe00 0x10>;
673 clocks = <&clk32k 0>;
676 shutdown_controller: shdwc@fffffe10 {
677 compatible = "microchip,sam9x60-shdwc";
678 reg = <0xfffffe10 0x10>;
679 clocks = <&clk32k 0>;
680 #address-cells = <1>;
682 atmel,wakeup-rtc-timer;
683 atmel,wakeup-rtt-timer;
688 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
689 reg = <0xfffffe20 0x20>;
690 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
691 clocks = <&clk32k 0>;
694 pit: timer@fffffe40 {
695 compatible = "atmel,at91sam9260-pit";
696 reg = <0xfffffe40 0x10>;
697 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
698 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
701 clk32k: sckc@fffffe50 {
702 compatible = "microchip,sam9x60-sckc";
703 reg = <0xfffffe50 0x4>;
704 clocks = <&slow_xtal>;
708 gpbr: syscon@fffffe60 {
709 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
710 reg = <0xfffffe60 0x10>;
714 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
715 reg = <0xfffffea8 0x100>;
716 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
717 clocks = <&clk32k 0>;
720 watchdog: watchdog@ffffff80 {
721 compatible = "microchip,sam9x60-wdt";
722 reg = <0xffffff80 0x24>;
723 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
724 clocks = <&clk32k 0>;