2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/rv1108-cru.h>
45 #include <dt-bindings/pinctrl/rockchip.h>
46 #include <dt-bindings/thermal/thermal.h>
51 compatible = "rockchip,rv1108";
53 interrupt-parent = <&gic>;
71 compatible = "arm,cortex-a7";
73 clocks = <&cru ARMCLK>;
74 #cooling-cells = <2>; /* min followed by max */
75 dynamic-power-coefficient = <75>;
76 operating-points-v2 = <&cpu_opp_table>;
80 cpu_opp_table: opp_table {
81 compatible = "operating-points-v2";
84 opp-hz = /bits/ 64 <408000000>;
85 opp-microvolt = <975000>;
86 clock-latency-ns = <40000>;
89 opp-hz = /bits/ 64 <600000000>;
90 opp-microvolt = <975000>;
91 clock-latency-ns = <40000>;
94 opp-hz = /bits/ 64 <816000000>;
95 opp-microvolt = <1025000>;
96 clock-latency-ns = <40000>;
99 opp-hz = /bits/ 64 <1008000000>;
100 opp-microvolt = <1150000>;
101 clock-latency-ns = <40000>;
106 compatible = "arm,cortex-a7-pmu";
107 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
111 compatible = "arm,armv7-timer";
112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
114 clock-frequency = <24000000>;
118 compatible = "fixed-clock";
119 clock-frequency = <24000000>;
120 clock-output-names = "xin24m";
125 compatible = "simple-bus";
126 #address-cells = <1>;
130 pdma: pdma@102a0000 {
131 compatible = "arm,pl330", "arm,primecell";
132 reg = <0x102a0000 0x4000>;
133 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
135 arm,pl330-broken-no-flushp;
136 clocks = <&cru ACLK_DMAC>;
137 clock-names = "apb_pclk";
141 bus_intmem@10080000 {
142 compatible = "mmio-sram";
143 reg = <0x10080000 0x2000>;
144 #address-cells = <1>;
146 ranges = <0 0x10080000 0x2000>;
149 uart2: serial@10210000 {
150 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
151 reg = <0x10210000 0x100>;
152 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
155 clock-frequency = <24000000>;
156 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
157 clock-names = "baudclk", "apb_pclk";
158 pinctrl-names = "default";
159 pinctrl-0 = <&uart2m0_xfer>;
163 uart1: serial@10220000 {
164 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
165 reg = <0x10220000 0x100>;
166 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
169 clock-frequency = <24000000>;
170 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
171 clock-names = "baudclk", "apb_pclk";
172 pinctrl-names = "default";
173 pinctrl-0 = <&uart1_xfer>;
177 uart0: serial@10230000 {
178 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
179 reg = <0x10230000 0x100>;
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
183 clock-frequency = <24000000>;
184 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
185 clock-names = "baudclk", "apb_pclk";
186 pinctrl-names = "default";
187 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
192 compatible = "rockchip,rv1108-i2c";
193 reg = <0x10240000 0x1000>;
194 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
195 #address-cells = <1>;
197 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
198 clock-names = "i2c", "pclk";
199 pinctrl-names = "default";
200 pinctrl-0 = <&i2c1_xfer>;
201 rockchip,grf = <&grf>;
206 compatible = "rockchip,rv1108-i2c";
207 reg = <0x10250000 0x1000>;
208 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
211 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
212 clock-names = "i2c", "pclk";
213 pinctrl-names = "default";
214 pinctrl-0 = <&i2c2m1_xfer>;
215 rockchip,grf = <&grf>;
220 compatible = "rockchip,rv1108-i2c";
221 reg = <0x10260000 0x1000>;
222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
223 #address-cells = <1>;
225 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
226 clock-names = "i2c", "pclk";
227 pinctrl-names = "default";
228 pinctrl-0 = <&i2c3_xfer>;
229 rockchip,grf = <&grf>;
234 compatible = "rockchip,rv1108-spi";
235 reg = <0x10270000 0x1000>;
236 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
238 clock-names = "spiclk", "apb_pclk";
239 dmas = <&pdma 8>, <&pdma 9>;
241 #address-cells = <1>;
247 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
248 reg = <0x10280000 0x10>;
249 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
251 clock-names = "pwm", "pclk";
252 pinctrl-names = "default";
253 pinctrl-0 = <&pwm4_pin>;
259 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
260 reg = <0x10280010 0x10>;
261 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
263 clock-names = "pwm", "pclk";
264 pinctrl-names = "default";
265 pinctrl-0 = <&pwm5_pin>;
271 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
272 reg = <0x10280020 0x10>;
273 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
275 clock-names = "pwm", "pclk";
276 pinctrl-names = "default";
277 pinctrl-0 = <&pwm6_pin>;
283 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
284 reg = <0x10280030 0x10>;
285 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
287 clock-names = "pwm", "pclk";
288 pinctrl-names = "default";
289 pinctrl-0 = <&pwm7_pin>;
294 grf: syscon@10300000 {
295 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
296 reg = <0x10300000 0x1000>;
297 #address-cells = <1>;
300 u2phy: usb2-phy@100 {
301 compatible = "rockchip,rv1108-usb2phy";
303 clocks = <&cru SCLK_USBPHY>;
304 clock-names = "phyclk";
306 clock-output-names = "usbphy";
307 rockchip,usbgrf = <&usbgrf>;
310 u2phy_otg: otg-port {
311 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "otg-mux";
317 u2phy_host: host-port {
318 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
319 interrupt-names = "linestate";
326 watchdog: wdt@10360000 {
327 compatible = "snps,dw-wdt";
328 reg = <0x10360000 0x100>;
329 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cru PCLK_WDT>;
331 clock-names = "pclk_wdt";
336 soc_thermal: soc-thermal {
337 polling-delay-passive = <20>;
338 polling-delay = <1000>;
339 sustainable-power = <50>;
340 thermal-sensors = <&tsadc 0>;
343 threshold: trip-point0 {
344 temperature = <70000>;
348 target: trip-point1 {
349 temperature = <85000>;
354 temperature = <95000>;
363 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
364 contribution = <4096>;
370 tsadc: tsadc@10370000 {
371 compatible = "rockchip,rv1108-tsadc";
372 reg = <0x10370000 0x100>;
373 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
374 assigned-clocks = <&cru SCLK_TSADC>;
375 assigned-clock-rates = <750000>;
376 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
377 clock-names = "tsadc", "apb_pclk";
378 pinctrl-names = "init", "default", "sleep";
379 pinctrl-0 = <&otp_gpio>;
380 pinctrl-1 = <&otp_out>;
381 pinctrl-2 = <&otp_gpio>;
382 resets = <&cru SRST_TSADC>;
383 reset-names = "tsadc-apb";
384 rockchip,hw-tshut-temp = <120000>;
385 #thermal-sensor-cells = <1>;
390 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
391 reg = <0x1038c000 0x100>;
392 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
393 #io-channel-cells = <1>;
394 clock-frequency = <1000000>;
395 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
396 clock-names = "saradc", "apb_pclk";
401 compatible = "rockchip,rv1108-i2c";
402 reg = <0x20000000 0x1000>;
403 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
407 clock-names = "i2c", "pclk";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c0_xfer>;
410 rockchip,grf = <&grf>;
415 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
416 reg = <0x20040000 0x10>;
417 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
419 clock-names = "pwm", "pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&pwm0_pin>;
427 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
428 reg = <0x20040010 0x10>;
429 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
431 clock-names = "pwm", "pclk";
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm1_pin>;
439 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
440 reg = <0x20040020 0x10>;
441 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
443 clock-names = "pwm", "pclk";
444 pinctrl-names = "default";
445 pinctrl-0 = <&pwm2_pin>;
451 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
452 reg = <0x20040030 0x10>;
453 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
455 clock-names = "pwm", "pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&pwm3_pin>;
462 pmugrf: syscon@20060000 {
463 compatible = "rockchip,rv1108-pmugrf", "syscon";
464 reg = <0x20060000 0x1000>;
467 usbgrf: syscon@202a0000 {
468 compatible = "rockchip,rv1108-usbgrf", "syscon";
469 reg = <0x202a0000 0x1000>;
472 cru: clock-controller@20200000 {
473 compatible = "rockchip,rv1108-cru";
474 reg = <0x20200000 0x1000>;
475 rockchip,grf = <&grf>;
480 emmc: dwmmc@30110000 {
481 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
482 reg = <0x30110000 0x4000>;
483 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
485 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
486 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
487 fifo-depth = <0x100>;
488 max-frequency = <150000000>;
492 sdio: dwmmc@30120000 {
493 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
494 reg = <0x30120000 0x4000>;
495 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
497 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
498 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
499 fifo-depth = <0x100>;
500 max-frequency = <150000000>;
504 sdmmc: dwmmc@30130000 {
505 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
506 reg = <0x30130000 0x4000>;
507 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
509 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
510 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
511 fifo-depth = <0x100>;
512 max-frequency = <100000000>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
518 usb_host_ehci: usb@30140000 {
519 compatible = "generic-ehci";
520 reg = <0x30140000 0x20000>;
521 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru HCLK_HOST0>, <&u2phy>;
523 clock-names = "usbhost", "utmi";
524 phys = <&u2phy_host>;
529 usb_host_ohci: usb@30160000 {
530 compatible = "generic-ohci";
531 reg = <0x30160000 0x20000>;
532 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru HCLK_HOST0>, <&u2phy>;
534 clock-names = "usbhost", "utmi";
535 phys = <&u2phy_host>;
540 usb_otg: usb@30180000 {
541 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
543 reg = <0x30180000 0x40000>;
544 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cru HCLK_OTG>;
548 g-np-tx-fifo-size = <16>;
549 g-rx-fifo-size = <280>;
550 g-tx-fifo-size = <256 128 128 64 32 16>;
553 phy-names = "usb2-phy";
557 gic: interrupt-controller@32010000 {
558 compatible = "arm,gic-400";
559 interrupt-controller;
560 #interrupt-cells = <3>;
561 #address-cells = <0>;
563 reg = <0x32011000 0x1000>,
567 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
571 compatible = "rockchip,rv1108-pinctrl";
572 rockchip,grf = <&grf>;
573 rockchip,pmu = <&pmugrf>;
574 #address-cells = <1>;
578 gpio0: gpio0@20030000 {
579 compatible = "rockchip,gpio-bank";
580 reg = <0x20030000 0x100>;
581 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
591 gpio1: gpio1@10310000 {
592 compatible = "rockchip,gpio-bank";
593 reg = <0x10310000 0x100>;
594 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
600 interrupt-controller;
601 #interrupt-cells = <2>;
604 gpio2: gpio2@10320000 {
605 compatible = "rockchip,gpio-bank";
606 reg = <0x10320000 0x100>;
607 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
617 gpio3: gpio3@10330000 {
618 compatible = "rockchip,gpio-bank";
619 reg = <0x10330000 0x100>;
620 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
630 pcfg_pull_up: pcfg-pull-up {
634 pcfg_pull_down: pcfg-pull-down {
638 pcfg_pull_none: pcfg-pull-none {
642 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
643 drive-strength = <8>;
646 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
647 drive-strength = <12>;
650 pcfg_pull_none_smt: pcfg-pull-none-smt {
652 input-schmitt-enable;
655 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
657 drive-strength = <8>;
660 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
661 drive-strength = <4>;
664 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
666 drive-strength = <4>;
669 pcfg_output_high: pcfg-output-high {
673 pcfg_output_low: pcfg-output-low {
677 pcfg_input_high: pcfg-input-high {
683 i2c0_xfer: i2c0-xfer {
684 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
685 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
690 i2c1_xfer: i2c1-xfer {
691 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
692 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
697 i2c2m1_xfer: i2c2m1-xfer {
698 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
699 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
702 i2c2m1_gpio: i2c2m1-gpio {
703 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
704 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
709 i2c2m05v_xfer: i2c2m05v-xfer {
710 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
711 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
714 i2c2m05v_gpio: i2c2m05v-gpio {
715 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
716 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
721 i2c3_xfer: i2c3-xfer {
722 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
723 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
729 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
735 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
741 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
747 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
753 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
759 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
765 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
771 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
776 sdmmc_clk: sdmmc-clk {
777 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
780 sdmmc_cmd: sdmmc-cmd {
781 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
785 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
788 sdmmc_bus1: sdmmc-bus1 {
789 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
792 sdmmc_bus4: sdmmc-bus4 {
793 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
794 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
795 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
796 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
802 rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
806 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
811 uart0_xfer: uart0-xfer {
812 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
813 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
816 uart0_cts: uart0-cts {
817 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
820 uart0_rts: uart0-rts {
821 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
824 uart0_rts_gpio: uart0-rts-gpio {
825 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
830 uart1_xfer: uart1-xfer {
831 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
832 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
835 uart1_cts: uart1-cts {
836 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
839 uart1_rts: uart1-rts {
840 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
845 uart2m0_xfer: uart2m0-xfer {
846 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
847 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
852 uart2m1_xfer: uart2m1-xfer {
853 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
854 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
859 uart2_5v_cts: uart2_5v-cts {
860 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
863 uart2_5v_rts: uart2_5v-rts {
864 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;