arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron (and derivatives) fragment for sdmmc cards
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 / {
   9         aliases {
  10                 mmc1 = &sdmmc;
  11         };
  12 };
  13
  14 &io_domains {
  15         sdcard-supply = <&vccio_sd>;
  16 };
  17
  18 &pinctrl {
  19         sdmmc {
  20                 /*
  21                  * We run sdmmc at max speed; bump up drive strength.
  22                  * We also have external pulls, so disable the internal ones.
  23                  */
  24                 sdmmc_bus4: sdmmc-bus4 {
  25                         rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
  26                                         <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
  27                                         <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
  28                                         <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
  29                 };
  30
  31                 sdmmc_clk: sdmmc-clk {
  32                         rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
  33                 };
  34
  35                 sdmmc_cmd: sdmmc-cmd {
  36                         rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
  37                 };
  38
  39                 /*
  40                  * Builtin CD line is hooked to ground to prevent JTAG at boot
  41                  * (and also to get the voltage rail correct).
  42                  * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
  43                  * think there's a card inserted
  44                  */
  45                 sdmmc_cd_disabled: sdmmc-cd-disabled {
  46                         rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  47                 };
  48
  49                 /* This is where we actually hook up CD */
  50                 sdmmc_cd_pin: sdmmc-cd-pin {
  51                         rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
  52                 };
  53         };
  54 };
  55
  56 &rk808 {
  57         vcc9-supply = <&vcc_5v>;
  58
  59         regulators {
  60                 vccio_sd: LDO_REG4 {
  61                         regulator-name = "vccio_sd";
  62                         regulator-min-microvolt = <1800000>;
  63                         regulator-max-microvolt = <3300000>;
  64                         regulator-state-mem {
  65                                 regulator-off-in-suspend;
  66                         };
  67                 };
  68
  69                 vcc33_sd: LDO_REG5 {
  70                         regulator-name = "vcc33_sd";
  71                         regulator-min-microvolt = <3300000>;
  72                         regulator-max-microvolt = <3300000>;
  73                         regulator-state-mem {
  74                                 regulator-off-in-suspend;
  75                         };
  76                 };
  77         };
  78 };
  79
  80 &sdmmc {
  81         status = "okay";
  82
  83         bus-width = <4>;
  84         cap-mmc-highspeed;
  85         cap-sd-highspeed;
  86         card-detect-delay = <200>;
  87         cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
  88         rockchip,default-sample-phase = <90>;
  89         sd-uhs-sdr12;
  90         sd-uhs-sdr25;
  91         sd-uhs-sdr50;
  92         sd-uhs-sdr104;
  93         vmmc-supply = <&vcc33_sd>;
  94         vqmmc-supply = <&vccio_sd>;
  95 };