1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Simon Horman
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
15 compatible = "renesas,r8a7779";
16 interrupt-parent = <&gic>;
26 compatible = "arm,cortex-a9";
28 clock-frequency = <1000000000>;
29 clocks = <&cpg_clocks R8A7779_CLK_Z>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <1000000000>;
36 clocks = <&cpg_clocks R8A7779_CLK_Z>;
37 power-domains = <&sysc R8A7779_PD_ARM1>;
41 compatible = "arm,cortex-a9";
43 clock-frequency = <1000000000>;
44 clocks = <&cpg_clocks R8A7779_CLK_Z>;
45 power-domains = <&sysc R8A7779_PD_ARM2>;
49 compatible = "arm,cortex-a9";
51 clock-frequency = <1000000000>;
52 clocks = <&cpg_clocks R8A7779_CLK_Z>;
53 power-domains = <&sysc R8A7779_PD_ARM3>;
63 gic: interrupt-controller@f0001000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
67 reg = <0xf0001000 0x1000>,
72 compatible = "arm,cortex-a9-global-timer";
73 reg = <0xf0000200 0x100>;
74 interrupts = <GIC_PPI 11
75 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
76 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
80 compatible = "arm,cortex-a9-twd-timer";
81 reg = <0xf0000600 0x20>;
82 interrupts = <GIC_PPI 13
83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
84 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
87 gpio0: gpio@ffc40000 {
88 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
89 reg = <0xffc40000 0x2c>;
90 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
93 gpio-ranges = <&pfc 0 0 32>;
94 #interrupt-cells = <2>;
98 gpio1: gpio@ffc41000 {
99 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
100 reg = <0xffc41000 0x2c>;
101 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
104 gpio-ranges = <&pfc 0 32 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
109 gpio2: gpio@ffc42000 {
110 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
111 reg = <0xffc42000 0x2c>;
112 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
115 gpio-ranges = <&pfc 0 64 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
120 gpio3: gpio@ffc43000 {
121 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
122 reg = <0xffc43000 0x2c>;
123 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
131 gpio4: gpio@ffc44000 {
132 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
133 reg = <0xffc44000 0x2c>;
134 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
137 gpio-ranges = <&pfc 0 128 32>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
142 gpio5: gpio@ffc45000 {
143 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
144 reg = <0xffc45000 0x2c>;
145 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
148 gpio-ranges = <&pfc 0 160 32>;
149 #interrupt-cells = <2>;
150 interrupt-controller;
153 gpio6: gpio@ffc46000 {
154 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
155 reg = <0xffc46000 0x2c>;
156 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
159 gpio-ranges = <&pfc 0 192 9>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
164 irqpin0: interrupt-controller@fe78001c {
165 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
166 #interrupt-cells = <2>;
168 interrupt-controller;
169 reg = <0xfe78001c 4>,
175 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
179 sense-bitfield-width = <2>;
183 #address-cells = <1>;
185 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
186 reg = <0xffc70000 0x1000>;
187 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
189 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
194 #address-cells = <1>;
196 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
197 reg = <0xffc71000 0x1000>;
198 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
200 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
201 i2c-scl-internal-delay-ns = <5>;
206 #address-cells = <1>;
208 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
209 reg = <0xffc72000 0x1000>;
210 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
212 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
213 i2c-scl-internal-delay-ns = <5>;
218 #address-cells = <1>;
220 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
221 reg = <0xffc73000 0x1000>;
222 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
224 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
225 i2c-scl-internal-delay-ns = <5>;
229 scif0: serial@ffe40000 {
230 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
232 reg = <0xffe40000 0x100>;
233 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
235 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
236 clock-names = "fck", "brg_int", "scif_clk";
237 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
241 scif1: serial@ffe41000 {
242 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
244 reg = <0xffe41000 0x100>;
245 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
247 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
248 clock-names = "fck", "brg_int", "scif_clk";
249 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
253 scif2: serial@ffe42000 {
254 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
256 reg = <0xffe42000 0x100>;
257 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
259 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
260 clock-names = "fck", "brg_int", "scif_clk";
261 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
265 scif3: serial@ffe43000 {
266 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
268 reg = <0xffe43000 0x100>;
269 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
271 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
272 clock-names = "fck", "brg_int", "scif_clk";
273 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
277 scif4: serial@ffe44000 {
278 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
280 reg = <0xffe44000 0x100>;
281 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
283 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
284 clock-names = "fck", "brg_int", "scif_clk";
285 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
289 scif5: serial@ffe45000 {
290 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
292 reg = <0xffe45000 0x100>;
293 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
295 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
296 clock-names = "fck", "brg_int", "scif_clk";
297 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
301 hscif0: serial@ffe48000 {
302 compatible = "renesas,hscif-r8a7779",
303 "renesas,rcar-gen1-hscif", "renesas,hscif";
304 reg = <0xffe48000 96>;
305 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
307 <&cpg_clocks R8A7779_CLK_S>,
309 clock-names = "fck", "brg_int", "scif_clk";
310 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
314 hscif1: serial@ffe49000 {
315 compatible = "renesas,hscif-r8a7779",
316 "renesas,rcar-gen1-hscif", "renesas,hscif";
317 reg = <0xffe49000 96>;
318 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
320 <&cpg_clocks R8A7779_CLK_S>,
322 clock-names = "fck", "brg_int", "scif_clk";
323 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
328 compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
329 reg = <0xffe50000 0x8>;
330 clocks = <&mstp0_clks R8A7779_CLK_PWM>;
331 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
337 compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
338 reg = <0xffe51000 0x8>;
339 clocks = <&mstp0_clks R8A7779_CLK_PWM>;
340 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
346 compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
347 reg = <0xffe52000 0x8>;
348 clocks = <&mstp0_clks R8A7779_CLK_PWM>;
349 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
355 compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
356 reg = <0xffe53000 0x8>;
357 clocks = <&mstp0_clks R8A7779_CLK_PWM>;
358 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
364 compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
365 reg = <0xffe54000 0x8>;
366 clocks = <&mstp0_clks R8A7779_CLK_PWM>;
367 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
373 compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
374 reg = <0xffe55000 0x8>;
375 clocks = <&mstp0_clks R8A7779_CLK_PWM>;
376 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
382 compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
383 reg = <0xffe56000 0x8>;
384 clocks = <&mstp0_clks R8A7779_CLK_PWM>;
385 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
390 pfc: pinctrl@fffc0000 {
391 compatible = "renesas,pfc-r8a7779";
392 reg = <0xfffc0000 0x23c>;
396 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
397 reg = <0xffc48000 0x38>;
400 tmu0: timer@ffd80000 {
401 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
402 reg = <0xffd80000 0x30>;
403 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
408 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
410 #renesas,channels = <3>;
415 tmu1: timer@ffd81000 {
416 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
417 reg = <0xffd81000 0x30>;
418 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
423 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
425 #renesas,channels = <3>;
430 tmu2: timer@ffd82000 {
431 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
432 reg = <0xffd82000 0x30>;
433 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
438 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
440 #renesas,channels = <3>;
445 sata: sata@fc600000 {
446 compatible = "renesas,sata-r8a7779";
447 reg = <0xfc600000 0x200000>;
448 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
450 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
454 sdhi0: mmc@ffe4c000 {
455 compatible = "renesas,sdhi-r8a7779",
456 "renesas,rcar-gen1-sdhi";
457 reg = <0xffe4c000 0x100>;
458 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
460 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
464 sdhi1: mmc@ffe4d000 {
465 compatible = "renesas,sdhi-r8a7779",
466 "renesas,rcar-gen1-sdhi";
467 reg = <0xffe4d000 0x100>;
468 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
470 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
474 sdhi2: mmc@ffe4e000 {
475 compatible = "renesas,sdhi-r8a7779",
476 "renesas,rcar-gen1-sdhi";
477 reg = <0xffe4e000 0x100>;
478 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
480 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
484 sdhi3: mmc@ffe4f000 {
485 compatible = "renesas,sdhi-r8a7779",
486 "renesas,rcar-gen1-sdhi";
487 reg = <0xffe4f000 0x100>;
488 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
490 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
494 hspi0: spi@fffc7000 {
495 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
496 reg = <0xfffc7000 0x18>;
497 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
498 #address-cells = <1>;
500 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
501 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
505 hspi1: spi@fffc8000 {
506 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
507 reg = <0xfffc8000 0x18>;
508 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>;
511 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
512 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
516 hspi2: spi@fffc6000 {
517 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
518 reg = <0xfffc6000 0x18>;
519 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
522 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
523 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
527 du: display@fff80000 {
528 compatible = "renesas,du-r8a7779";
529 reg = <0xfff80000 0x40000>;
530 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&mstp1_clks R8A7779_CLK_DU>;
532 clock-names = "du.0";
533 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
537 #address-cells = <1>;
542 du_out_rgb0: endpoint {
547 du_out_rgb1: endpoint {
554 #address-cells = <1>;
558 /* External root clock */
560 compatible = "fixed-clock";
562 /* This value must be overriden by the board. */
563 clock-frequency = <0>;
566 /* External SCIF clock */
568 compatible = "fixed-clock";
570 /* This value must be overridden by the board. */
571 clock-frequency = <0>;
574 /* Special CPG clocks */
575 cpg_clocks: clocks@ffc80000 {
576 compatible = "renesas,r8a7779-cpg-clocks";
577 reg = <0xffc80000 0x30>;
578 clocks = <&extal_clk>;
580 clock-output-names = "plla", "z", "zs", "s",
581 "s1", "p", "b", "out";
582 #power-domain-cells = <0>;
585 /* Fixed factor clocks */
587 compatible = "fixed-factor-clock";
588 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
594 compatible = "fixed-factor-clock";
595 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
601 compatible = "fixed-factor-clock";
602 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
608 compatible = "fixed-factor-clock";
609 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
616 mstp0_clks: clocks@ffc80030 {
617 compatible = "renesas,r8a7779-mstp-clocks",
618 "renesas,cpg-mstp-clocks";
619 reg = <0xffc80030 4>;
620 clocks = <&cpg_clocks R8A7779_CLK_P>,
621 <&cpg_clocks R8A7779_CLK_S>,
622 <&cpg_clocks R8A7779_CLK_P>,
623 <&cpg_clocks R8A7779_CLK_P>,
624 <&cpg_clocks R8A7779_CLK_P>,
625 <&cpg_clocks R8A7779_CLK_S>,
626 <&cpg_clocks R8A7779_CLK_S>,
627 <&cpg_clocks R8A7779_CLK_P>,
628 <&cpg_clocks R8A7779_CLK_P>,
629 <&cpg_clocks R8A7779_CLK_P>,
630 <&cpg_clocks R8A7779_CLK_P>,
631 <&cpg_clocks R8A7779_CLK_P>,
632 <&cpg_clocks R8A7779_CLK_P>,
633 <&cpg_clocks R8A7779_CLK_P>,
634 <&cpg_clocks R8A7779_CLK_P>,
635 <&cpg_clocks R8A7779_CLK_P>,
636 <&cpg_clocks R8A7779_CLK_P>;
639 R8A7779_CLK_PWM R8A7779_CLK_HSPI
640 R8A7779_CLK_TMU2 R8A7779_CLK_TMU1
641 R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1
642 R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5
643 R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3
644 R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
645 R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3
646 R8A7779_CLK_I2C2 R8A7779_CLK_I2C1
650 "pwm", "hspi", "tmu2", "tmu1", "tmu0",
651 "hscif1", "hscif0", "scif5", "scif4", "scif3",
652 "scif2", "scif1", "scif0", "i2c3", "i2c2",
655 mstp1_clks: clocks@ffc80034 {
656 compatible = "renesas,r8a7779-mstp-clocks",
657 "renesas,cpg-mstp-clocks";
658 reg = <0xffc80034 4>, <0xffc80044 4>;
659 clocks = <&cpg_clocks R8A7779_CLK_P>,
660 <&cpg_clocks R8A7779_CLK_P>,
661 <&cpg_clocks R8A7779_CLK_S>,
662 <&cpg_clocks R8A7779_CLK_S>,
663 <&cpg_clocks R8A7779_CLK_S>,
664 <&cpg_clocks R8A7779_CLK_S>,
665 <&cpg_clocks R8A7779_CLK_P>,
666 <&cpg_clocks R8A7779_CLK_P>,
667 <&cpg_clocks R8A7779_CLK_P>,
668 <&cpg_clocks R8A7779_CLK_S>;
671 R8A7779_CLK_USB01 R8A7779_CLK_USB2
672 R8A7779_CLK_DU R8A7779_CLK_VIN2
673 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
674 R8A7779_CLK_ETHER R8A7779_CLK_SATA
675 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
684 mstp3_clks: clocks@ffc8003c {
685 compatible = "renesas,r8a7779-mstp-clocks",
686 "renesas,cpg-mstp-clocks";
687 reg = <0xffc8003c 4>;
688 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
689 <&s4_clk>, <&s4_clk>;
692 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
693 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
694 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
697 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
703 compatible = "simple-bus";
704 #address-cells = <1>;
706 ranges = <0 0 0x1c000000>;
709 prr: chipid@ff000044 {
710 compatible = "renesas,prr";
711 reg = <0xff000044 4>;
714 rst: reset-controller@ffcc0000 {
715 compatible = "renesas,r8a7779-reset-wdt";
716 reg = <0xffcc0000 0x48>;
719 sysc: system-controller@ffd85000 {
720 compatible = "renesas,r8a7779-sysc";
721 reg = <0xffd85000 0x0200>;
722 #power-domain-cells = <1>;