2 * Device Tree Source for the Alt board
4 * Copyright (C) 2014 Renesas Electronics Corporation
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
12 #include "r8a7794.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "renesas,alt", "renesas,r8a7794";
26 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
27 stdout-path = "serial0:115200n8";
31 device_type = "memory";
32 reg = <0 0x40000000 0 0x40000000>;
35 d3_3v: regulator-d3-3v {
36 compatible = "regulator-fixed";
37 regulator-name = "D3.3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
44 vcc_sdhi0: regulator-vcc-sdhi0 {
45 compatible = "regulator-fixed";
47 regulator-name = "SDHI0 Vcc";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
51 gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
55 vccq_sdhi0: regulator-vccq-sdhi0 {
56 compatible = "regulator-gpio";
58 regulator-name = "SDHI0 VccQ";
59 regulator-min-microvolt = <1800000>;
60 regulator-max-microvolt = <3300000>;
62 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
68 vcc_sdhi1: regulator-vcc-sdhi1 {
69 compatible = "regulator-fixed";
71 regulator-name = "SDHI1 Vcc";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
75 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
79 vccq_sdhi1: regulator-vccq-sdhi1 {
80 compatible = "regulator-gpio";
82 regulator-name = "SDHI1 VccQ";
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <3300000>;
86 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
98 compatible = "adi,adv7123";
101 #address-cells = <1>;
106 adv7123_in: endpoint {
107 remote-endpoint = <&du_out_rgb1>;
112 adv7123_out: endpoint {
113 remote-endpoint = <&vga_in>;
120 compatible = "vga-connector";
124 remote-endpoint = <&adv7123_out>;
130 compatible = "fixed-clock";
132 clock-frequency = <74250000>;
136 compatible = "fixed-clock";
138 clock-frequency = <148500000>;
142 #address-cells = <1>;
144 compatible = "i2c-gpio";
146 gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
147 &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
149 i2c-gpio,delay-us = <5>;
153 * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
154 * A fallback to GPIO is provided.
157 compatible = "i2c-demux-pinctrl";
158 i2c-parent = <&i2c4>, <&gpioi2c4>;
159 i2c-bus-name = "i2c-exio4";
160 #address-cells = <1>;
166 pinctrl-0 = <&du_pins>;
167 pinctrl-names = "default";
170 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
171 <&x13_clk>, <&x2_clk>;
172 clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
177 remote-endpoint = <&adv7123_in>;
184 clock-frequency = <20000000>;
188 pinctrl-0 = <&scif_clk_pins>;
189 pinctrl-names = "default";
192 groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
197 groups = "scif2_data";
201 scif_clk_pins: scif_clk {
203 function = "scif_clk";
207 groups = "eth_link", "eth_mdio", "eth_rmii";
212 groups = "intc_irq8";
227 groups = "vin0_data8", "vin0_clk";
231 mmcif0_pins: mmcif0 {
232 groups = "mmc_data8", "mmc_ctrl";
237 groups = "sdhi0_data4", "sdhi0_ctrl";
239 power-source = <3300>;
242 sdhi0_pins_uhs: sd0_uhs {
243 groups = "sdhi0_data4", "sdhi0_ctrl";
245 power-source = <1800>;
249 groups = "sdhi1_data4", "sdhi1_ctrl";
251 power-source = <3300>;
254 sdhi1_pins_uhs: sd1_uhs {
255 groups = "sdhi1_data4", "sdhi1_ctrl";
257 power-source = <1800>;
267 groups = "qspi_ctrl", "qspi_data4";
273 pinctrl-0 = <ðer_pins &phy1_pins>;
274 pinctrl-names = "default";
276 phy-handle = <&phy1>;
277 renesas,ether-link-active-low;
280 phy1: ethernet-phy@1 {
282 interrupt-parent = <&irqc0>;
283 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
284 micrel,led-mode = <1>;
289 pinctrl-0 = <&mmcif0_pins>;
290 pinctrl-names = "default";
292 vmmc-supply = <&d3_3v>;
293 vqmmc-supply = <&d3_3v>;
300 pinctrl-0 = <&sdhi0_pins>;
301 pinctrl-1 = <&sdhi0_pins_uhs>;
302 pinctrl-names = "default", "state_uhs";
304 vmmc-supply = <&vcc_sdhi0>;
305 vqmmc-supply = <&vccq_sdhi0>;
306 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
307 wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
314 pinctrl-0 = <&sdhi1_pins>;
315 pinctrl-1 = <&sdhi1_pins_uhs>;
316 pinctrl-names = "default", "state_uhs";
318 vmmc-supply = <&vcc_sdhi1>;
319 vqmmc-supply = <&vccq_sdhi1>;
320 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
321 wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
327 pinctrl-0 = <&i2c1_pins>;
328 pinctrl-names = "default";
331 clock-frequency = <400000>;
334 compatible = "adi,adv7180";
341 remote-endpoint = <&vin0ep>;
348 pinctrl-0 = <&i2c4_pins>;
349 pinctrl-names = "i2c-exio4";
354 pinctrl-0 = <&vin0_pins>;
355 pinctrl-names = "default";
358 #address-cells = <1>;
362 remote-endpoint = <&adv7180>;
369 pinctrl-0 = <&scif2_pins>;
370 pinctrl-names = "default";
376 clock-frequency = <14745600>;
380 pinctrl-0 = <&qspi_pins>;
381 pinctrl-names = "default";
386 compatible = "spansion,s25fl512s", "jedec,spi-nor";
388 spi-max-frequency = <30000000>;
389 spi-tx-bus-width = <4>;
390 spi-rx-bus-width = <4>;
396 compatible = "fixed-partitions";
397 #address-cells = <1>;
402 reg = <0x00000000 0x00040000>;
407 reg = <0x00040000 0x00040000>;
412 reg = <0x00080000 0x03f80000>;