arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37                 vin0 = &vin0;
  38                 vin1 = &vin1;
  39                 vin2 = &vin2;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0>;
  50                         clock-frequency = <1500000000>;
  51                         voltage-tolerance = <1>; /* 1% */
  52                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  53                         clock-latency = <300000>; /* 300 us */
  54
  55                         /* kHz - uV - OPPs unknown yet */
  56                         operating-points = <1500000 1000000>,
  57                                            <1312500 1000000>,
  58                                            <1125000 1000000>,
  59                                            < 937500 1000000>,
  60                                            < 750000 1000000>,
  61                                            < 375000 1000000>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <1>;
  68                         clock-frequency = <1500000000>;
  69                 };
  70         };
  71
  72         gic: interrupt-controller@f1001000 {
  73                 compatible = "arm,cortex-a15-gic";
  74                 #interrupt-cells = <3>;
  75                 #address-cells = <0>;
  76                 interrupt-controller;
  77                 reg = <0 0xf1001000 0 0x1000>,
  78                         <0 0xf1002000 0 0x1000>,
  79                         <0 0xf1004000 0 0x2000>,
  80                         <0 0xf1006000 0 0x2000>;
  81                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  82         };
  83
  84         gpio0: gpio@e6050000 {
  85                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  86                 reg = <0 0xe6050000 0 0x50>;
  87                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  88                 #gpio-cells = <2>;
  89                 gpio-controller;
  90                 gpio-ranges = <&pfc 0 0 32>;
  91                 #interrupt-cells = <2>;
  92                 interrupt-controller;
  93                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
  94         };
  95
  96         gpio1: gpio@e6051000 {
  97                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  98                 reg = <0 0xe6051000 0 0x50>;
  99                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 32 32>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 106         };
 107
 108         gpio2: gpio@e6052000 {
 109                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 110                 reg = <0 0xe6052000 0 0x50>;
 111                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 64 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 118         };
 119
 120         gpio3: gpio@e6053000 {
 121                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 122                 reg = <0 0xe6053000 0 0x50>;
 123                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 124                 #gpio-cells = <2>;
 125                 gpio-controller;
 126                 gpio-ranges = <&pfc 0 96 32>;
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 142         };
 143
 144         gpio5: gpio@e6055000 {
 145                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 146                 reg = <0 0xe6055000 0 0x50>;
 147                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 160 32>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 154         };
 155
 156         gpio6: gpio@e6055400 {
 157                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 158                 reg = <0 0xe6055400 0 0x50>;
 159                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 160                 #gpio-cells = <2>;
 161                 gpio-controller;
 162                 gpio-ranges = <&pfc 0 192 32>;
 163                 #interrupt-cells = <2>;
 164                 interrupt-controller;
 165                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 166         };
 167
 168         gpio7: gpio@e6055800 {
 169                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 170                 reg = <0 0xe6055800 0 0x50>;
 171                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 172                 #gpio-cells = <2>;
 173                 gpio-controller;
 174                 gpio-ranges = <&pfc 0 224 26>;
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 178         };
 179
 180         thermal@e61f0000 {
 181                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 182                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 183                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 185         };
 186
 187         timer {
 188                 compatible = "arm,armv7-timer";
 189                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 190                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 191                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 193         };
 194
 195         irqc0: interrupt-controller@e61c0000 {
 196                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 197                 #interrupt-cells = <2>;
 198                 interrupt-controller;
 199                 reg = <0 0xe61c0000 0 0x200>;
 200                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 201                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 202                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 203                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 204                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 205                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 206                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 207                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 208                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 209                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 210         };
 211
 212         dmac0: dma-controller@e6700000 {
 213                 compatible = "renesas,rcar-dmac";
 214                 reg = <0 0xe6700000 0 0x20000>;
 215                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 216                               0 200 IRQ_TYPE_LEVEL_HIGH
 217                               0 201 IRQ_TYPE_LEVEL_HIGH
 218                               0 202 IRQ_TYPE_LEVEL_HIGH
 219                               0 203 IRQ_TYPE_LEVEL_HIGH
 220                               0 204 IRQ_TYPE_LEVEL_HIGH
 221                               0 205 IRQ_TYPE_LEVEL_HIGH
 222                               0 206 IRQ_TYPE_LEVEL_HIGH
 223                               0 207 IRQ_TYPE_LEVEL_HIGH
 224                               0 208 IRQ_TYPE_LEVEL_HIGH
 225                               0 209 IRQ_TYPE_LEVEL_HIGH
 226                               0 210 IRQ_TYPE_LEVEL_HIGH
 227                               0 211 IRQ_TYPE_LEVEL_HIGH
 228                               0 212 IRQ_TYPE_LEVEL_HIGH
 229                               0 213 IRQ_TYPE_LEVEL_HIGH
 230                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 231                 interrupt-names = "error",
 232                                 "ch0", "ch1", "ch2", "ch3",
 233                                 "ch4", "ch5", "ch6", "ch7",
 234                                 "ch8", "ch9", "ch10", "ch11",
 235                                 "ch12", "ch13", "ch14";
 236                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 237                 clock-names = "fck";
 238                 #dma-cells = <1>;
 239                 dma-channels = <15>;
 240         };
 241
 242         dmac1: dma-controller@e6720000 {
 243                 compatible = "renesas,rcar-dmac";
 244                 reg = <0 0xe6720000 0 0x20000>;
 245                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 246                               0 216 IRQ_TYPE_LEVEL_HIGH
 247                               0 217 IRQ_TYPE_LEVEL_HIGH
 248                               0 218 IRQ_TYPE_LEVEL_HIGH
 249                               0 219 IRQ_TYPE_LEVEL_HIGH
 250                               0 308 IRQ_TYPE_LEVEL_HIGH
 251                               0 309 IRQ_TYPE_LEVEL_HIGH
 252                               0 310 IRQ_TYPE_LEVEL_HIGH
 253                               0 311 IRQ_TYPE_LEVEL_HIGH
 254                               0 312 IRQ_TYPE_LEVEL_HIGH
 255                               0 313 IRQ_TYPE_LEVEL_HIGH
 256                               0 314 IRQ_TYPE_LEVEL_HIGH
 257                               0 315 IRQ_TYPE_LEVEL_HIGH
 258                               0 316 IRQ_TYPE_LEVEL_HIGH
 259                               0 317 IRQ_TYPE_LEVEL_HIGH
 260                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 261                 interrupt-names = "error",
 262                                 "ch0", "ch1", "ch2", "ch3",
 263                                 "ch4", "ch5", "ch6", "ch7",
 264                                 "ch8", "ch9", "ch10", "ch11",
 265                                 "ch12", "ch13", "ch14";
 266                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 267                 clock-names = "fck";
 268                 #dma-cells = <1>;
 269                 dma-channels = <15>;
 270         };
 271
 272         /* The memory map in the User's Manual maps the cores to bus numbers */
 273         i2c0: i2c@e6508000 {
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 compatible = "renesas,i2c-r8a7791";
 277                 reg = <0 0xe6508000 0 0x40>;
 278                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 280                 status = "disabled";
 281         };
 282
 283         i2c1: i2c@e6518000 {
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 compatible = "renesas,i2c-r8a7791";
 287                 reg = <0 0xe6518000 0 0x40>;
 288                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 290                 status = "disabled";
 291         };
 292
 293         i2c2: i2c@e6530000 {
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 compatible = "renesas,i2c-r8a7791";
 297                 reg = <0 0xe6530000 0 0x40>;
 298                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 300                 status = "disabled";
 301         };
 302
 303         i2c3: i2c@e6540000 {
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 compatible = "renesas,i2c-r8a7791";
 307                 reg = <0 0xe6540000 0 0x40>;
 308                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 310                 status = "disabled";
 311         };
 312
 313         i2c4: i2c@e6520000 {
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 compatible = "renesas,i2c-r8a7791";
 317                 reg = <0 0xe6520000 0 0x40>;
 318                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 320                 status = "disabled";
 321         };
 322
 323         i2c5: i2c@e6528000 {
 324                 /* doesn't need pinmux */
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 compatible = "renesas,i2c-r8a7791";
 328                 reg = <0 0xe6528000 0 0x40>;
 329                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 331                 status = "disabled";
 332         };
 333
 334         i2c6: i2c@e60b0000 {
 335                 /* doesn't need pinmux */
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 339                 reg = <0 0xe60b0000 0 0x425>;
 340                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 341                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 342                 status = "disabled";
 343         };
 344
 345         i2c7: i2c@e6500000 {
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 349                 reg = <0 0xe6500000 0 0x425>;
 350                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 352                 status = "disabled";
 353         };
 354
 355         i2c8: i2c@e6510000 {
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 359                 reg = <0 0xe6510000 0 0x425>;
 360                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 361                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 362                 status = "disabled";
 363         };
 364
 365         pfc: pfc@e6060000 {
 366                 compatible = "renesas,pfc-r8a7791";
 367                 reg = <0 0xe6060000 0 0x250>;
 368                 #gpio-range-cells = <3>;
 369         };
 370
 371         sdhi0: sd@ee100000 {
 372                 compatible = "renesas,sdhi-r8a7791";
 373                 reg = <0 0xee100000 0 0x200>;
 374                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 376                 status = "disabled";
 377         };
 378
 379         sdhi1: sd@ee140000 {
 380                 compatible = "renesas,sdhi-r8a7791";
 381                 reg = <0 0xee140000 0 0x100>;
 382                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 384                 status = "disabled";
 385         };
 386
 387         sdhi2: sd@ee160000 {
 388                 compatible = "renesas,sdhi-r8a7791";
 389                 reg = <0 0xee160000 0 0x100>;
 390                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 392                 status = "disabled";
 393         };
 394
 395         scifa0: serial@e6c40000 {
 396                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 397                 reg = <0 0xe6c40000 0 64>;
 398                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 400                 clock-names = "sci_ick";
 401                 status = "disabled";
 402         };
 403
 404         scifa1: serial@e6c50000 {
 405                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 406                 reg = <0 0xe6c50000 0 64>;
 407                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 409                 clock-names = "sci_ick";
 410                 status = "disabled";
 411         };
 412
 413         scifa2: serial@e6c60000 {
 414                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 415                 reg = <0 0xe6c60000 0 64>;
 416                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 417                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 418                 clock-names = "sci_ick";
 419                 status = "disabled";
 420         };
 421
 422         scifa3: serial@e6c70000 {
 423                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 424                 reg = <0 0xe6c70000 0 64>;
 425                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 427                 clock-names = "sci_ick";
 428                 status = "disabled";
 429         };
 430
 431         scifa4: serial@e6c78000 {
 432                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 433                 reg = <0 0xe6c78000 0 64>;
 434                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 436                 clock-names = "sci_ick";
 437                 status = "disabled";
 438         };
 439
 440         scifa5: serial@e6c80000 {
 441                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 442                 reg = <0 0xe6c80000 0 64>;
 443                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 445                 clock-names = "sci_ick";
 446                 status = "disabled";
 447         };
 448
 449         scifb0: serial@e6c20000 {
 450                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 451                 reg = <0 0xe6c20000 0 64>;
 452                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 454                 clock-names = "sci_ick";
 455                 status = "disabled";
 456         };
 457
 458         scifb1: serial@e6c30000 {
 459                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 460                 reg = <0 0xe6c30000 0 64>;
 461                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 463                 clock-names = "sci_ick";
 464                 status = "disabled";
 465         };
 466
 467         scifb2: serial@e6ce0000 {
 468                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 469                 reg = <0 0xe6ce0000 0 64>;
 470                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 471                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 472                 clock-names = "sci_ick";
 473                 status = "disabled";
 474         };
 475
 476         scif0: serial@e6e60000 {
 477                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 478                 reg = <0 0xe6e60000 0 64>;
 479                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 480                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 481                 clock-names = "sci_ick";
 482                 status = "disabled";
 483         };
 484
 485         scif1: serial@e6e68000 {
 486                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 487                 reg = <0 0xe6e68000 0 64>;
 488                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 489                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 490                 clock-names = "sci_ick";
 491                 status = "disabled";
 492         };
 493
 494         scif2: serial@e6e58000 {
 495                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 496                 reg = <0 0xe6e58000 0 64>;
 497                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 499                 clock-names = "sci_ick";
 500                 status = "disabled";
 501         };
 502
 503         scif3: serial@e6ea8000 {
 504                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 505                 reg = <0 0xe6ea8000 0 64>;
 506                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 508                 clock-names = "sci_ick";
 509                 status = "disabled";
 510         };
 511
 512         scif4: serial@e6ee0000 {
 513                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 514                 reg = <0 0xe6ee0000 0 64>;
 515                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 517                 clock-names = "sci_ick";
 518                 status = "disabled";
 519         };
 520
 521         scif5: serial@e6ee8000 {
 522                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 523                 reg = <0 0xe6ee8000 0 64>;
 524                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 526                 clock-names = "sci_ick";
 527                 status = "disabled";
 528         };
 529
 530         hscif0: serial@e62c0000 {
 531                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 532                 reg = <0 0xe62c0000 0 96>;
 533                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 534                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 535                 clock-names = "sci_ick";
 536                 status = "disabled";
 537         };
 538
 539         hscif1: serial@e62c8000 {
 540                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 541                 reg = <0 0xe62c8000 0 96>;
 542                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 543                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 544                 clock-names = "sci_ick";
 545                 status = "disabled";
 546         };
 547
 548         hscif2: serial@e62d0000 {
 549                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 550                 reg = <0 0xe62d0000 0 96>;
 551                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 552                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 553                 clock-names = "sci_ick";
 554                 status = "disabled";
 555         };
 556
 557         ether: ethernet@ee700000 {
 558                 compatible = "renesas,ether-r8a7791";
 559                 reg = <0 0xee700000 0 0x400>;
 560                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 561                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 562                 phy-mode = "rmii";
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         sata0: sata@ee300000 {
 569                 compatible = "renesas,sata-r8a7791";
 570                 reg = <0 0xee300000 0 0x2000>;
 571                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 572                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 573                 status = "disabled";
 574         };
 575
 576         sata1: sata@ee500000 {
 577                 compatible = "renesas,sata-r8a7791";
 578                 reg = <0 0xee500000 0 0x2000>;
 579                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 580                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 581                 status = "disabled";
 582         };
 583
 584         vin0: video@e6ef0000 {
 585                 compatible = "renesas,vin-r8a7791";
 586                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 587                 reg = <0 0xe6ef0000 0 0x1000>;
 588                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 589                 status = "disabled";
 590         };
 591
 592         vin1: video@e6ef1000 {
 593                 compatible = "renesas,vin-r8a7791";
 594                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 595                 reg = <0 0xe6ef1000 0 0x1000>;
 596                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 597                 status = "disabled";
 598         };
 599
 600         vin2: video@e6ef2000 {
 601                 compatible = "renesas,vin-r8a7791";
 602                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 603                 reg = <0 0xe6ef2000 0 0x1000>;
 604                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 605                 status = "disabled";
 606         };
 607
 608         clocks {
 609                 #address-cells = <2>;
 610                 #size-cells = <2>;
 611                 ranges;
 612
 613                 /* External root clock */
 614                 extal_clk: extal_clk {
 615                         compatible = "fixed-clock";
 616                         #clock-cells = <0>;
 617                         /* This value must be overriden by the board. */
 618                         clock-frequency = <0>;
 619                         clock-output-names = "extal";
 620                 };
 621
 622                 /*
 623                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 624                  * default. Boards that provide audio clocks should override them.
 625                  */
 626                 audio_clk_a: audio_clk_a {
 627                         compatible = "fixed-clock";
 628                         #clock-cells = <0>;
 629                         clock-frequency = <0>;
 630                         clock-output-names = "audio_clk_a";
 631                 };
 632                 audio_clk_b: audio_clk_b {
 633                         compatible = "fixed-clock";
 634                         #clock-cells = <0>;
 635                         clock-frequency = <0>;
 636                         clock-output-names = "audio_clk_b";
 637                 };
 638                 audio_clk_c: audio_clk_c {
 639                         compatible = "fixed-clock";
 640                         #clock-cells = <0>;
 641                         clock-frequency = <0>;
 642                         clock-output-names = "audio_clk_c";
 643                 };
 644
 645                 /* External PCIe clock - can be overridden by the board */
 646                 pcie_bus_clk: pcie_bus_clk {
 647                         compatible = "fixed-clock";
 648                         #clock-cells = <0>;
 649                         clock-frequency = <100000000>;
 650                         clock-output-names = "pcie_bus";
 651                         status = "disabled";
 652                 };
 653
 654                 /* Special CPG clocks */
 655                 cpg_clocks: cpg_clocks@e6150000 {
 656                         compatible = "renesas,r8a7791-cpg-clocks",
 657                                      "renesas,rcar-gen2-cpg-clocks";
 658                         reg = <0 0xe6150000 0 0x1000>;
 659                         clocks = <&extal_clk>;
 660                         #clock-cells = <1>;
 661                         clock-output-names = "main", "pll0", "pll1", "pll3",
 662                                              "lb", "qspi", "sdh", "sd0", "z";
 663                 };
 664
 665                 /* Variable factor clocks */
 666                 sd1_clk: sd2_clk@e6150078 {
 667                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 668                         reg = <0 0xe6150078 0 4>;
 669                         clocks = <&pll1_div2_clk>;
 670                         #clock-cells = <0>;
 671                         clock-output-names = "sd1";
 672                 };
 673                 sd2_clk: sd3_clk@e615026c {
 674                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 675                         reg = <0 0xe615026c 0 4>;
 676                         clocks = <&pll1_div2_clk>;
 677                         #clock-cells = <0>;
 678                         clock-output-names = "sd2";
 679                 };
 680                 mmc0_clk: mmc0_clk@e6150240 {
 681                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 682                         reg = <0 0xe6150240 0 4>;
 683                         clocks = <&pll1_div2_clk>;
 684                         #clock-cells = <0>;
 685                         clock-output-names = "mmc0";
 686                 };
 687                 ssp_clk: ssp_clk@e6150248 {
 688                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 689                         reg = <0 0xe6150248 0 4>;
 690                         clocks = <&pll1_div2_clk>;
 691                         #clock-cells = <0>;
 692                         clock-output-names = "ssp";
 693                 };
 694                 ssprs_clk: ssprs_clk@e615024c {
 695                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 696                         reg = <0 0xe615024c 0 4>;
 697                         clocks = <&pll1_div2_clk>;
 698                         #clock-cells = <0>;
 699                         clock-output-names = "ssprs";
 700                 };
 701
 702                 /* Fixed factor clocks */
 703                 pll1_div2_clk: pll1_div2_clk {
 704                         compatible = "fixed-factor-clock";
 705                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 706                         #clock-cells = <0>;
 707                         clock-div = <2>;
 708                         clock-mult = <1>;
 709                         clock-output-names = "pll1_div2";
 710                 };
 711                 zg_clk: zg_clk {
 712                         compatible = "fixed-factor-clock";
 713                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 714                         #clock-cells = <0>;
 715                         clock-div = <3>;
 716                         clock-mult = <1>;
 717                         clock-output-names = "zg";
 718                 };
 719                 zx_clk: zx_clk {
 720                         compatible = "fixed-factor-clock";
 721                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 722                         #clock-cells = <0>;
 723                         clock-div = <3>;
 724                         clock-mult = <1>;
 725                         clock-output-names = "zx";
 726                 };
 727                 zs_clk: zs_clk {
 728                         compatible = "fixed-factor-clock";
 729                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 730                         #clock-cells = <0>;
 731                         clock-div = <6>;
 732                         clock-mult = <1>;
 733                         clock-output-names = "zs";
 734                 };
 735                 hp_clk: hp_clk {
 736                         compatible = "fixed-factor-clock";
 737                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 738                         #clock-cells = <0>;
 739                         clock-div = <12>;
 740                         clock-mult = <1>;
 741                         clock-output-names = "hp";
 742                 };
 743                 i_clk: i_clk {
 744                         compatible = "fixed-factor-clock";
 745                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 746                         #clock-cells = <0>;
 747                         clock-div = <2>;
 748                         clock-mult = <1>;
 749                         clock-output-names = "i";
 750                 };
 751                 b_clk: b_clk {
 752                         compatible = "fixed-factor-clock";
 753                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 754                         #clock-cells = <0>;
 755                         clock-div = <12>;
 756                         clock-mult = <1>;
 757                         clock-output-names = "b";
 758                 };
 759                 p_clk: p_clk {
 760                         compatible = "fixed-factor-clock";
 761                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 762                         #clock-cells = <0>;
 763                         clock-div = <24>;
 764                         clock-mult = <1>;
 765                         clock-output-names = "p";
 766                 };
 767                 cl_clk: cl_clk {
 768                         compatible = "fixed-factor-clock";
 769                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 770                         #clock-cells = <0>;
 771                         clock-div = <48>;
 772                         clock-mult = <1>;
 773                         clock-output-names = "cl";
 774                 };
 775                 m2_clk: m2_clk {
 776                         compatible = "fixed-factor-clock";
 777                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 778                         #clock-cells = <0>;
 779                         clock-div = <8>;
 780                         clock-mult = <1>;
 781                         clock-output-names = "m2";
 782                 };
 783                 imp_clk: imp_clk {
 784                         compatible = "fixed-factor-clock";
 785                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 786                         #clock-cells = <0>;
 787                         clock-div = <4>;
 788                         clock-mult = <1>;
 789                         clock-output-names = "imp";
 790                 };
 791                 rclk_clk: rclk_clk {
 792                         compatible = "fixed-factor-clock";
 793                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 794                         #clock-cells = <0>;
 795                         clock-div = <(48 * 1024)>;
 796                         clock-mult = <1>;
 797                         clock-output-names = "rclk";
 798                 };
 799                 oscclk_clk: oscclk_clk {
 800                         compatible = "fixed-factor-clock";
 801                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 802                         #clock-cells = <0>;
 803                         clock-div = <(12 * 1024)>;
 804                         clock-mult = <1>;
 805                         clock-output-names = "oscclk";
 806                 };
 807                 zb3_clk: zb3_clk {
 808                         compatible = "fixed-factor-clock";
 809                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 810                         #clock-cells = <0>;
 811                         clock-div = <4>;
 812                         clock-mult = <1>;
 813                         clock-output-names = "zb3";
 814                 };
 815                 zb3d2_clk: zb3d2_clk {
 816                         compatible = "fixed-factor-clock";
 817                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 818                         #clock-cells = <0>;
 819                         clock-div = <8>;
 820                         clock-mult = <1>;
 821                         clock-output-names = "zb3d2";
 822                 };
 823                 ddr_clk: ddr_clk {
 824                         compatible = "fixed-factor-clock";
 825                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 826                         #clock-cells = <0>;
 827                         clock-div = <8>;
 828                         clock-mult = <1>;
 829                         clock-output-names = "ddr";
 830                 };
 831                 mp_clk: mp_clk {
 832                         compatible = "fixed-factor-clock";
 833                         clocks = <&pll1_div2_clk>;
 834                         #clock-cells = <0>;
 835                         clock-div = <15>;
 836                         clock-mult = <1>;
 837                         clock-output-names = "mp";
 838                 };
 839                 cp_clk: cp_clk {
 840                         compatible = "fixed-factor-clock";
 841                         clocks = <&extal_clk>;
 842                         #clock-cells = <0>;
 843                         clock-div = <2>;
 844                         clock-mult = <1>;
 845                         clock-output-names = "cp";
 846                 };
 847
 848                 /* Gate clocks */
 849                 mstp0_clks: mstp0_clks@e6150130 {
 850                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 851                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 852                         clocks = <&mp_clk>;
 853                         #clock-cells = <1>;
 854                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 855                         clock-output-names = "msiof0";
 856                 };
 857                 mstp1_clks: mstp1_clks@e6150134 {
 858                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 859                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 860                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 861                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 862                         #clock-cells = <1>;
 863                         renesas,clock-indices = <
 864                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 865                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 866                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
 867                         >;
 868                         clock-output-names =
 869                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 870                                 "vsp1-du0", "vsp1-sy";
 871                 };
 872                 mstp2_clks: mstp2_clks@e6150138 {
 873                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 874                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 875                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 876                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
 877                                  <&zs_clk>, <&zs_clk>;
 878                         #clock-cells = <1>;
 879                         renesas,clock-indices = <
 880                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 881                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 882                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 883                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
 884                         >;
 885                         clock-output-names =
 886                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 887                                 "scifb1", "msiof1", "scifb2",
 888                                 "sys-dmac1", "sys-dmac0";
 889                 };
 890                 mstp3_clks: mstp3_clks@e615013c {
 891                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 892                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 893                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
 894                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 895                         #clock-cells = <1>;
 896                         renesas,clock-indices = <
 897                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
 898                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
 899                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
 900                         >;
 901                         clock-output-names =
 902                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
 903                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
 904                 };
 905                 mstp5_clks: mstp5_clks@e6150144 {
 906                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 907                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 908                         clocks = <&extal_clk>, <&p_clk>;
 909                         #clock-cells = <1>;
 910                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 911                         clock-output-names = "thermal", "pwm";
 912                 };
 913                 mstp7_clks: mstp7_clks@e615014c {
 914                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 915                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 916                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 917                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 918                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 919                         #clock-cells = <1>;
 920                         renesas,clock-indices = <
 921                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 922                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 923                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 924                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 925                                 R8A7791_CLK_LVDS0
 926                         >;
 927                         clock-output-names =
 928                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 929                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 930                 };
 931                 mstp8_clks: mstp8_clks@e6150990 {
 932                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 933                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 934                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 935                                  <&zs_clk>;
 936                         #clock-cells = <1>;
 937                         renesas,clock-indices = <
 938                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 939                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 940                         >;
 941                         clock-output-names =
 942                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 943                 };
 944                 mstp9_clks: mstp9_clks@e6150994 {
 945                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 946                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 947                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 948                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 949                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
 950                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
 951                                  <&hp_clk>, <&hp_clk>;
 952                         #clock-cells = <1>;
 953                         renesas,clock-indices = <
 954                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
 955                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
 956                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
 957                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
 958                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 959                         >;
 960                         clock-output-names =
 961                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 962                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
 963                                 "i2c1", "i2c0";
 964                 };
 965                 mstp10_clks: mstp10_clks@e6150998 {
 966                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 967                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
 968                         clocks = <&p_clk>,
 969                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 970                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 971                                 <&p_clk>,
 972                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 973                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 974                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 975                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 976                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
 977                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
 978
 979                         #clock-cells = <1>;
 980                         clock-indices = <
 981                                 R8A7791_CLK_SSI_ALL
 982                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
 983                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
 984                                 R8A7791_CLK_SCU_ALL
 985                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
 986                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
 987                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
 988                         >;
 989                         clock-output-names =
 990                                 "ssi-all",
 991                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
 992                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
 993                                 "scu-all",
 994                                 "scu-dvc1", "scu-dvc0",
 995                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
 996                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
 997                 };
 998                 mstp11_clks: mstp11_clks@e615099c {
 999                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1000                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1001                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1002                         #clock-cells = <1>;
1003                         renesas,clock-indices = <
1004                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1005                         >;
1006                         clock-output-names = "scifa3", "scifa4", "scifa5";
1007                 };
1008         };
1009
1010         qspi: spi@e6b10000 {
1011                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1012                 reg = <0 0xe6b10000 0 0x2c>;
1013                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1014                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1015                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1016                 dma-names = "tx", "rx";
1017                 num-cs = <1>;
1018                 #address-cells = <1>;
1019                 #size-cells = <0>;
1020                 status = "disabled";
1021         };
1022
1023         msiof0: spi@e6e20000 {
1024                 compatible = "renesas,msiof-r8a7791";
1025                 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1026                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1027                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1028                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1029                 dma-names = "tx", "rx";
1030                 #address-cells = <1>;
1031                 #size-cells = <0>;
1032                 status = "disabled";
1033         };
1034
1035         msiof1: spi@e6e10000 {
1036                 compatible = "renesas,msiof-r8a7791";
1037                 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1038                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1039                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1040                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1041                 dma-names = "tx", "rx";
1042                 #address-cells = <1>;
1043                 #size-cells = <0>;
1044                 status = "disabled";
1045         };
1046
1047         msiof2: spi@e6e00000 {
1048                 compatible = "renesas,msiof-r8a7791";
1049                 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1050                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1051                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1052                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1053                 dma-names = "tx", "rx";
1054                 #address-cells = <1>;
1055                 #size-cells = <0>;
1056                 status = "disabled";
1057         };
1058
1059         pci0: pci@ee090000 {
1060                 compatible = "renesas,pci-r8a7791";
1061                 device_type = "pci";
1062                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1063                 reg = <0 0xee090000 0 0xc00>,
1064                       <0 0xee080000 0 0x1100>;
1065                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1066                 status = "disabled";
1067
1068                 bus-range = <0 0>;
1069                 #address-cells = <3>;
1070                 #size-cells = <2>;
1071                 #interrupt-cells = <1>;
1072                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1073                 interrupt-map-mask = <0xff00 0 0 0x7>;
1074                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1075                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1076                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1077         };
1078
1079         pci1: pci@ee0d0000 {
1080                 compatible = "renesas,pci-r8a7791";
1081                 device_type = "pci";
1082                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1083                 reg = <0 0xee0d0000 0 0xc00>,
1084                       <0 0xee0c0000 0 0x1100>;
1085                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1086                 status = "disabled";
1087
1088                 bus-range = <1 1>;
1089                 #address-cells = <3>;
1090                 #size-cells = <2>;
1091                 #interrupt-cells = <1>;
1092                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1093                 interrupt-map-mask = <0xff00 0 0 0x7>;
1094                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1095                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1096                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1097         };
1098
1099         pciec: pcie@fe000000 {
1100                 compatible = "renesas,pcie-r8a7791";
1101                 reg = <0 0xfe000000 0 0x80000>;
1102                 #address-cells = <3>;
1103                 #size-cells = <2>;
1104                 bus-range = <0x00 0xff>;
1105                 device_type = "pci";
1106                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1107                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1108                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1109                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1110                 /* Map all possible DDR as inbound ranges */
1111                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1112                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1113                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1114                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1115                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1116                 #interrupt-cells = <1>;
1117                 interrupt-map-mask = <0 0 0 0>;
1118                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1119                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1120                 clock-names = "pcie", "pcie_bus";
1121                 status = "disabled";
1122         };
1123
1124         rcar_sound: rcar_sound@0xec500000 {
1125                 #sound-dai-cells = <1>;
1126                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1127                 interrupt-parent = <&gic>;
1128                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1129                         <0 0xec5a0000 0 0x100>,  /* ADG */
1130                         <0 0xec540000 0 0x1000>, /* SSIU */
1131                         <0 0xec541000 0 0x1280>; /* SSI */
1132                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1133                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1134                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1135                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1136                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1137                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1138                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1139                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1140                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1141                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1142                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1143                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1144                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1145                 clock-names = "ssi-all",
1146                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1147                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1148                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1149                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1150                                 "dvc.0", "dvc.1",
1151                                 "clk_a", "clk_b", "clk_c", "clk_i";
1152
1153                 status = "disabled";
1154
1155                 rcar_sound,dvc {
1156                         dvc0: dvc@0 { };
1157                         dvc1: dvc@1 { };
1158                 };
1159
1160                 rcar_sound,src {
1161                         src0: src@0 { };
1162                         src1: src@1 { };
1163                         src2: src@2 { };
1164                         src3: src@3 { };
1165                         src4: src@4 { };
1166                         src5: src@5 { };
1167                         src6: src@6 { };
1168                         src7: src@7 { };
1169                         src8: src@8 { };
1170                         src9: src@9 { };
1171                 };
1172
1173                 rcar_sound,ssi {
1174                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1175                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1176                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1177                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1178                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1179                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1180                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1181                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1182                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1183                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1184                 };
1185         };
1186 };