1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
21 clock-frequency = <19200000>;
24 sleep_clk: sleep_clk {
25 compatible = "fixed-clock";
27 clock-frequency = <32768>;
34 interrupts = <GIC_PPI 9 0xf04>;
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v2";
41 next-level-cache = <&L2>;
44 cpu-idle-states = <&CPU_SPC>;
48 compatible = "qcom,krait";
49 enable-method = "qcom,kpss-acc-v2";
52 next-level-cache = <&L2>;
55 cpu-idle-states = <&CPU_SPC>;
59 compatible = "qcom,krait";
60 enable-method = "qcom,kpss-acc-v2";
63 next-level-cache = <&L2>;
66 cpu-idle-states = <&CPU_SPC>;
70 compatible = "qcom,krait";
71 enable-method = "qcom,kpss-acc-v2";
74 next-level-cache = <&L2>;
77 cpu-idle-states = <&CPU_SPC>;
88 compatible = "qcom,idle-state-spc",
90 entry-latency-us = <150>;
91 exit-latency-us = <200>;
92 min-residency-us = <2000>;
99 compatible = "qcom,scm";
100 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
101 clock-names = "core", "bus", "iface";
106 device_type = "memory";
111 compatible = "qcom,krait-pmu";
112 interrupts = <GIC_PPI 7 0xf04>;
116 #address-cells = <1>;
120 mpss_region: mpss@8000000 {
121 reg = <0x08000000 0x5100000>;
125 mba_region: mba@d100000 {
126 reg = <0x0d100000 0x100000>;
130 wcnss_region: wcnss@d200000 {
131 reg = <0x0d200000 0xa00000>;
135 adsp_region: adsp@dc00000 {
136 reg = <0x0dc00000 0x1900000>;
140 venus_region: memory@f500000 {
141 reg = <0x0f500000 0x500000>;
145 smem_region: smem@fa00000 {
146 reg = <0xfa00000 0x200000>;
150 tz_region: memory@fc00000 {
151 reg = <0x0fc00000 0x160000>;
155 rfsa_mem: memory@fd60000 {
156 reg = <0x0fd60000 0x20000>;
161 compatible = "qcom,rmtfs-mem";
162 reg = <0x0fd80000 0x180000>;
165 qcom,client-id = <1>;
170 compatible = "qcom,smem";
172 memory-region = <&smem_region>;
173 qcom,rpm-msg-ram = <&rpm_msg_ram>;
175 hwlocks = <&tcsr_mutex 3>;
179 compatible = "qcom,smp2p";
180 qcom,smem = <443>, <429>;
182 interrupt-parent = <&intc>;
183 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
185 qcom,ipc = <&apcs 8 10>;
187 qcom,local-pid = <0>;
188 qcom,remote-pid = <2>;
190 adsp_smp2p_out: master-kernel {
191 qcom,entry-name = "master-kernel";
192 #qcom,smem-state-cells = <1>;
195 adsp_smp2p_in: slave-kernel {
196 qcom,entry-name = "slave-kernel";
198 interrupt-controller;
199 #interrupt-cells = <2>;
204 compatible = "qcom,smp2p";
205 qcom,smem = <435>, <428>;
207 interrupt-parent = <&intc>;
208 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
210 qcom,ipc = <&apcs 8 14>;
212 qcom,local-pid = <0>;
213 qcom,remote-pid = <1>;
215 modem_smp2p_out: master-kernel {
216 qcom,entry-name = "master-kernel";
217 #qcom,smem-state-cells = <1>;
220 modem_smp2p_in: slave-kernel {
221 qcom,entry-name = "slave-kernel";
223 interrupt-controller;
224 #interrupt-cells = <2>;
229 compatible = "qcom,smp2p";
230 qcom,smem = <451>, <431>;
232 interrupt-parent = <&intc>;
233 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
235 qcom,ipc = <&apcs 8 18>;
237 qcom,local-pid = <0>;
238 qcom,remote-pid = <4>;
240 wcnss_smp2p_out: master-kernel {
241 qcom,entry-name = "master-kernel";
243 #qcom,smem-state-cells = <1>;
246 wcnss_smp2p_in: slave-kernel {
247 qcom,entry-name = "slave-kernel";
249 interrupt-controller;
250 #interrupt-cells = <2>;
255 compatible = "qcom,smsm";
257 #address-cells = <1>;
260 qcom,ipc-1 = <&apcs 8 13>;
261 qcom,ipc-2 = <&apcs 8 9>;
262 qcom,ipc-3 = <&apcs 8 19>;
267 #qcom,smem-state-cells = <1>;
270 modem_smsm: modem@1 {
272 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
280 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
286 wcnss_smsm: wcnss@7 {
288 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
296 compatible = "qcom,smd";
299 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
300 qcom,ipc = <&apcs 8 0>;
301 qcom,smd-edge = <15>;
303 rpm_requests: rpm_requests {
304 compatible = "qcom,rpm-msm8974";
305 qcom,smd-channels = "rpm_requests";
307 rpmcc: clock-controller {
308 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
316 #address-cells = <1>;
319 compatible = "simple-bus";
321 intc: interrupt-controller@f9000000 {
322 compatible = "qcom,msm-qgic2";
323 interrupt-controller;
324 #interrupt-cells = <3>;
325 reg = <0xf9000000 0x1000>,
329 apcs: syscon@f9011000 {
330 compatible = "syscon";
331 reg = <0xf9011000 0x1000>;
335 #address-cells = <1>;
338 compatible = "arm,armv7-timer-mem";
339 reg = <0xf9020000 0x1000>;
340 clock-frequency = <19200000>;
344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
346 reg = <0xf9021000 0x1000>,
352 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
353 reg = <0xf9023000 0x1000>;
359 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
360 reg = <0xf9024000 0x1000>;
366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
367 reg = <0xf9025000 0x1000>;
373 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
374 reg = <0xf9026000 0x1000>;
380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
381 reg = <0xf9027000 0x1000>;
387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
388 reg = <0xf9028000 0x1000>;
393 saw0: power-controller@f9089000 {
394 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
395 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
398 saw1: power-controller@f9099000 {
399 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
400 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
403 saw2: power-controller@f90a9000 {
404 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
405 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
408 saw3: power-controller@f90b9000 {
409 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
410 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
413 saw_l2: power-controller@f9012000 {
414 compatible = "qcom,saw2";
415 reg = <0xf9012000 0x1000>;
419 acc0: clock-controller@f9088000 {
420 compatible = "qcom,kpss-acc-v2";
421 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
424 acc1: clock-controller@f9098000 {
425 compatible = "qcom,kpss-acc-v2";
426 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
429 acc2: clock-controller@f90a8000 {
430 compatible = "qcom,kpss-acc-v2";
431 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
434 acc3: clock-controller@f90b8000 {
435 compatible = "qcom,kpss-acc-v2";
436 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
439 sdhc_1: sdhci@f9824900 {
440 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
442 reg-names = "hc_mem", "core_mem";
443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "hc_irq", "pwr_irq";
446 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
447 <&gcc GCC_SDCC1_AHB_CLK>,
449 clock-names = "core", "iface", "xo";
456 sdhc_3: sdhci@f9864900 {
457 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
459 reg-names = "hc_mem", "core_mem";
460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "hc_irq", "pwr_irq";
463 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
464 <&gcc GCC_SDCC3_AHB_CLK>,
466 clock-names = "core", "iface", "xo";
469 #address-cells = <1>;
475 sdhc_2: sdhci@f98a4900 {
476 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
478 reg-names = "hc_mem", "core_mem";
479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
481 interrupt-names = "hc_irq", "pwr_irq";
482 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
483 <&gcc GCC_SDCC2_AHB_CLK>,
485 clock-names = "core", "iface", "xo";
488 #address-cells = <1>;
494 blsp1_uart1: serial@f991d000 {
495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
496 reg = <0xf991d000 0x1000>;
497 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
499 clock-names = "core", "iface";
503 blsp1_uart2: serial@f991e000 {
504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
505 reg = <0xf991e000 0x1000>;
506 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
508 clock-names = "core", "iface";
512 blsp1_i2c1: i2c@f9923000 {
514 compatible = "qcom,i2c-qup-v2.1.1";
515 reg = <0xf9923000 0x1000>;
516 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "core", "iface";
519 pinctrl-names = "default", "sleep";
520 pinctrl-0 = <&blsp1_i2c1_default>;
521 pinctrl-1 = <&blsp1_i2c1_sleep>;
522 #address-cells = <1>;
526 blsp1_i2c2: i2c@f9924000 {
528 compatible = "qcom,i2c-qup-v2.1.1";
529 reg = <0xf9924000 0x1000>;
530 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
532 clock-names = "core", "iface";
533 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_i2c2_default>;
535 pinctrl-1 = <&blsp1_i2c2_sleep>;
536 #address-cells = <1>;
540 blsp1_i2c3: i2c@f9925000 {
542 compatible = "qcom,i2c-qup-v2.1.1";
543 reg = <0xf9925000 0x1000>;
544 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
546 clock-names = "core", "iface";
547 pinctrl-names = "default", "sleep";
548 pinctrl-0 = <&blsp1_i2c3_default>;
549 pinctrl-1 = <&blsp1_i2c3_sleep>;
550 #address-cells = <1>;
554 blsp1_i2c6: i2c@f9928000 {
556 compatible = "qcom,i2c-qup-v2.1.1";
557 reg = <0xf9928000 0x1000>;
558 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
560 clock-names = "core", "iface";
561 pinctrl-names = "default", "sleep";
562 pinctrl-0 = <&blsp1_i2c6_default>;
563 pinctrl-1 = <&blsp1_i2c6_sleep>;
564 #address-cells = <1>;
568 blsp2_dma: dma-controller@f9944000 {
569 compatible = "qcom,bam-v1.4.0";
570 reg = <0xf9944000 0x19000>;
571 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
573 clock-names = "bam_clk";
578 blsp2_uart1: serial@f995d000 {
579 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
580 reg = <0xf995d000 0x1000>;
581 interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
582 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
583 clock-names = "core", "iface";
587 blsp2_uart2: serial@f995e000 {
588 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
589 reg = <0xf995e000 0x1000>;
590 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
592 clock-names = "core", "iface";
596 blsp2_uart4: serial@f9960000 {
597 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
598 reg = <0xf9960000 0x1000>;
599 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
601 clock-names = "core", "iface";
605 blsp2_i2c2: i2c@f9964000 {
607 compatible = "qcom,i2c-qup-v2.1.1";
608 reg = <0xf9964000 0x1000>;
609 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
611 clock-names = "core", "iface";
612 pinctrl-names = "default", "sleep";
613 pinctrl-0 = <&blsp2_i2c2_default>;
614 pinctrl-1 = <&blsp2_i2c2_sleep>;
615 #address-cells = <1>;
619 blsp2_i2c5: i2c@f9967000 {
621 compatible = "qcom,i2c-qup-v2.1.1";
622 reg = <0xf9967000 0x1000>;
623 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
625 clock-names = "core", "iface";
626 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
627 dma-names = "tx", "rx";
628 pinctrl-names = "default", "sleep";
629 pinctrl-0 = <&blsp2_i2c5_default>;
630 pinctrl-1 = <&blsp2_i2c5_sleep>;
631 #address-cells = <1>;
635 blsp2_i2c6: i2c@f9968000 {
637 compatible = "qcom,i2c-qup-v2.1.1";
638 reg = <0xf9968000 0x1000>;
639 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
641 clock-names = "core", "iface";
642 #address-cells = <1>;
647 compatible = "qcom,ci-hdrc";
648 reg = <0xf9a55000 0x200>,
650 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
652 <&gcc GCC_USB_HS_SYSTEM_CLK>;
653 clock-names = "iface", "core";
654 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
655 assigned-clock-rates = <75000000>;
656 resets = <&gcc GCC_USB_HS_BCR>;
657 reset-names = "core";
660 ahb-burst-config = <0>;
661 phy-names = "usb-phy";
667 compatible = "qcom,usb-hs-phy-msm8974",
670 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
671 clock-names = "ref", "sleep";
672 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
673 reset-names = "phy", "por";
678 compatible = "qcom,usb-hs-phy-msm8974",
681 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
682 clock-names = "ref", "sleep";
683 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
684 reset-names = "phy", "por";
691 compatible = "qcom,prng";
692 reg = <0xf9bff000 0x200>;
693 clocks = <&gcc GCC_PRNG_AHB_CLK>;
694 clock-names = "core";
697 pronto: remoteproc@fb21b000 {
698 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
699 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
700 reg-names = "ccu", "dxe", "pmu";
702 memory-region = <&wcnss_region>;
704 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
705 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
706 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
707 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
708 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
709 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
711 qcom,smem-states = <&wcnss_smp2p_out 0>;
712 qcom,smem-state-names = "stop";
717 compatible = "qcom,wcn3680";
719 clocks = <&rpmcc RPM_SMD_CXO_A2>;
724 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
726 qcom,ipc = <&apcs 8 17>;
730 compatible = "qcom,wcnss";
731 qcom,smd-channels = "WCNSS_CTRL";
734 qcom,mmio = <&pronto>;
737 compatible = "qcom,wcnss-bt";
741 compatible = "qcom,wcnss-wlan";
743 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
744 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
745 interrupt-names = "tx", "rx";
747 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
748 qcom,smem-state-names = "tx-enable",
756 compatible = "arm,coresight-tmc", "arm,primecell";
757 reg = <0xfc307000 0x1000>;
759 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
760 clock-names = "apb_pclk", "atclk";
765 remote-endpoint = <&replicator_in>;
773 remote-endpoint = <&merger_out>;
780 compatible = "arm,coresight-tpiu", "arm,primecell";
781 reg = <0xfc318000 0x1000>;
783 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
784 clock-names = "apb_pclk", "atclk";
789 remote-endpoint = <&replicator_out1>;
796 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
797 reg = <0xfc31a000 0x1000>;
799 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
800 clock-names = "apb_pclk", "atclk";
803 #address-cells = <1>;
807 * Not described input ports:
809 * 1 - connected trought funnel to Multimedia CPU
810 * 2 - connected to Wireless CPU
814 * 7 - connected to STM
818 funnel1_in5: endpoint {
819 remote-endpoint = <&kpss_out>;
826 funnel1_out: endpoint {
827 remote-endpoint = <&merger_in1>;
834 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
835 reg = <0xfc31b000 0x1000>;
837 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
838 clock-names = "apb_pclk", "atclk";
841 #address-cells = <1>;
845 * Not described input ports:
846 * 0 - connected trought funnel to Audio, Modem and
847 * Resource and Power Manager CPU's
848 * 2...7 - not-connected
852 merger_in1: endpoint {
853 remote-endpoint = <&funnel1_out>;
860 merger_out: endpoint {
861 remote-endpoint = <&etf_in>;
867 replicator@fc31c000 {
868 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
869 reg = <0xfc31c000 0x1000>;
871 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
872 clock-names = "apb_pclk", "atclk";
875 #address-cells = <1>;
880 replicator_out0: endpoint {
881 remote-endpoint = <&etr_in>;
886 replicator_out1: endpoint {
887 remote-endpoint = <&tpiu_in>;
894 replicator_in: endpoint {
895 remote-endpoint = <&etf_out>;
902 compatible = "arm,coresight-tmc", "arm,primecell";
903 reg = <0xfc322000 0x1000>;
905 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
906 clock-names = "apb_pclk", "atclk";
911 remote-endpoint = <&replicator_out0>;
918 compatible = "arm,coresight-etm4x", "arm,primecell";
919 reg = <0xfc33c000 0x1000>;
921 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
922 clock-names = "apb_pclk", "atclk";
929 remote-endpoint = <&kpss_in0>;
936 compatible = "arm,coresight-etm4x", "arm,primecell";
937 reg = <0xfc33d000 0x1000>;
939 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
940 clock-names = "apb_pclk", "atclk";
947 remote-endpoint = <&kpss_in1>;
954 compatible = "arm,coresight-etm4x", "arm,primecell";
955 reg = <0xfc33e000 0x1000>;
957 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
958 clock-names = "apb_pclk", "atclk";
965 remote-endpoint = <&kpss_in2>;
972 compatible = "arm,coresight-etm4x", "arm,primecell";
973 reg = <0xfc33f000 0x1000>;
975 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
976 clock-names = "apb_pclk", "atclk";
983 remote-endpoint = <&kpss_in3>;
989 /* KPSS funnel, only 4 inputs are used */
991 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
992 reg = <0xfc345000 0x1000>;
994 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
995 clock-names = "apb_pclk", "atclk";
998 #address-cells = <1>;
1003 kpss_in0: endpoint {
1004 remote-endpoint = <&etm0_out>;
1009 kpss_in1: endpoint {
1010 remote-endpoint = <&etm1_out>;
1015 kpss_in2: endpoint {
1016 remote-endpoint = <&etm2_out>;
1021 kpss_in3: endpoint {
1022 remote-endpoint = <&etm3_out>;
1029 kpss_out: endpoint {
1030 remote-endpoint = <&funnel1_in5>;
1036 gcc: clock-controller@fc400000 {
1037 compatible = "qcom,gcc-msm8974";
1040 #power-domain-cells = <1>;
1041 reg = <0xfc400000 0x4000>;
1044 rpm_msg_ram: memory@fc428000 {
1045 compatible = "qcom,rpm-msg-ram";
1046 reg = <0xfc428000 0x4000>;
1049 bimc: interconnect@fc380000 {
1050 reg = <0xfc380000 0x6a000>;
1051 compatible = "qcom,msm8974-bimc";
1052 #interconnect-cells = <1>;
1053 clock-names = "bus", "bus_a";
1054 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1055 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1058 snoc: interconnect@fc460000 {
1059 reg = <0xfc460000 0x4000>;
1060 compatible = "qcom,msm8974-snoc";
1061 #interconnect-cells = <1>;
1062 clock-names = "bus", "bus_a";
1063 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1064 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1067 pnoc: interconnect@fc468000 {
1068 reg = <0xfc468000 0x4000>;
1069 compatible = "qcom,msm8974-pnoc";
1070 #interconnect-cells = <1>;
1071 clock-names = "bus", "bus_a";
1072 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1073 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1076 ocmemnoc: interconnect@fc470000 {
1077 reg = <0xfc470000 0x4000>;
1078 compatible = "qcom,msm8974-ocmemnoc";
1079 #interconnect-cells = <1>;
1080 clock-names = "bus", "bus_a";
1081 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1082 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1085 mmssnoc: interconnect@fc478000 {
1086 reg = <0xfc478000 0x4000>;
1087 compatible = "qcom,msm8974-mmssnoc";
1088 #interconnect-cells = <1>;
1089 clock-names = "bus", "bus_a";
1090 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1091 <&mmcc MMSS_S0_AXI_CLK>;
1094 cnoc: interconnect@fc480000 {
1095 reg = <0xfc480000 0x4000>;
1096 compatible = "qcom,msm8974-cnoc";
1097 #interconnect-cells = <1>;
1098 clock-names = "bus", "bus_a";
1099 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1100 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1103 tsens: thermal-sensor@fc4a9000 {
1104 compatible = "qcom,msm8974-tsens";
1105 reg = <0xfc4a9000 0x1000>, /* TM */
1106 <0xfc4a8000 0x1000>; /* SROT */
1107 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1108 nvmem-cell-names = "calib", "calib_backup";
1109 #qcom,sensors = <11>;
1110 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1111 interrupt-names = "uplow";
1112 #thermal-sensor-cells = <1>;
1116 compatible = "qcom,pshold";
1117 reg = <0xfc4ab000 0x4>;
1120 qfprom: qfprom@fc4bc000 {
1121 #address-cells = <1>;
1123 compatible = "qcom,qfprom";
1124 reg = <0xfc4bc000 0x1000>;
1125 tsens_calib: calib@d0 {
1128 tsens_backup: backup@440 {
1133 spmi_bus: spmi@fc4cf000 {
1134 compatible = "qcom,spmi-pmic-arb";
1135 reg-names = "core", "intr", "cnfg";
1136 reg = <0xfc4cf000 0x1000>,
1137 <0xfc4cb000 0x1000>,
1138 <0xfc4ca000 0x1000>;
1139 interrupt-names = "periph_irq";
1140 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cells = <2>;
1145 interrupt-controller;
1146 #interrupt-cells = <4>;
1149 remoteproc_mss: remoteproc@fc880000 {
1150 compatible = "qcom,msm8974-mss-pil";
1151 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1152 reg-names = "qdsp6", "rmb";
1154 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1155 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1156 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1157 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1158 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1159 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1161 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1162 <&gcc GCC_MSS_CFG_AHB_CLK>,
1163 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1165 clock-names = "iface", "bus", "mem", "xo";
1167 resets = <&gcc GCC_MSS_RESTART>;
1168 reset-names = "mss_restart";
1170 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
1172 qcom,smem-states = <&modem_smp2p_out 0>;
1173 qcom,smem-state-names = "stop";
1176 memory-region = <&mba_region>;
1180 memory-region = <&mpss_region>;
1184 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1186 qcom,ipc = <&apcs 8 12>;
1187 qcom,smd-edge = <0>;
1193 tcsr_mutex_block: syscon@fd484000 {
1194 compatible = "syscon";
1195 reg = <0xfd484000 0x2000>;
1198 tcsr: syscon@fd4a0000 {
1199 compatible = "syscon";
1200 reg = <0xfd4a0000 0x10000>;
1203 tlmm: pinctrl@fd510000 {
1204 compatible = "qcom,msm8974-pinctrl";
1205 reg = <0xfd510000 0x4000>;
1207 gpio-ranges = <&tlmm 0 0 146>;
1209 interrupt-controller;
1210 #interrupt-cells = <2>;
1211 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1213 sdc1_off: sdc1-off {
1217 drive-strength = <2>;
1223 drive-strength = <2>;
1229 drive-strength = <2>;
1233 sdc2_off: sdc2-off {
1237 drive-strength = <2>;
1243 drive-strength = <2>;
1249 drive-strength = <2>;
1255 drive-strength = <2>;
1259 blsp1_uart2_active: blsp1-uart2-active {
1262 function = "blsp_uart2";
1263 drive-strength = <2>;
1269 function = "blsp_uart2";
1270 drive-strength = <4>;
1275 blsp2_uart1_active: blsp2-uart1-active {
1277 pins = "gpio41", "gpio44";
1278 function = "blsp_uart7";
1279 drive-strength = <2>;
1284 pins = "gpio42", "gpio43";
1285 function = "blsp_uart7";
1286 drive-strength = <2>;
1291 blsp2_uart1_sleep: blsp2-uart1-sleep {
1292 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1294 drive-strength = <2>;
1298 blsp2_uart4_active: blsp2-uart4-active {
1300 pins = "gpio53", "gpio56";
1301 function = "blsp_uart10";
1302 drive-strength = <2>;
1307 pins = "gpio54", "gpio55";
1308 function = "blsp_uart10";
1309 drive-strength = <2>;
1314 blsp1_i2c1_default: blsp1-i2c1-default {
1315 pins = "gpio2", "gpio3";
1316 function = "blsp_i2c1";
1317 drive-strength = <2>;
1321 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1322 pins = "gpio2", "gpio3";
1323 function = "blsp_i2c1";
1324 drive-strength = <2>;
1328 blsp1_i2c2_default: blsp1-i2c2-default {
1329 pins = "gpio6", "gpio7";
1330 function = "blsp_i2c2";
1331 drive-strength = <2>;
1335 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1336 pins = "gpio6", "gpio7";
1337 function = "blsp_i2c2";
1338 drive-strength = <2>;
1342 blsp1_i2c3_default: blsp1-i2c3-default {
1343 pins = "gpio10", "gpio11";
1344 function = "blsp_i2c3";
1345 drive-strength = <2>;
1349 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1350 pins = "gpio10", "gpio11";
1351 function = "blsp_i2c3";
1352 drive-strength = <2>;
1356 /* BLSP1_I2C4 info is missing */
1358 /* BLSP1_I2C5 info is missing */
1360 blsp1_i2c6_default: blsp1-i2c6-default {
1361 pins = "gpio29", "gpio30";
1362 function = "blsp_i2c6";
1363 drive-strength = <2>;
1367 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1368 pins = "gpio29", "gpio30";
1369 function = "blsp_i2c6";
1370 drive-strength = <2>;
1373 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1375 /* BLSP2_I2C1 info is missing */
1377 blsp2_i2c2_default: blsp2-i2c2-default {
1378 pins = "gpio47", "gpio48";
1379 function = "blsp_i2c8";
1380 drive-strength = <2>;
1384 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1385 pins = "gpio47", "gpio48";
1386 function = "blsp_i2c8";
1387 drive-strength = <2>;
1391 /* BLSP2_I2C3 info is missing */
1393 /* BLSP2_I2C4 info is missing */
1395 blsp2_i2c5_default: blsp2-i2c5-default {
1396 pins = "gpio83", "gpio84";
1397 function = "blsp_i2c11";
1398 drive-strength = <2>;
1402 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1403 pins = "gpio83", "gpio84";
1404 function = "blsp_i2c11";
1405 drive-strength = <2>;
1409 /* BLSP2_I2C6 info is missing - nobody uses it though? */
1411 spi8_default: spi8_default {
1414 function = "blsp_spi8";
1418 function = "blsp_spi8";
1422 function = "blsp_spi8";
1426 function = "blsp_spi8";
1431 mmcc: clock-controller@fd8c0000 {
1432 compatible = "qcom,mmcc-msm8974";
1435 #power-domain-cells = <1>;
1436 reg = <0xfd8c0000 0x6000>;
1439 mdss: mdss@fd900000 {
1440 compatible = "qcom,mdss";
1441 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1442 reg-names = "mdss_phys", "vbif_phys";
1444 power-domains = <&mmcc MDSS_GDSC>;
1446 clocks = <&mmcc MDSS_AHB_CLK>,
1447 <&mmcc MDSS_AXI_CLK>,
1448 <&mmcc MDSS_VSYNC_CLK>;
1449 clock-names = "iface", "bus", "vsync";
1451 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1453 interrupt-controller;
1454 #interrupt-cells = <1>;
1456 status = "disabled";
1458 #address-cells = <1>;
1463 compatible = "qcom,mdp5";
1464 reg = <0xfd900100 0x22000>;
1465 reg-names = "mdp_phys";
1467 interrupt-parent = <&mdss>;
1470 clocks = <&mmcc MDSS_AHB_CLK>,
1471 <&mmcc MDSS_AXI_CLK>,
1472 <&mmcc MDSS_MDP_CLK>,
1473 <&mmcc MDSS_VSYNC_CLK>;
1474 clock-names = "iface", "bus", "core", "vsync";
1476 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1477 interconnect-names = "mdp0-mem";
1480 #address-cells = <1>;
1485 mdp5_intf1_out: endpoint {
1486 remote-endpoint = <&dsi0_in>;
1492 dsi0: dsi@fd922800 {
1493 compatible = "qcom,mdss-dsi-ctrl";
1494 reg = <0xfd922800 0x1f8>;
1495 reg-names = "dsi_ctrl";
1497 interrupt-parent = <&mdss>;
1500 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1501 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1503 clocks = <&mmcc MDSS_MDP_CLK>,
1504 <&mmcc MDSS_AHB_CLK>,
1505 <&mmcc MDSS_AXI_CLK>,
1506 <&mmcc MDSS_BYTE0_CLK>,
1507 <&mmcc MDSS_PCLK0_CLK>,
1508 <&mmcc MDSS_ESC0_CLK>,
1509 <&mmcc MMSS_MISC_AHB_CLK>;
1510 clock-names = "mdp_core",
1519 phy-names = "dsi-phy";
1521 status = "disabled";
1523 #address-cells = <1>;
1527 #address-cells = <1>;
1533 remote-endpoint = <&mdp5_intf1_out>;
1539 dsi0_out: endpoint {
1545 dsi0_phy: dsi-phy@fd922a00 {
1546 compatible = "qcom,dsi-phy-28nm-hpm";
1547 reg = <0xfd922a00 0xd4>,
1550 reg-names = "dsi_pll",
1552 "dsi_phy_regulator";
1557 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1558 clock-names = "iface", "ref";
1560 status = "disabled";
1564 gpu: adreno@fdb00000 {
1565 compatible = "qcom,adreno-330.1", "qcom,adreno";
1566 reg = <0xfdb00000 0x10000>;
1567 reg-names = "kgsl_3d0_reg_memory";
1569 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1570 interrupt-names = "kgsl_3d0_irq";
1572 clocks = <&mmcc OXILI_GFX3D_CLK>,
1573 <&mmcc OXILICX_AHB_CLK>,
1574 <&mmcc OXILICX_AXI_CLK>;
1575 clock-names = "core", "iface", "mem_iface";
1578 power-domains = <&mmcc OXILICX_GDSC>;
1579 operating-points-v2 = <&gpu_opp_table>;
1581 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
1582 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
1583 interconnect-names = "gfx-mem", "ocmem";
1585 // iommus = <&gpu_iommu 0>;
1587 status = "disabled";
1589 gpu_opp_table: opp_table {
1590 compatible = "operating-points-v2";
1593 opp-hz = /bits/ 64 <320000000>;
1597 opp-hz = /bits/ 64 <200000000>;
1601 opp-hz = /bits/ 64 <27000000>;
1607 compatible = "qcom,msm8974-ocmem";
1608 reg = <0xfdd00000 0x2000>,
1609 <0xfec00000 0x180000>;
1610 reg-names = "ctrl", "mem";
1611 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1612 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1613 clock-names = "core", "iface";
1615 #address-cells = <1>;
1618 gmu_sram: gmu-sram@0 {
1619 reg = <0x0 0x100000>;
1623 remoteproc_adsp: remoteproc@fe200000 {
1624 compatible = "qcom,msm8974-adsp-pil";
1625 reg = <0xfe200000 0x100>;
1627 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1628 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1629 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1630 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1631 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1632 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1634 clocks = <&xo_board>;
1637 memory-region = <&adsp_region>;
1639 qcom,smem-states = <&adsp_smp2p_out 0>;
1640 qcom,smem-state-names = "stop";
1643 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1645 qcom,ipc = <&apcs 8 8>;
1646 qcom,smd-edge = <1>;
1648 #address-cells = <1>;
1653 imem: imem@fe805000 {
1654 compatible = "syscon", "simple-mfd";
1655 reg = <0xfe805000 0x1000>;
1658 compatible = "syscon-reboot-mode";
1664 tcsr_mutex: tcsr-mutex {
1665 compatible = "qcom,tcsr-mutex";
1666 syscon = <&tcsr_mutex_block 0 0x80>;
1668 #hwlock-cells = <1>;
1673 polling-delay-passive = <250>;
1674 polling-delay = <1000>;
1676 thermal-sensors = <&tsens 5>;
1680 temperature = <75000>;
1681 hysteresis = <2000>;
1685 temperature = <110000>;
1686 hysteresis = <2000>;
1693 polling-delay-passive = <250>;
1694 polling-delay = <1000>;
1696 thermal-sensors = <&tsens 6>;
1700 temperature = <75000>;
1701 hysteresis = <2000>;
1705 temperature = <110000>;
1706 hysteresis = <2000>;
1713 polling-delay-passive = <250>;
1714 polling-delay = <1000>;
1716 thermal-sensors = <&tsens 7>;
1720 temperature = <75000>;
1721 hysteresis = <2000>;
1725 temperature = <110000>;
1726 hysteresis = <2000>;
1733 polling-delay-passive = <250>;
1734 polling-delay = <1000>;
1736 thermal-sensors = <&tsens 8>;
1740 temperature = <75000>;
1741 hysteresis = <2000>;
1745 temperature = <110000>;
1746 hysteresis = <2000>;
1753 polling-delay-passive = <250>;
1754 polling-delay = <1000>;
1756 thermal-sensors = <&tsens 1>;
1759 q6_dsp_alert0: trip-point0 {
1760 temperature = <90000>;
1761 hysteresis = <2000>;
1768 polling-delay-passive = <250>;
1769 polling-delay = <1000>;
1771 thermal-sensors = <&tsens 2>;
1774 modemtx_alert0: trip-point0 {
1775 temperature = <90000>;
1776 hysteresis = <2000>;
1783 polling-delay-passive = <250>;
1784 polling-delay = <1000>;
1786 thermal-sensors = <&tsens 3>;
1789 video_alert0: trip-point0 {
1790 temperature = <95000>;
1791 hysteresis = <2000>;
1798 polling-delay-passive = <250>;
1799 polling-delay = <1000>;
1801 thermal-sensors = <&tsens 4>;
1804 wlan_alert0: trip-point0 {
1805 temperature = <105000>;
1806 hysteresis = <2000>;
1813 polling-delay-passive = <250>;
1814 polling-delay = <1000>;
1816 thermal-sensors = <&tsens 9>;
1819 gpu1_alert0: trip-point0 {
1820 temperature = <90000>;
1821 hysteresis = <2000>;
1827 gpu-bottom-thermal {
1828 polling-delay-passive = <250>;
1829 polling-delay = <1000>;
1831 thermal-sensors = <&tsens 10>;
1834 gpu2_alert0: trip-point0 {
1835 temperature = <90000>;
1836 hysteresis = <2000>;
1844 compatible = "arm,armv7-timer";
1845 interrupts = <GIC_PPI 2 0xf08>,
1849 clock-frequency = <19200000>;
1852 vreg_boost: vreg-boost {
1853 compatible = "regulator-fixed";
1855 regulator-name = "vreg-boost";
1856 regulator-min-microvolt = <3150000>;
1857 regulator-max-microvolt = <3150000>;
1859 regulator-always-on;
1862 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1865 pinctrl-names = "default";
1866 pinctrl-0 = <&boost_bypass_n_pin>;
1869 vreg_vph_pwr: vreg-vph-pwr {
1870 compatible = "regulator-fixed";
1871 regulator-name = "vph-pwr";
1873 regulator-min-microvolt = <3600000>;
1874 regulator-max-microvolt = <3600000>;
1876 regulator-always-on;