1 // SPDX-License-Identifier: GPL-2.0
4 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 model = "Qualcomm IPQ8064";
11 compatible = "qcom,ipq8064";
12 interrupt-parent = <&intc>;
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
23 next-level-cache = <&L2>;
29 compatible = "qcom,krait";
30 enable-method = "qcom,kpss-acc-v1";
33 next-level-cache = <&L2>;
45 compatible = "qcom,krait-pmu";
46 interrupts = <1 10 0x304>;
55 reg = <0x40000000 0x1000000>;
60 reg = <0x41000000 0x200000>;
67 compatible = "fixed-clock";
69 clock-frequency = <25000000>;
73 compatible = "fixed-clock";
75 clock-frequency = <25000000>;
78 sleep_clk: sleep_clk {
79 compatible = "fixed-clock";
80 clock-frequency = <32768>;
89 compatible = "simple-bus";
92 compatible = "qcom,lpass-cpu";
94 clocks = <&lcc AHBIX_CLK>,
97 clock-names = "ahbix-clk",
100 interrupts = <0 85 1>;
101 interrupt-names = "lpass-irq-lpaif";
102 reg = <0x28100000 0x10000>;
103 reg-names = "lpass-lpaif";
106 qcom_pinmux: pinmux@800000 {
107 compatible = "qcom,ipq8064-pinctrl";
108 reg = <0x800000 0x4000>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 interrupts = <0 16 0x4>;
117 intc: interrupt-controller@2000000 {
118 compatible = "qcom,msm-qgic2";
119 interrupt-controller;
120 #interrupt-cells = <3>;
121 reg = <0x02000000 0x1000>,
126 compatible = "qcom,kpss-timer",
127 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
128 interrupts = <1 1 0x301>,
133 reg = <0x0200a000 0x100>;
134 clock-frequency = <25000000>,
136 clocks = <&sleep_clk>;
137 clock-names = "sleep";
138 cpu-offset = <0x80000>;
141 acc0: clock-controller@2088000 {
142 compatible = "qcom,kpss-acc-v1";
143 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
146 acc1: clock-controller@2098000 {
147 compatible = "qcom,kpss-acc-v1";
148 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
151 saw0: regulator@2089000 {
152 compatible = "qcom,saw2";
153 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
157 saw1: regulator@2099000 {
158 compatible = "qcom,saw2";
159 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
163 gsbi2: gsbi@12480000 {
164 compatible = "qcom,gsbi-v1.0.0";
166 reg = <0x12480000 0x100>;
167 clocks = <&gcc GSBI2_H_CLK>;
168 clock-names = "iface";
169 #address-cells = <1>;
174 syscon-tcsr = <&tcsr>;
177 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
178 reg = <0x12490000 0x1000>,
180 interrupts = <0 195 0x0>;
181 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
182 clock-names = "core", "iface";
187 compatible = "qcom,i2c-qup-v1.1.1";
188 reg = <0x124a0000 0x1000>;
189 interrupts = <0 196 0>;
191 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
192 clock-names = "core", "iface";
195 #address-cells = <1>;
201 gsbi4: gsbi@16300000 {
202 compatible = "qcom,gsbi-v1.0.0";
204 reg = <0x16300000 0x100>;
205 clocks = <&gcc GSBI4_H_CLK>;
206 clock-names = "iface";
207 #address-cells = <1>;
212 syscon-tcsr = <&tcsr>;
214 gsbi4_serial: serial@16340000 {
215 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
216 reg = <0x16340000 0x1000>,
218 interrupts = <0 152 0x0>;
219 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
220 clock-names = "core", "iface";
225 compatible = "qcom,i2c-qup-v1.1.1";
226 reg = <0x16380000 0x1000>;
227 interrupts = <0 153 0>;
229 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
230 clock-names = "core", "iface";
233 #address-cells = <1>;
238 gsbi5: gsbi@1a200000 {
239 compatible = "qcom,gsbi-v1.0.0";
241 reg = <0x1a200000 0x100>;
242 clocks = <&gcc GSBI5_H_CLK>;
243 clock-names = "iface";
244 #address-cells = <1>;
249 syscon-tcsr = <&tcsr>;
252 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
253 reg = <0x1a240000 0x1000>,
255 interrupts = <0 154 0x0>;
256 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
257 clock-names = "core", "iface";
262 compatible = "qcom,i2c-qup-v1.1.1";
263 reg = <0x1a280000 0x1000>;
264 interrupts = <0 155 0>;
266 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
267 clock-names = "core", "iface";
270 #address-cells = <1>;
275 compatible = "qcom,spi-qup-v1.1.1";
276 reg = <0x1a280000 0x1000>;
277 interrupts = <0 155 0>;
279 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
280 clock-names = "core", "iface";
283 #address-cells = <1>;
288 gsbi7: gsbi@16600000 {
290 compatible = "qcom,gsbi-v1.0.0";
292 reg = <0x16600000 0x100>;
293 clocks = <&gcc GSBI7_H_CLK>;
294 clock-names = "iface";
295 #address-cells = <1>;
298 syscon-tcsr = <&tcsr>;
300 gsbi7_serial: serial@16640000 {
301 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
302 reg = <0x16640000 0x1000>,
304 interrupts = <0 158 0x0>;
305 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
306 clock-names = "core", "iface";
311 sata_phy: sata-phy@1b400000 {
312 compatible = "qcom,ipq806x-sata-phy";
313 reg = <0x1b400000 0x200>;
315 clocks = <&gcc SATA_PHY_CFG_CLK>;
323 compatible = "qcom,ipq806x-ahci", "generic-ahci";
324 reg = <0x29000000 0x180>;
326 interrupts = <0 209 0x0>;
328 clocks = <&gcc SFAB_SATA_S_H_CLK>,
331 <&gcc SATA_RXOOB_CLK>,
332 <&gcc SATA_PMALIVE_CLK>;
333 clock-names = "slave_face", "iface", "core",
336 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
337 assigned-clock-rates = <100000000>, <100000000>;
340 phy-names = "sata-phy";
345 compatible = "qcom,ssbi";
346 reg = <0x00500000 0x1000>;
347 qcom,controller-type = "pmic-arbiter";
350 gcc: clock-controller@900000 {
351 compatible = "qcom,gcc-ipq8064";
352 reg = <0x00900000 0x4000>;
357 tcsr: syscon@1a400000 {
358 compatible = "qcom,tcsr-ipq8064", "syscon";
359 reg = <0x1a400000 0x100>;
362 lcc: clock-controller@28000000 {
363 compatible = "qcom,lcc-ipq8064";
364 reg = <0x28000000 0x1000>;