1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 model = "Qualcomm Technologies, Inc. IPQ4019";
17 compatible = "qcom,ipq4019";
18 interrupt-parent = <&intc>;
21 #address-cells = <0x1>;
25 smem_region: smem@87e00000 {
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
103 compatible = "cache";
105 qcom,saw = <&saw_l2>;
109 cpu0_opp_table: opp_table0 {
110 compatible = "operating-points-v2";
114 opp-hz = /bits/ 64 <48000000>;
115 clock-latency-ns = <256000>;
118 opp-hz = /bits/ 64 <200000000>;
119 clock-latency-ns = <256000>;
122 opp-hz = /bits/ 64 <500000000>;
123 clock-latency-ns = <256000>;
126 opp-hz = /bits/ 64 <716000000>;
127 clock-latency-ns = <256000>;
132 device_type = "memory";
137 compatible = "arm,cortex-a7-pmu";
138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
139 IRQ_TYPE_LEVEL_HIGH)>;
143 sleep_clk: sleep_clk {
144 compatible = "fixed-clock";
145 clock-frequency = <32000>;
146 clock-output-names = "gcc_sleep_clk_src";
151 compatible = "fixed-clock";
152 clock-frequency = <48000000>;
159 compatible = "qcom,scm-ipq4019";
164 compatible = "arm,armv7-timer";
165 interrupts = <1 2 0xf08>,
169 clock-frequency = <48000000>;
174 #address-cells = <1>;
177 compatible = "simple-bus";
179 intc: interrupt-controller@b000000 {
180 compatible = "qcom,msm-qgic2";
181 interrupt-controller;
182 #interrupt-cells = <3>;
183 reg = <0x0b000000 0x1000>,
187 gcc: clock-controller@1800000 {
188 compatible = "qcom,gcc-ipq4019";
190 #power-domain-cells = <1>;
192 reg = <0x1800000 0x60000>;
196 compatible = "qcom,prng";
197 reg = <0x22000 0x140>;
198 clocks = <&gcc GCC_PRNG_AHB_CLK>;
199 clock-names = "core";
203 tlmm: pinctrl@1000000 {
204 compatible = "qcom,ipq4019-pinctrl";
205 reg = <0x01000000 0x300000>;
207 gpio-ranges = <&tlmm 0 0 100>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
211 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
214 vqmmc: regulator@1948000 {
215 compatible = "qcom,vqmmc-ipq4019-regulator";
216 reg = <0x01948000 0x4>;
217 regulator-name = "vqmmc";
218 regulator-min-microvolt = <1500000>;
219 regulator-max-microvolt = <3000000>;
224 sdhci: sdhci@7824900 {
225 compatible = "qcom,sdhci-msm-v4";
226 reg = <0x7824900 0x11c>, <0x7824000 0x800>;
227 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
228 interrupt-names = "hc_irq", "pwr_irq";
230 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
231 <&gcc GCC_DCD_XO_CLK>;
232 clock-names = "core", "iface", "xo";
236 blsp_dma: dma@7884000 {
237 compatible = "qcom,bam-v1.7.0";
238 reg = <0x07884000 0x23000>;
239 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
241 clock-names = "bam_clk";
247 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
248 compatible = "qcom,spi-qup-v2.2.1";
249 reg = <0x78b5000 0x600>;
250 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
252 <&gcc GCC_BLSP1_AHB_CLK>;
253 clock-names = "core", "iface";
254 #address-cells = <1>;
256 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
257 dma-names = "rx", "tx";
261 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
262 compatible = "qcom,spi-qup-v2.2.1";
263 reg = <0x78b6000 0x600>;
264 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
266 <&gcc GCC_BLSP1_AHB_CLK>;
267 clock-names = "core", "iface";
268 #address-cells = <1>;
270 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
271 dma-names = "rx", "tx";
275 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
276 compatible = "qcom,i2c-qup-v2.2.1";
277 reg = <0x78b7000 0x600>;
278 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
280 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
281 clock-names = "iface", "core";
282 #address-cells = <1>;
284 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
285 dma-names = "rx", "tx";
289 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
290 compatible = "qcom,i2c-qup-v2.2.1";
291 reg = <0x78b8000 0x600>;
292 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
294 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
295 clock-names = "iface", "core";
296 #address-cells = <1>;
298 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
299 dma-names = "rx", "tx";
303 cryptobam: dma@8e04000 {
304 compatible = "qcom,bam-v1.7.0";
305 reg = <0x08e04000 0x20000>;
306 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
308 clock-names = "bam_clk";
311 qcom,controlled-remotely;
315 crypto: crypto@8e3a000 {
316 compatible = "qcom,crypto-v5.1";
317 reg = <0x08e3a000 0x6000>;
318 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
319 <&gcc GCC_CRYPTO_AXI_CLK>,
320 <&gcc GCC_CRYPTO_CLK>;
321 clock-names = "iface", "bus", "core";
322 dmas = <&cryptobam 2>, <&cryptobam 3>;
323 dma-names = "rx", "tx";
327 acc0: clock-controller@b088000 {
328 compatible = "qcom,kpss-acc-v2";
329 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
332 acc1: clock-controller@b098000 {
333 compatible = "qcom,kpss-acc-v2";
334 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
337 acc2: clock-controller@b0a8000 {
338 compatible = "qcom,kpss-acc-v2";
339 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
342 acc3: clock-controller@b0b8000 {
343 compatible = "qcom,kpss-acc-v2";
344 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
347 saw0: regulator@b089000 {
348 compatible = "qcom,saw2";
349 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
353 saw1: regulator@b099000 {
354 compatible = "qcom,saw2";
355 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
359 saw2: regulator@b0a9000 {
360 compatible = "qcom,saw2";
361 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
365 saw3: regulator@b0b9000 {
366 compatible = "qcom,saw2";
367 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
371 saw_l2: regulator@b012000 {
372 compatible = "qcom,saw2";
373 reg = <0xb012000 0x1000>;
377 blsp1_uart1: serial@78af000 {
378 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
379 reg = <0x78af000 0x200>;
380 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
383 <&gcc GCC_BLSP1_AHB_CLK>;
384 clock-names = "core", "iface";
385 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
386 dma-names = "rx", "tx";
389 blsp1_uart2: serial@78b0000 {
390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
391 reg = <0x78b0000 0x200>;
392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
395 <&gcc GCC_BLSP1_AHB_CLK>;
396 clock-names = "core", "iface";
397 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
398 dma-names = "rx", "tx";
401 watchdog: watchdog@b017000 {
402 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
403 reg = <0xb017000 0x40>;
404 clocks = <&sleep_clk>;
410 compatible = "qcom,pshold";
411 reg = <0x4ab000 0x4>;
414 pcie0: pci@40000000 {
415 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
416 reg = <0x40000000 0xf1d
420 reg-names = "dbi", "elbi", "parf", "config";
422 linux,pci-domain = <0>;
423 bus-range = <0x00 0xff>;
425 #address-cells = <3>;
428 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
429 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
431 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-names = "msi";
433 #interrupt-cells = <1>;
434 interrupt-map-mask = <0 0 0 0x7>;
435 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
436 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
437 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
438 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
439 clocks = <&gcc GCC_PCIE_AHB_CLK>,
440 <&gcc GCC_PCIE_AXI_M_CLK>,
441 <&gcc GCC_PCIE_AXI_S_CLK>;
446 resets = <&gcc PCIE_AXI_M_ARES>,
447 <&gcc PCIE_AXI_S_ARES>,
448 <&gcc PCIE_PIPE_ARES>,
449 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
450 <&gcc PCIE_AXI_S_XPU_ARES>,
451 <&gcc PCIE_PARF_XPU_ARES>,
452 <&gcc PCIE_PHY_ARES>,
453 <&gcc PCIE_AXI_M_STICKY_ARES>,
454 <&gcc PCIE_PIPE_STICKY_ARES>,
455 <&gcc PCIE_PWR_ARES>,
456 <&gcc PCIE_AHB_ARES>,
457 <&gcc PCIE_PHY_AHB_ARES>;
458 reset-names = "axi_m",
474 qpic_bam: dma@7984000 {
475 compatible = "qcom,bam-v1.7.0";
476 reg = <0x7984000 0x1a000>;
477 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&gcc GCC_QPIC_CLK>;
479 clock-names = "bam_clk";
485 nand: nand-controller@79b0000 {
486 compatible = "qcom,ipq4019-nand";
487 reg = <0x79b0000 0x1000>;
488 #address-cells = <1>;
490 clocks = <&gcc GCC_QPIC_CLK>,
491 <&gcc GCC_QPIC_AHB_CLK>;
492 clock-names = "core", "aon";
494 dmas = <&qpic_bam 0>,
497 dma-names = "tx", "rx", "cmd";
503 nand-ecc-strength = <4>;
504 nand-ecc-step-size = <512>;
505 nand-bus-width = <8>;
509 wifi0: wifi@a000000 {
510 compatible = "qcom,ipq4019-wifi";
511 reg = <0xa000000 0x200000>;
512 resets = <&gcc WIFI0_CPU_INIT_RESET>,
513 <&gcc WIFI0_RADIO_SRIF_RESET>,
514 <&gcc WIFI0_RADIO_WARM_RESET>,
515 <&gcc WIFI0_RADIO_COLD_RESET>,
516 <&gcc WIFI0_CORE_WARM_RESET>,
517 <&gcc WIFI0_CORE_COLD_RESET>;
518 reset-names = "wifi_cpu_init", "wifi_radio_srif",
519 "wifi_radio_warm", "wifi_radio_cold",
520 "wifi_core_warm", "wifi_core_cold";
521 clocks = <&gcc GCC_WCSS2G_CLK>,
522 <&gcc GCC_WCSS2G_REF_CLK>,
523 <&gcc GCC_WCSS2G_RTC_CLK>;
524 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
526 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
527 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
528 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
529 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
530 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
531 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
532 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
533 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
534 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
535 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
536 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
537 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
538 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
540 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
543 interrupt-names = "msi0", "msi1", "msi2", "msi3",
544 "msi4", "msi5", "msi6", "msi7",
545 "msi8", "msi9", "msi10", "msi11",
546 "msi12", "msi13", "msi14", "msi15",
551 wifi1: wifi@a800000 {
552 compatible = "qcom,ipq4019-wifi";
553 reg = <0xa800000 0x200000>;
554 resets = <&gcc WIFI1_CPU_INIT_RESET>,
555 <&gcc WIFI1_RADIO_SRIF_RESET>,
556 <&gcc WIFI1_RADIO_WARM_RESET>,
557 <&gcc WIFI1_RADIO_COLD_RESET>,
558 <&gcc WIFI1_CORE_WARM_RESET>,
559 <&gcc WIFI1_CORE_COLD_RESET>;
560 reset-names = "wifi_cpu_init", "wifi_radio_srif",
561 "wifi_radio_warm", "wifi_radio_cold",
562 "wifi_core_warm", "wifi_core_cold";
563 clocks = <&gcc GCC_WCSS5G_CLK>,
564 <&gcc GCC_WCSS5G_REF_CLK>,
565 <&gcc GCC_WCSS5G_RTC_CLK>;
566 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
568 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
569 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
570 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
571 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
572 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
573 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
574 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
575 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
576 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
577 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
578 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
579 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
580 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
581 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
582 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
583 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
584 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
585 interrupt-names = "msi0", "msi1", "msi2", "msi3",
586 "msi4", "msi5", "msi6", "msi7",
587 "msi8", "msi9", "msi10", "msi11",
588 "msi12", "msi13", "msi14", "msi15",
594 #address-cells = <1>;
596 compatible = "qcom,ipq4019-mdio";
597 reg = <0x90000 0x64>;
600 ethphy0: ethernet-phy@0 {
604 ethphy1: ethernet-phy@1 {
608 ethphy2: ethernet-phy@2 {
612 ethphy3: ethernet-phy@3 {
616 ethphy4: ethernet-phy@4 {
621 usb3_ss_phy: ssphy@9a000 {
622 compatible = "qcom,usb-ss-ipq4019-phy";
624 reg = <0x9a000 0x800>;
625 reg-names = "phy_base";
626 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
627 reset-names = "por_rst";
631 usb3_hs_phy: hsphy@a6000 {
632 compatible = "qcom,usb-hs-ipq4019-phy";
634 reg = <0xa6000 0x40>;
635 reg-names = "phy_base";
636 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
637 reset-names = "por_rst", "srif_rst";
642 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
643 reg = <0x8af8800 0x100>;
644 #address-cells = <1>;
646 clocks = <&gcc GCC_USB3_MASTER_CLK>,
647 <&gcc GCC_USB3_SLEEP_CLK>,
648 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
649 clock-names = "master", "sleep", "mock_utmi";
654 compatible = "snps,dwc3";
655 reg = <0x8a00000 0xf8000>;
656 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
657 phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
658 phy-names = "usb2-phy", "usb3-phy";
663 usb2_hs_phy: hsphy@a8000 {
664 compatible = "qcom,usb-hs-ipq4019-phy";
666 reg = <0xa8000 0x40>;
667 reg-names = "phy_base";
668 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
669 reset-names = "por_rst", "srif_rst";
674 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
675 reg = <0x60f8800 0x100>;
676 #address-cells = <1>;
678 clocks = <&gcc GCC_USB2_MASTER_CLK>,
679 <&gcc GCC_USB2_SLEEP_CLK>,
680 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
681 clock-names = "master", "sleep", "mock_utmi";
686 compatible = "snps,dwc3";
687 reg = <0x6000000 0xf8000>;
688 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
689 phys = <&usb2_hs_phy>;
690 phy-names = "usb2-phy";