3 #include "skeleton.dtsi"
6 model = "Qualcomm APQ 8084";
7 compatible = "qcom,apq8084";
8 interrupt-parent = <&intc>;
16 compatible = "qcom,krait";
18 enable-method = "qcom,kpss-acc-v2";
19 next-level-cache = <&L2>;
25 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v2";
28 next-level-cache = <&L2>;
34 compatible = "qcom,krait";
36 enable-method = "qcom,kpss-acc-v2";
37 next-level-cache = <&L2>;
43 compatible = "qcom,krait";
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&L2>;
51 compatible = "qcom,arch-cache";
58 compatible = "qcom,krait-pmu";
59 interrupts = <1 7 0xf04>;
63 compatible = "arm,armv7-timer";
64 interrupts = <1 2 0xf08>,
68 clock-frequency = <19200000>;
75 compatible = "simple-bus";
77 intc: interrupt-controller@f9000000 {
78 compatible = "qcom,msm-qgic2";
80 #interrupt-cells = <3>;
81 reg = <0xf9000000 0x1000>,
89 compatible = "arm,armv7-timer-mem";
90 reg = <0xf9020000 0x1000>;
91 clock-frequency = <19200000>;
95 interrupts = <0 8 0x4>,
97 reg = <0xf9021000 0x1000>,
103 interrupts = <0 9 0x4>;
104 reg = <0xf9023000 0x1000>;
110 interrupts = <0 10 0x4>;
111 reg = <0xf9024000 0x1000>;
117 interrupts = <0 11 0x4>;
118 reg = <0xf9025000 0x1000>;
124 interrupts = <0 12 0x4>;
125 reg = <0xf9026000 0x1000>;
131 interrupts = <0 13 0x4>;
132 reg = <0xf9027000 0x1000>;
138 interrupts = <0 14 0x4>;
139 reg = <0xf9028000 0x1000>;
144 saw_l2: regulator@f9012000 {
145 compatible = "qcom,saw2";
146 reg = <0xf9012000 0x1000>;
150 acc0: clock-controller@f9088000 {
151 compatible = "qcom,kpss-acc-v2";
152 reg = <0xf9088000 0x1000>,
156 acc1: clock-controller@f9098000 {
157 compatible = "qcom,kpss-acc-v2";
158 reg = <0xf9098000 0x1000>,
162 acc2: clock-controller@f90a8000 {
163 compatible = "qcom,kpss-acc-v2";
164 reg = <0xf90a8000 0x1000>,
168 acc3: clock-controller@f90b8000 {
169 compatible = "qcom,kpss-acc-v2";
170 reg = <0xf90b8000 0x1000>,
175 compatible = "qcom,pshold";
176 reg = <0xfc4ab000 0x4>;