3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
19 smem_region: smem@80000000 {
20 reg = <0x80000000 0x200000>;
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
34 next-level-cache = <&L2>;
37 cpu-idle-states = <&CPU_SPC>;
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
45 next-level-cache = <&L2>;
48 cpu-idle-states = <&CPU_SPC>;
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
56 next-level-cache = <&L2>;
59 cpu-idle-states = <&CPU_SPC>;
63 compatible = "qcom,krait";
64 enable-method = "qcom,kpss-acc-v1";
67 next-level-cache = <&L2>;
70 cpu-idle-states = <&CPU_SPC>;
80 compatible = "qcom,idle-state-spc",
82 entry-latency-us = <400>;
83 exit-latency-us = <900>;
84 min-residency-us = <3000>;
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 10 0x304>;
95 compatible = "qcom,sfpb-mutex";
96 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
101 compatible = "qcom,smem";
102 memory-region = <&smem_region>;
104 hwlocks = <&sfpb_mutex 3>;
108 #address-cells = <1>;
111 compatible = "simple-bus";
113 tlmm_pinmux: pinctrl@800000 {
114 compatible = "qcom,apq8064-pinctrl";
115 reg = <0x800000 0x4000>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&ps_hold>;
126 sdc4_gpios: sdc4-gpios {
128 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
136 function = "ps_hold";
142 pins = "gpio20", "gpio21";
149 pins = "gpio8", "gpio9";
154 gsbi6_uart_2pins: gsbi6_uart_2pins {
156 pins = "gpio14", "gpio15";
161 gsbi6_uart_4pins: gsbi6_uart_4pins {
163 pins = "gpio14", "gpio15", "gpio16", "gpio17";
168 gsbi7_uart_2pins: gsbi7_uart_2pins {
170 pins = "gpio82", "gpio83";
175 gsbi7_uart_4pins: gsbi7_uart_4pins {
177 pins = "gpio82", "gpio83", "gpio84", "gpio85";
183 sfpb_wrapper_mutex: syscon@1200000 {
184 compatible = "syscon";
185 reg = <0x01200000 0x8000>;
188 intc: interrupt-controller@2000000 {
189 compatible = "qcom,msm-qgic2";
190 interrupt-controller;
191 #interrupt-cells = <3>;
192 reg = <0x02000000 0x1000>,
197 compatible = "qcom,kpss-timer", "qcom,msm-timer";
198 interrupts = <1 1 0x301>,
201 reg = <0x0200a000 0x100>;
202 clock-frequency = <27000000>,
204 cpu-offset = <0x80000>;
207 acc0: clock-controller@2088000 {
208 compatible = "qcom,kpss-acc-v1";
209 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
212 acc1: clock-controller@2098000 {
213 compatible = "qcom,kpss-acc-v1";
214 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
217 acc2: clock-controller@20a8000 {
218 compatible = "qcom,kpss-acc-v1";
219 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
222 acc3: clock-controller@20b8000 {
223 compatible = "qcom,kpss-acc-v1";
224 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
227 saw0: power-controller@2089000 {
228 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
229 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
233 saw1: power-controller@2099000 {
234 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
235 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
239 saw2: power-controller@20a9000 {
240 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
241 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
245 saw3: power-controller@20b9000 {
246 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
247 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
251 gsbi1: gsbi@12440000 {
253 compatible = "qcom,gsbi-v1.0.0";
255 reg = <0x12440000 0x100>;
256 clocks = <&gcc GSBI1_H_CLK>;
257 clock-names = "iface";
258 #address-cells = <1>;
262 syscon-tcsr = <&tcsr>;
265 compatible = "qcom,i2c-qup-v1.1.1";
266 pinctrl-0 = <&i2c1_pins>;
267 pinctrl-names = "default";
268 reg = <0x12460000 0x1000>;
269 interrupts = <0 194 IRQ_TYPE_NONE>;
270 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
271 clock-names = "core", "iface";
272 #address-cells = <1>;
277 gsbi2: gsbi@12480000 {
279 compatible = "qcom,gsbi-v1.0.0";
281 reg = <0x12480000 0x100>;
282 clocks = <&gcc GSBI2_H_CLK>;
283 clock-names = "iface";
284 #address-cells = <1>;
288 syscon-tcsr = <&tcsr>;
291 compatible = "qcom,i2c-qup-v1.1.1";
292 reg = <0x124a0000 0x1000>;
293 interrupts = <0 196 IRQ_TYPE_NONE>;
294 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
295 clock-names = "core", "iface";
296 #address-cells = <1>;
301 gsbi3: gsbi@16200000 {
303 compatible = "qcom,gsbi-v1.0.0";
305 reg = <0x16200000 0x100>;
306 clocks = <&gcc GSBI3_H_CLK>;
307 clock-names = "iface";
308 #address-cells = <1>;
312 compatible = "qcom,i2c-qup-v1.1.1";
313 pinctrl-0 = <&i2c3_pins>;
314 pinctrl-names = "default";
315 reg = <0x16280000 0x1000>;
316 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
317 clocks = <&gcc GSBI3_QUP_CLK>,
319 clock-names = "core", "iface";
323 gsbi5: gsbi@1a200000 {
325 compatible = "qcom,gsbi-v1.0.0";
327 reg = <0x1a200000 0x03>;
328 clocks = <&gcc GSBI5_H_CLK>;
329 clock-names = "iface";
330 #address-cells = <1>;
334 gsbi5_serial: serial@1a240000 {
335 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
336 reg = <0x1a240000 0x100>,
338 interrupts = <0 154 0x0>;
339 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
340 clock-names = "core", "iface";
345 gsbi6: gsbi@16500000 {
347 compatible = "qcom,gsbi-v1.0.0";
349 reg = <0x16500000 0x03>;
350 clocks = <&gcc GSBI6_H_CLK>;
351 clock-names = "iface";
352 #address-cells = <1>;
356 gsbi6_serial: serial@16540000 {
357 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
358 reg = <0x16540000 0x100>,
360 interrupts = <0 156 0x0>;
361 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
362 clock-names = "core", "iface";
367 gsbi7: gsbi@16600000 {
369 compatible = "qcom,gsbi-v1.0.0";
371 reg = <0x16600000 0x100>;
372 clocks = <&gcc GSBI7_H_CLK>;
373 clock-names = "iface";
374 #address-cells = <1>;
377 syscon-tcsr = <&tcsr>;
379 gsbi7_serial: serial@16640000 {
380 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
381 reg = <0x16640000 0x1000>,
383 interrupts = <0 158 0x0>;
384 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
385 clock-names = "core", "iface";
391 compatible = "qcom,prng";
392 reg = <0x1a500000 0x200>;
393 clocks = <&gcc PRNG_CLK>;
394 clock-names = "core";
398 compatible = "qcom,ssbi";
399 reg = <0x00500000 0x1000>;
400 qcom,controller-type = "pmic-arbiter";
403 compatible = "qcom,pm8921";
404 interrupt-parent = <&tlmm_pinmux>;
406 #interrupt-cells = <2>;
407 interrupt-controller;
408 #address-cells = <1>;
411 pm8921_gpio: gpio@150 {
413 compatible = "qcom,pm8921-gpio";
415 interrupts = <192 1>, <193 1>, <194 1>,
416 <195 1>, <196 1>, <197 1>,
417 <198 1>, <199 1>, <200 1>,
418 <201 1>, <202 1>, <203 1>,
419 <204 1>, <205 1>, <206 1>,
420 <207 1>, <208 1>, <209 1>,
421 <210 1>, <211 1>, <212 1>,
422 <213 1>, <214 1>, <215 1>,
423 <216 1>, <217 1>, <218 1>,
424 <219 1>, <220 1>, <221 1>,
425 <222 1>, <223 1>, <224 1>,
426 <225 1>, <226 1>, <227 1>,
427 <228 1>, <229 1>, <230 1>,
428 <231 1>, <232 1>, <233 1>,
436 pm8921_mpps: mpps@50 {
437 compatible = "qcom,pm8921-mpp";
442 <128 1>, <129 1>, <130 1>, <131 1>,
443 <132 1>, <133 1>, <134 1>, <135 1>,
444 <136 1>, <137 1>, <138 1>, <139 1>;
448 compatible = "qcom,pm8921-rtc";
449 interrupt-parent = <&pmicintc>;
456 compatible = "qcom,pm8921-pwrkey";
458 interrupt-parent = <&pmicintc>;
459 interrupts = <50 1>, <51 1>;
466 gcc: clock-controller@900000 {
467 compatible = "qcom,gcc-apq8064";
468 reg = <0x00900000 0x4000>;
473 lcc: clock-controller@28000000 {
474 compatible = "qcom,lcc-apq8064";
475 reg = <0x28000000 0x1000>;
480 mmcc: clock-controller@4000000 {
481 compatible = "qcom,mmcc-apq8064";
482 reg = <0x4000000 0x1000>;
487 l2cc: clock-controller@2011000 {
488 compatible = "syscon";
489 reg = <0x2011000 0x1000>;
493 compatible = "qcom,rpm-apq8064";
494 reg = <0x108000 0x1000>;
495 qcom,ipc = <&l2cc 0x8 2>;
497 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
498 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
499 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
500 interrupt-names = "ack", "err", "wakeup";
503 compatible = "qcom,rpm-pm8921-regulators";
539 pm8921_lvs1: lvs1 {};
540 pm8921_lvs2: lvs2 {};
541 pm8921_lvs3: lvs3 {};
542 pm8921_lvs4: lvs4 {};
543 pm8921_lvs5: lvs5 {};
544 pm8921_lvs6: lvs6 {};
545 pm8921_lvs7: lvs7 {};
547 pm8921_usb_switch: usb-switch {};
549 pm8921_hdmi_switch: hdmi-switch {
557 usb1_phy: phy@12500000 {
558 compatible = "qcom,usb-otg-ci";
559 reg = <0x12500000 0x400>;
560 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
564 clocks = <&gcc USB_HS1_XCVR_CLK>,
565 <&gcc USB_HS1_H_CLK>;
566 clock-names = "core", "iface";
568 resets = <&gcc USB_HS1_RESET>;
569 reset-names = "link";
572 usb3_phy: phy@12520000 {
573 compatible = "qcom,usb-otg-ci";
574 reg = <0x12520000 0x400>;
575 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
579 clocks = <&gcc USB_HS3_XCVR_CLK>,
580 <&gcc USB_HS3_H_CLK>;
581 clock-names = "core", "iface";
583 resets = <&gcc USB_HS3_RESET>;
584 reset-names = "link";
587 usb4_phy: phy@12530000 {
588 compatible = "qcom,usb-otg-ci";
589 reg = <0x12530000 0x400>;
590 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
594 clocks = <&gcc USB_HS4_XCVR_CLK>,
595 <&gcc USB_HS4_H_CLK>;
596 clock-names = "core", "iface";
598 resets = <&gcc USB_HS4_RESET>;
599 reset-names = "link";
602 gadget1: gadget@12500000 {
603 compatible = "qcom,ci-hdrc";
604 reg = <0x12500000 0x400>;
606 dr_mode = "peripheral";
607 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
608 usb-phy = <&usb1_phy>;
612 compatible = "qcom,ehci-host";
613 reg = <0x12500000 0x400>;
614 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
616 usb-phy = <&usb1_phy>;
620 compatible = "qcom,ehci-host";
621 reg = <0x12520000 0x400>;
622 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
624 usb-phy = <&usb3_phy>;
628 compatible = "qcom,ehci-host";
629 reg = <0x12530000 0x400>;
630 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
632 usb-phy = <&usb4_phy>;
635 sata_phy0: phy@1b400000 {
636 compatible = "qcom,apq8064-sata-phy";
638 reg = <0x1b400000 0x200>;
639 reg-names = "phy_mem";
640 clocks = <&gcc SATA_PHY_CFG_CLK>;
645 sata0: sata@29000000 {
646 compatible = "generic-ahci";
648 reg = <0x29000000 0x180>;
649 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
651 clocks = <&gcc SFAB_SATA_S_H_CLK>,
654 <&gcc SATA_RXOOB_CLK>,
655 <&gcc SATA_PMALIVE_CLK>;
656 clock-names = "slave_iface",
662 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
663 <&gcc SATA_PMALIVE_CLK>;
664 assigned-clock-rates = <100000000>, <100000000>;
667 phy-names = "sata-phy";
670 /* Temporary fixed regulator */
671 sdcc1bam:dma@12402000{
672 compatible = "qcom,bam-v1.3.0";
673 reg = <0x12402000 0x8000>;
674 interrupts = <0 98 0>;
675 clocks = <&gcc SDC1_H_CLK>;
676 clock-names = "bam_clk";
681 sdcc3bam:dma@12182000{
682 compatible = "qcom,bam-v1.3.0";
683 reg = <0x12182000 0x8000>;
684 interrupts = <0 96 0>;
685 clocks = <&gcc SDC3_H_CLK>;
686 clock-names = "bam_clk";
691 sdcc4bam:dma@121c2000{
692 compatible = "qcom,bam-v1.3.0";
693 reg = <0x121c2000 0x8000>;
694 interrupts = <0 95 0>;
695 clocks = <&gcc SDC4_H_CLK>;
696 clock-names = "bam_clk";
702 compatible = "arm,amba-bus";
703 #address-cells = <1>;
706 sdcc1: sdcc@12400000 {
708 compatible = "arm,pl18x", "arm,primecell";
709 arm,primecell-periphid = <0x00051180>;
710 reg = <0x12400000 0x2000>;
711 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
712 interrupt-names = "cmd_irq";
713 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
714 clock-names = "mclk", "apb_pclk";
716 max-frequency = <96000000>;
720 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
721 dma-names = "tx", "rx";
724 sdcc3: sdcc@12180000 {
725 compatible = "arm,pl18x", "arm,primecell";
726 arm,primecell-periphid = <0x00051180>;
728 reg = <0x12180000 0x2000>;
729 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
730 interrupt-names = "cmd_irq";
731 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
732 clock-names = "mclk", "apb_pclk";
736 max-frequency = <192000000>;
738 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
739 dma-names = "tx", "rx";
742 sdcc4: sdcc@121c0000 {
743 compatible = "arm,pl18x", "arm,primecell";
744 arm,primecell-periphid = <0x00051180>;
746 reg = <0x121c0000 0x2000>;
747 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
748 interrupt-names = "cmd_irq";
749 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
750 clock-names = "mclk", "apb_pclk";
754 max-frequency = <48000000>;
755 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
756 dma-names = "tx", "rx";
757 pinctrl-names = "default";
758 pinctrl-0 = <&sdc4_gpios>;
762 tcsr: syscon@1a400000 {
763 compatible = "qcom,tcsr-apq8064", "syscon";
764 reg = <0x1a400000 0x100>;