1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
21 clock-frequency = <19200000>;
24 sleep_clk: sleep_clk {
25 compatible = "fixed-clock";
27 clock-frequency = <32768>;
34 interrupts = <GIC_PPI 9 0xf04>;
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v2";
41 next-level-cache = <&L2>;
44 cpu-idle-states = <&CPU_SPC>;
48 compatible = "qcom,krait";
49 enable-method = "qcom,kpss-acc-v2";
52 next-level-cache = <&L2>;
55 cpu-idle-states = <&CPU_SPC>;
59 compatible = "qcom,krait";
60 enable-method = "qcom,kpss-acc-v2";
63 next-level-cache = <&L2>;
66 cpu-idle-states = <&CPU_SPC>;
70 compatible = "qcom,krait";
71 enable-method = "qcom,kpss-acc-v2";
74 next-level-cache = <&L2>;
77 cpu-idle-states = <&CPU_SPC>;
89 compatible = "qcom,idle-state-spc",
91 entry-latency-us = <150>;
92 exit-latency-us = <200>;
93 min-residency-us = <2000>;
100 compatible = "qcom,scm-msm8974", "qcom,scm";
101 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
102 clock-names = "core", "bus", "iface";
107 device_type = "memory";
112 compatible = "qcom,krait-pmu";
113 interrupts = <GIC_PPI 7 0xf04>;
117 #address-cells = <1>;
121 mpss_region: mpss@8000000 {
122 reg = <0x08000000 0x5100000>;
126 mba_region: mba@d100000 {
127 reg = <0x0d100000 0x100000>;
131 wcnss_region: wcnss@d200000 {
132 reg = <0x0d200000 0xa00000>;
136 adsp_region: adsp@dc00000 {
137 reg = <0x0dc00000 0x1900000>;
141 venus_region: memory@f500000 {
142 reg = <0x0f500000 0x500000>;
146 smem_region: smem@fa00000 {
147 reg = <0xfa00000 0x200000>;
151 tz_region: memory@fc00000 {
152 reg = <0x0fc00000 0x160000>;
156 rfsa_mem: memory@fd60000 {
157 reg = <0x0fd60000 0x20000>;
162 compatible = "qcom,rmtfs-mem";
163 reg = <0x0fd80000 0x180000>;
166 qcom,client-id = <1>;
171 compatible = "qcom,smem";
173 memory-region = <&smem_region>;
174 qcom,rpm-msg-ram = <&rpm_msg_ram>;
176 hwlocks = <&tcsr_mutex 3>;
180 compatible = "qcom,smp2p";
181 qcom,smem = <443>, <429>;
183 interrupt-parent = <&intc>;
184 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
186 qcom,ipc = <&apcs 8 10>;
188 qcom,local-pid = <0>;
189 qcom,remote-pid = <2>;
191 adsp_smp2p_out: master-kernel {
192 qcom,entry-name = "master-kernel";
193 #qcom,smem-state-cells = <1>;
196 adsp_smp2p_in: slave-kernel {
197 qcom,entry-name = "slave-kernel";
199 interrupt-controller;
200 #interrupt-cells = <2>;
205 compatible = "qcom,smp2p";
206 qcom,smem = <435>, <428>;
208 interrupt-parent = <&intc>;
209 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
211 qcom,ipc = <&apcs 8 14>;
213 qcom,local-pid = <0>;
214 qcom,remote-pid = <1>;
216 modem_smp2p_out: master-kernel {
217 qcom,entry-name = "master-kernel";
218 #qcom,smem-state-cells = <1>;
221 modem_smp2p_in: slave-kernel {
222 qcom,entry-name = "slave-kernel";
224 interrupt-controller;
225 #interrupt-cells = <2>;
230 compatible = "qcom,smp2p";
231 qcom,smem = <451>, <431>;
233 interrupt-parent = <&intc>;
234 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
236 qcom,ipc = <&apcs 8 18>;
238 qcom,local-pid = <0>;
239 qcom,remote-pid = <4>;
241 wcnss_smp2p_out: master-kernel {
242 qcom,entry-name = "master-kernel";
244 #qcom,smem-state-cells = <1>;
247 wcnss_smp2p_in: slave-kernel {
248 qcom,entry-name = "slave-kernel";
250 interrupt-controller;
251 #interrupt-cells = <2>;
256 compatible = "qcom,smsm";
258 #address-cells = <1>;
261 qcom,ipc-1 = <&apcs 8 13>;
262 qcom,ipc-2 = <&apcs 8 9>;
263 qcom,ipc-3 = <&apcs 8 19>;
268 #qcom,smem-state-cells = <1>;
271 modem_smsm: modem@1 {
273 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
281 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
287 wcnss_smsm: wcnss@7 {
289 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
297 compatible = "qcom,smd";
300 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
301 qcom,ipc = <&apcs 8 0>;
302 qcom,smd-edge = <15>;
304 rpm_requests: rpm-requests {
305 compatible = "qcom,rpm-msm8974";
306 qcom,smd-channels = "rpm_requests";
308 rpmcc: clock-controller {
309 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
311 clocks = <&xo_board>;
319 #address-cells = <1>;
322 compatible = "simple-bus";
324 intc: interrupt-controller@f9000000 {
325 compatible = "qcom,msm-qgic2";
326 interrupt-controller;
327 #interrupt-cells = <3>;
328 reg = <0xf9000000 0x1000>,
332 apcs: syscon@f9011000 {
333 compatible = "syscon";
334 reg = <0xf9011000 0x1000>;
338 #address-cells = <1>;
341 compatible = "arm,armv7-timer-mem";
342 reg = <0xf9020000 0x1000>;
343 clock-frequency = <19200000>;
347 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
349 reg = <0xf9021000 0x1000>,
355 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
356 reg = <0xf9023000 0x1000>;
362 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
363 reg = <0xf9024000 0x1000>;
369 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
370 reg = <0xf9025000 0x1000>;
376 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
377 reg = <0xf9026000 0x1000>;
383 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
384 reg = <0xf9027000 0x1000>;
390 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
391 reg = <0xf9028000 0x1000>;
396 saw0: power-controller@f9089000 {
397 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
398 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
401 saw1: power-controller@f9099000 {
402 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
403 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
406 saw2: power-controller@f90a9000 {
407 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
408 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
411 saw3: power-controller@f90b9000 {
412 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
413 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
416 saw_l2: power-controller@f9012000 {
417 compatible = "qcom,saw2";
418 reg = <0xf9012000 0x1000>;
422 acc0: power-manager@f9088000 {
423 compatible = "qcom,kpss-acc-v2";
424 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
427 acc1: power-manager@f9098000 {
428 compatible = "qcom,kpss-acc-v2";
429 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
432 acc2: power-manager@f90a8000 {
433 compatible = "qcom,kpss-acc-v2";
434 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
437 acc3: power-manager@f90b8000 {
438 compatible = "qcom,kpss-acc-v2";
439 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
442 sdhc_1: mmc@f9824900 {
443 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
444 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
445 reg-names = "hc", "core";
446 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "hc_irq", "pwr_irq";
449 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
450 <&gcc GCC_SDCC1_APPS_CLK>,
452 clock-names = "iface", "core", "xo";
459 sdhc_3: mmc@f9864900 {
460 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
461 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
462 reg-names = "hc", "core";
463 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "hc_irq", "pwr_irq";
466 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
467 <&gcc GCC_SDCC3_APPS_CLK>,
469 clock-names = "iface", "core", "xo";
472 #address-cells = <1>;
478 sdhc_2: mmc@f98a4900 {
479 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
480 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
481 reg-names = "hc", "core";
482 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-names = "hc_irq", "pwr_irq";
485 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
486 <&gcc GCC_SDCC2_APPS_CLK>,
488 clock-names = "iface", "core", "xo";
491 #address-cells = <1>;
497 blsp1_uart1: serial@f991d000 {
498 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
499 reg = <0xf991d000 0x1000>;
500 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
502 clock-names = "core", "iface";
506 blsp1_uart2: serial@f991e000 {
507 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
508 reg = <0xf991e000 0x1000>;
509 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
511 clock-names = "core", "iface";
512 pinctrl-names = "default";
513 pinctrl-0 = <&blsp1_uart2_default>;
517 blsp1_i2c1: i2c@f9923000 {
519 compatible = "qcom,i2c-qup-v2.1.1";
520 reg = <0xf9923000 0x1000>;
521 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", "iface";
524 pinctrl-names = "default", "sleep";
525 pinctrl-0 = <&blsp1_i2c1_default>;
526 pinctrl-1 = <&blsp1_i2c1_sleep>;
527 #address-cells = <1>;
531 blsp1_i2c2: i2c@f9924000 {
533 compatible = "qcom,i2c-qup-v2.1.1";
534 reg = <0xf9924000 0x1000>;
535 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", "iface";
538 pinctrl-names = "default", "sleep";
539 pinctrl-0 = <&blsp1_i2c2_default>;
540 pinctrl-1 = <&blsp1_i2c2_sleep>;
541 #address-cells = <1>;
545 blsp1_i2c3: i2c@f9925000 {
547 compatible = "qcom,i2c-qup-v2.1.1";
548 reg = <0xf9925000 0x1000>;
549 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
551 clock-names = "core", "iface";
552 pinctrl-names = "default", "sleep";
553 pinctrl-0 = <&blsp1_i2c3_default>;
554 pinctrl-1 = <&blsp1_i2c3_sleep>;
555 #address-cells = <1>;
559 blsp1_i2c6: i2c@f9928000 {
561 compatible = "qcom,i2c-qup-v2.1.1";
562 reg = <0xf9928000 0x1000>;
563 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
565 clock-names = "core", "iface";
566 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_i2c6_default>;
568 pinctrl-1 = <&blsp1_i2c6_sleep>;
569 #address-cells = <1>;
573 blsp2_dma: dma-controller@f9944000 {
574 compatible = "qcom,bam-v1.4.0";
575 reg = <0xf9944000 0x19000>;
576 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
578 clock-names = "bam_clk";
583 blsp2_uart1: serial@f995d000 {
584 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
585 reg = <0xf995d000 0x1000>;
586 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
588 clock-names = "core", "iface";
589 pinctrl-names = "default", "sleep";
590 pinctrl-0 = <&blsp2_uart1_default>;
591 pinctrl-1 = <&blsp2_uart1_sleep>;
595 blsp2_uart2: serial@f995e000 {
596 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597 reg = <0xf995e000 0x1000>;
598 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
600 clock-names = "core", "iface";
604 blsp2_uart4: serial@f9960000 {
605 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
606 reg = <0xf9960000 0x1000>;
607 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
609 clock-names = "core", "iface";
610 pinctrl-names = "default";
611 pinctrl-0 = <&blsp2_uart4_default>;
615 blsp2_i2c2: i2c@f9964000 {
617 compatible = "qcom,i2c-qup-v2.1.1";
618 reg = <0xf9964000 0x1000>;
619 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
621 clock-names = "core", "iface";
622 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&blsp2_i2c2_default>;
624 pinctrl-1 = <&blsp2_i2c2_sleep>;
625 #address-cells = <1>;
629 blsp2_i2c5: i2c@f9967000 {
631 compatible = "qcom,i2c-qup-v2.1.1";
632 reg = <0xf9967000 0x1000>;
633 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
635 clock-names = "core", "iface";
636 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
637 dma-names = "tx", "rx";
638 pinctrl-names = "default", "sleep";
639 pinctrl-0 = <&blsp2_i2c5_default>;
640 pinctrl-1 = <&blsp2_i2c5_sleep>;
641 #address-cells = <1>;
645 blsp2_i2c6: i2c@f9968000 {
647 compatible = "qcom,i2c-qup-v2.1.1";
648 reg = <0xf9968000 0x1000>;
649 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
651 clock-names = "core", "iface";
652 pinctrl-names = "default", "sleep";
653 pinctrl-0 = <&blsp2_i2c6_default>;
654 pinctrl-1 = <&blsp2_i2c6_sleep>;
655 #address-cells = <1>;
660 compatible = "qcom,ci-hdrc";
661 reg = <0xf9a55000 0x200>,
663 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
665 <&gcc GCC_USB_HS_SYSTEM_CLK>;
666 clock-names = "iface", "core";
667 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
668 assigned-clock-rates = <75000000>;
669 resets = <&gcc GCC_USB_HS_BCR>;
670 reset-names = "core";
673 ahb-burst-config = <0>;
674 phy-names = "usb-phy";
680 compatible = "qcom,usb-hs-phy-msm8974",
683 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
684 clock-names = "ref", "sleep";
685 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
686 reset-names = "phy", "por";
691 compatible = "qcom,usb-hs-phy-msm8974",
694 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
695 clock-names = "ref", "sleep";
696 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
697 reset-names = "phy", "por";
704 compatible = "qcom,prng";
705 reg = <0xf9bff000 0x200>;
706 clocks = <&gcc GCC_PRNG_AHB_CLK>;
707 clock-names = "core";
710 pronto: remoteproc@fb204000 {
711 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
712 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
713 reg-names = "ccu", "dxe", "pmu";
715 memory-region = <&wcnss_region>;
717 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
718 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
719 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
720 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
721 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
722 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
724 qcom,smem-states = <&wcnss_smp2p_out 0>;
725 qcom,smem-state-names = "stop";
730 compatible = "qcom,wcn3680";
732 clocks = <&rpmcc RPM_SMD_CXO_A2>;
737 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
739 qcom,ipc = <&apcs 8 17>;
743 compatible = "qcom,wcnss";
744 qcom,smd-channels = "WCNSS_CTRL";
747 qcom,mmio = <&pronto>;
750 compatible = "qcom,wcnss-bt";
754 compatible = "qcom,wcnss-wlan";
756 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
757 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
758 interrupt-names = "tx", "rx";
760 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
761 qcom,smem-state-names = "tx-enable",
769 compatible = "qcom,msm8974-rpm-stats";
770 reg = <0xfc190000 0x10000>;
774 compatible = "arm,coresight-tmc", "arm,primecell";
775 reg = <0xfc307000 0x1000>;
777 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
778 clock-names = "apb_pclk", "atclk";
783 remote-endpoint = <&replicator_in>;
791 remote-endpoint = <&merger_out>;
798 compatible = "arm,coresight-tpiu", "arm,primecell";
799 reg = <0xfc318000 0x1000>;
801 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
802 clock-names = "apb_pclk", "atclk";
807 remote-endpoint = <&replicator_out1>;
814 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
815 reg = <0xfc31a000 0x1000>;
817 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
818 clock-names = "apb_pclk", "atclk";
821 #address-cells = <1>;
825 * Not described input ports:
827 * 1 - connected trought funnel to Multimedia CPU
828 * 2 - connected to Wireless CPU
832 * 7 - connected to STM
836 funnel1_in5: endpoint {
837 remote-endpoint = <&kpss_out>;
844 funnel1_out: endpoint {
845 remote-endpoint = <&merger_in1>;
852 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
853 reg = <0xfc31b000 0x1000>;
855 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
856 clock-names = "apb_pclk", "atclk";
859 #address-cells = <1>;
863 * Not described input ports:
864 * 0 - connected trought funnel to Audio, Modem and
865 * Resource and Power Manager CPU's
866 * 2...7 - not-connected
870 merger_in1: endpoint {
871 remote-endpoint = <&funnel1_out>;
878 merger_out: endpoint {
879 remote-endpoint = <&etf_in>;
885 replicator@fc31c000 {
886 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
887 reg = <0xfc31c000 0x1000>;
889 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
890 clock-names = "apb_pclk", "atclk";
893 #address-cells = <1>;
898 replicator_out0: endpoint {
899 remote-endpoint = <&etr_in>;
904 replicator_out1: endpoint {
905 remote-endpoint = <&tpiu_in>;
912 replicator_in: endpoint {
913 remote-endpoint = <&etf_out>;
920 compatible = "arm,coresight-tmc", "arm,primecell";
921 reg = <0xfc322000 0x1000>;
923 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
924 clock-names = "apb_pclk", "atclk";
929 remote-endpoint = <&replicator_out0>;
936 compatible = "arm,coresight-etm4x", "arm,primecell";
937 reg = <0xfc33c000 0x1000>;
939 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
940 clock-names = "apb_pclk", "atclk";
947 remote-endpoint = <&kpss_in0>;
954 compatible = "arm,coresight-etm4x", "arm,primecell";
955 reg = <0xfc33d000 0x1000>;
957 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
958 clock-names = "apb_pclk", "atclk";
965 remote-endpoint = <&kpss_in1>;
972 compatible = "arm,coresight-etm4x", "arm,primecell";
973 reg = <0xfc33e000 0x1000>;
975 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
976 clock-names = "apb_pclk", "atclk";
983 remote-endpoint = <&kpss_in2>;
990 compatible = "arm,coresight-etm4x", "arm,primecell";
991 reg = <0xfc33f000 0x1000>;
993 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
994 clock-names = "apb_pclk", "atclk";
1000 etm3_out: endpoint {
1001 remote-endpoint = <&kpss_in3>;
1007 /* KPSS funnel, only 4 inputs are used */
1009 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1010 reg = <0xfc345000 0x1000>;
1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1013 clock-names = "apb_pclk", "atclk";
1016 #address-cells = <1>;
1021 kpss_in0: endpoint {
1022 remote-endpoint = <&etm0_out>;
1027 kpss_in1: endpoint {
1028 remote-endpoint = <&etm1_out>;
1033 kpss_in2: endpoint {
1034 remote-endpoint = <&etm2_out>;
1039 kpss_in3: endpoint {
1040 remote-endpoint = <&etm3_out>;
1047 kpss_out: endpoint {
1048 remote-endpoint = <&funnel1_in5>;
1054 gcc: clock-controller@fc400000 {
1055 compatible = "qcom,gcc-msm8974";
1058 #power-domain-cells = <1>;
1059 reg = <0xfc400000 0x4000>;
1061 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1067 rpm_msg_ram: sram@fc428000 {
1068 compatible = "qcom,rpm-msg-ram";
1069 reg = <0xfc428000 0x4000>;
1072 bimc: interconnect@fc380000 {
1073 reg = <0xfc380000 0x6a000>;
1074 compatible = "qcom,msm8974-bimc";
1075 #interconnect-cells = <1>;
1076 clock-names = "bus", "bus_a";
1077 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1078 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1081 snoc: interconnect@fc460000 {
1082 reg = <0xfc460000 0x4000>;
1083 compatible = "qcom,msm8974-snoc";
1084 #interconnect-cells = <1>;
1085 clock-names = "bus", "bus_a";
1086 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1087 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1090 pnoc: interconnect@fc468000 {
1091 reg = <0xfc468000 0x4000>;
1092 compatible = "qcom,msm8974-pnoc";
1093 #interconnect-cells = <1>;
1094 clock-names = "bus", "bus_a";
1095 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1096 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1099 ocmemnoc: interconnect@fc470000 {
1100 reg = <0xfc470000 0x4000>;
1101 compatible = "qcom,msm8974-ocmemnoc";
1102 #interconnect-cells = <1>;
1103 clock-names = "bus", "bus_a";
1104 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1105 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1108 mmssnoc: interconnect@fc478000 {
1109 reg = <0xfc478000 0x4000>;
1110 compatible = "qcom,msm8974-mmssnoc";
1111 #interconnect-cells = <1>;
1112 clock-names = "bus", "bus_a";
1113 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1114 <&mmcc MMSS_S0_AXI_CLK>;
1117 cnoc: interconnect@fc480000 {
1118 reg = <0xfc480000 0x4000>;
1119 compatible = "qcom,msm8974-cnoc";
1120 #interconnect-cells = <1>;
1121 clock-names = "bus", "bus_a";
1122 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1123 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1126 tsens: thermal-sensor@fc4a9000 {
1127 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1128 reg = <0xfc4a9000 0x1000>, /* TM */
1129 <0xfc4a8000 0x1000>; /* SROT */
1130 nvmem-cells = <&tsens_mode>,
1131 <&tsens_base1>, <&tsens_base2>,
1132 <&tsens_use_backup>,
1133 <&tsens_mode_backup>,
1134 <&tsens_base1_backup>, <&tsens_base2_backup>,
1135 <&tsens_s0_p1>, <&tsens_s0_p2>,
1136 <&tsens_s1_p1>, <&tsens_s1_p2>,
1137 <&tsens_s2_p1>, <&tsens_s2_p2>,
1138 <&tsens_s3_p1>, <&tsens_s3_p2>,
1139 <&tsens_s4_p1>, <&tsens_s4_p2>,
1140 <&tsens_s5_p1>, <&tsens_s5_p2>,
1141 <&tsens_s6_p1>, <&tsens_s6_p2>,
1142 <&tsens_s7_p1>, <&tsens_s7_p2>,
1143 <&tsens_s8_p1>, <&tsens_s8_p2>,
1144 <&tsens_s9_p1>, <&tsens_s9_p2>,
1145 <&tsens_s10_p1>, <&tsens_s10_p2>,
1146 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
1147 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
1148 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
1149 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
1150 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
1151 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
1152 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
1153 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
1154 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
1155 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
1156 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
1157 nvmem-cell-names = "mode",
1161 "base1_backup", "base2_backup",
1173 "s0_p1_backup", "s0_p2_backup",
1174 "s1_p1_backup", "s1_p2_backup",
1175 "s2_p1_backup", "s2_p2_backup",
1176 "s3_p1_backup", "s3_p2_backup",
1177 "s4_p1_backup", "s4_p2_backup",
1178 "s5_p1_backup", "s5_p2_backup",
1179 "s6_p1_backup", "s6_p2_backup",
1180 "s7_p1_backup", "s7_p2_backup",
1181 "s8_p1_backup", "s8_p2_backup",
1182 "s9_p1_backup", "s9_p2_backup",
1183 "s10_p1_backup", "s10_p2_backup";
1184 #qcom,sensors = <11>;
1185 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1186 interrupt-names = "uplow";
1187 #thermal-sensor-cells = <1>;
1191 compatible = "qcom,pshold";
1192 reg = <0xfc4ab000 0x4>;
1195 qfprom: qfprom@fc4bc000 {
1196 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1197 reg = <0xfc4bc000 0x1000>;
1198 #address-cells = <1>;
1201 tsens_base1: base1@d0 {
1206 tsens_s0_p1: s0-p1@d1 {
1211 tsens_s1_p1: s1-p1@d2 {
1216 tsens_s2_p1: s2-p1@d2 {
1221 tsens_s3_p1: s3-p1@d3 {
1226 tsens_s4_p1: s4-p1@d4 {
1231 tsens_s5_p1: s5-p1@d4 {
1236 tsens_s6_p1: s6-p1@d5 {
1241 tsens_s7_p1: s7-p1@d6 {
1246 tsens_s8_p1: s8-p1@d7 {
1251 tsens_mode: mode@d7 {
1256 tsens_s9_p1: s9-p1@d8 {
1261 tsens_s10_p1: s10_p1@d8 {
1266 tsens_base2: base2@d9 {
1271 tsens_s0_p2: s0-p2@da {
1276 tsens_s1_p2: s1-p2@db {
1281 tsens_s2_p2: s2-p2@dc {
1286 tsens_s3_p2: s3-p2@dc {
1291 tsens_s4_p2: s4-p2@dd {
1296 tsens_s5_p2: s5-p2@de {
1301 tsens_s6_p2: s6-p2@df {
1306 tsens_s7_p2: s7-p2@e0 {
1311 tsens_s8_p2: s8-p2@e0 {
1316 tsens_s9_p2: s9-p2@e1 {
1321 tsens_s10_p2: s10_p2@e2 {
1326 tsens_s5_p2_backup: s5-p2_backup@e3 {
1331 tsens_mode_backup: mode_backup@e3 {
1336 tsens_s6_p2_backup: s6-p2_backup@e4 {
1341 tsens_s7_p2_backup: s7-p2_backup@e4 {
1346 tsens_s8_p2_backup: s8-p2_backup@e5 {
1351 tsens_s9_p2_backup: s9-p2_backup@e6 {
1356 tsens_s10_p2_backup: s10_p2_backup@e7 {
1361 tsens_base1_backup: base1_backup@440 {
1366 tsens_s0_p1_backup: s0-p1_backup@441 {
1371 tsens_s1_p1_backup: s1-p1_backup@442 {
1376 tsens_s2_p1_backup: s2-p1_backup@442 {
1381 tsens_s3_p1_backup: s3-p1_backup@443 {
1386 tsens_s4_p1_backup: s4-p1_backup@444 {
1391 tsens_s5_p1_backup: s5-p1_backup@444 {
1396 tsens_s6_p1_backup: s6-p1_backup@445 {
1401 tsens_s7_p1_backup: s7-p1_backup@446 {
1406 tsens_use_backup: use_backup@447 {
1411 tsens_s8_p1_backup: s8-p1_backup@448 {
1416 tsens_s9_p1_backup: s9-p1_backup@448 {
1421 tsens_s10_p1_backup: s10_p1_backup@449 {
1426 tsens_base2_backup: base2_backup@44a {
1431 tsens_s0_p2_backup: s0-p2_backup@44b {
1436 tsens_s1_p2_backup: s1-p2_backup@44c {
1441 tsens_s2_p2_backup: s2-p2_backup@44c {
1446 tsens_s3_p2_backup: s3-p2_backup@44d {
1451 tsens_s4_p2_backup: s4-p2_backup@44e {
1457 spmi_bus: spmi@fc4cf000 {
1458 compatible = "qcom,spmi-pmic-arb";
1459 reg-names = "core", "intr", "cnfg";
1460 reg = <0xfc4cf000 0x1000>,
1461 <0xfc4cb000 0x1000>,
1462 <0xfc4ca000 0x1000>;
1463 interrupt-names = "periph_irq";
1464 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1467 #address-cells = <2>;
1469 interrupt-controller;
1470 #interrupt-cells = <4>;
1473 bam_dmux_dma: dma-controller@fc834000 {
1474 compatible = "qcom,bam-v1.4.0";
1475 reg = <0xfc834000 0x7000>;
1476 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1482 qcom,powered-remotely;
1485 remoteproc_mss: remoteproc@fc880000 {
1486 compatible = "qcom,msm8974-mss-pil";
1487 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1488 reg-names = "qdsp6", "rmb";
1490 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1491 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1492 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1493 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1494 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1495 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1497 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1498 <&gcc GCC_MSS_CFG_AHB_CLK>,
1499 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1501 clock-names = "iface", "bus", "mem", "xo";
1503 resets = <&gcc GCC_MSS_RESTART>;
1504 reset-names = "mss_restart";
1506 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1508 qcom,smem-states = <&modem_smp2p_out 0>;
1509 qcom,smem-state-names = "stop";
1511 status = "disabled";
1514 memory-region = <&mba_region>;
1518 memory-region = <&mpss_region>;
1521 bam_dmux: bam-dmux {
1522 compatible = "qcom,bam-dmux";
1524 interrupt-parent = <&modem_smsm>;
1525 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1526 interrupt-names = "pc", "pc-ack";
1528 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1529 qcom,smem-state-names = "pc", "pc-ack";
1531 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1532 dma-names = "tx", "rx";
1536 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1538 qcom,ipc = <&apcs 8 12>;
1539 qcom,smd-edge = <0>;
1545 tcsr_mutex: hwlock@fd484000 {
1546 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1547 reg = <0xfd484000 0x2000>;
1548 #hwlock-cells = <1>;
1551 tcsr: syscon@fd4a0000 {
1552 compatible = "qcom,tcsr-msm8974", "syscon";
1553 reg = <0xfd4a0000 0x10000>;
1556 tlmm: pinctrl@fd510000 {
1557 compatible = "qcom,msm8974-pinctrl";
1558 reg = <0xfd510000 0x4000>;
1560 gpio-ranges = <&tlmm 0 0 146>;
1562 interrupt-controller;
1563 #interrupt-cells = <2>;
1564 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1566 sdc1_off: sdc1-off-state {
1570 drive-strength = <2>;
1576 drive-strength = <2>;
1582 drive-strength = <2>;
1586 sdc2_off: sdc2-off-state {
1590 drive-strength = <2>;
1596 drive-strength = <2>;
1602 drive-strength = <2>;
1609 drive-strength = <2>;
1613 blsp1_uart2_default: blsp1-uart2-default-state {
1616 function = "blsp_uart2";
1617 drive-strength = <2>;
1623 function = "blsp_uart2";
1624 drive-strength = <4>;
1629 blsp2_uart1_default: blsp2-uart1-default-state {
1631 pins = "gpio41", "gpio44";
1632 function = "blsp_uart7";
1633 drive-strength = <2>;
1638 pins = "gpio42", "gpio43";
1639 function = "blsp_uart7";
1640 drive-strength = <2>;
1645 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1646 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1648 drive-strength = <2>;
1652 blsp2_uart4_default: blsp2-uart4-default-state {
1654 pins = "gpio53", "gpio56";
1655 function = "blsp_uart10";
1656 drive-strength = <2>;
1661 pins = "gpio54", "gpio55";
1662 function = "blsp_uart10";
1663 drive-strength = <2>;
1668 blsp1_i2c1_default: blsp1-i2c1-default-state {
1669 pins = "gpio2", "gpio3";
1670 function = "blsp_i2c1";
1671 drive-strength = <2>;
1675 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1676 pins = "gpio2", "gpio3";
1677 function = "blsp_i2c1";
1678 drive-strength = <2>;
1682 blsp1_i2c2_default: blsp1-i2c2-default-state {
1683 pins = "gpio6", "gpio7";
1684 function = "blsp_i2c2";
1685 drive-strength = <2>;
1689 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1690 pins = "gpio6", "gpio7";
1691 function = "blsp_i2c2";
1692 drive-strength = <2>;
1696 blsp1_i2c3_default: blsp1-i2c3-default-state {
1697 pins = "gpio10", "gpio11";
1698 function = "blsp_i2c3";
1699 drive-strength = <2>;
1703 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1704 pins = "gpio10", "gpio11";
1705 function = "blsp_i2c3";
1706 drive-strength = <2>;
1710 /* BLSP1_I2C4 info is missing */
1712 /* BLSP1_I2C5 info is missing */
1714 blsp1_i2c6_default: blsp1-i2c6-default-state {
1715 pins = "gpio29", "gpio30";
1716 function = "blsp_i2c6";
1717 drive-strength = <2>;
1721 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1722 pins = "gpio29", "gpio30";
1723 function = "blsp_i2c6";
1724 drive-strength = <2>;
1727 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1729 /* BLSP2_I2C1 info is missing */
1731 blsp2_i2c2_default: blsp2-i2c2-default-state {
1732 pins = "gpio47", "gpio48";
1733 function = "blsp_i2c8";
1734 drive-strength = <2>;
1738 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1739 pins = "gpio47", "gpio48";
1740 function = "blsp_i2c8";
1741 drive-strength = <2>;
1745 /* BLSP2_I2C3 info is missing */
1747 /* BLSP2_I2C4 info is missing */
1749 blsp2_i2c5_default: blsp2-i2c5-default-state {
1750 pins = "gpio83", "gpio84";
1751 function = "blsp_i2c11";
1752 drive-strength = <2>;
1756 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1757 pins = "gpio83", "gpio84";
1758 function = "blsp_i2c11";
1759 drive-strength = <2>;
1763 blsp2_i2c6_default: blsp2-i2c6-default-state {
1764 pins = "gpio87", "gpio88";
1765 function = "blsp_i2c12";
1766 drive-strength = <2>;
1770 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1771 pins = "gpio87", "gpio88";
1772 function = "blsp_i2c12";
1773 drive-strength = <2>;
1777 cci_default: cci-default-state {
1778 cci_i2c0_default: cci-i2c0-default-pins {
1779 pins = "gpio19", "gpio20";
1780 function = "cci_i2c0";
1781 drive-strength = <2>;
1785 cci_i2c1_default: cci-i2c1-default-pins {
1786 pins = "gpio21", "gpio22";
1787 function = "cci_i2c1";
1788 drive-strength = <2>;
1793 cci_sleep: cci-sleep-state {
1794 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1795 pins = "gpio19", "gpio20";
1797 drive-strength = <2>;
1801 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1802 pins = "gpio21", "gpio22";
1804 drive-strength = <2>;
1809 spi8_default: spi8_default-state {
1812 function = "blsp_spi8";
1816 function = "blsp_spi8";
1820 function = "blsp_spi8";
1824 function = "blsp_spi8";
1829 mmcc: clock-controller@fd8c0000 {
1830 compatible = "qcom,mmcc-msm8974";
1833 #power-domain-cells = <1>;
1834 reg = <0xfd8c0000 0x6000>;
1835 clocks = <&xo_board>,
1836 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1839 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1861 mdss: display-subsystem@fd900000 {
1862 compatible = "qcom,mdss";
1863 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1864 reg-names = "mdss_phys", "vbif_phys";
1866 power-domains = <&mmcc MDSS_GDSC>;
1868 clocks = <&mmcc MDSS_AHB_CLK>,
1869 <&mmcc MDSS_AXI_CLK>,
1870 <&mmcc MDSS_VSYNC_CLK>;
1871 clock-names = "iface", "bus", "vsync";
1873 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1875 interrupt-controller;
1876 #interrupt-cells = <1>;
1878 status = "disabled";
1880 #address-cells = <1>;
1884 mdp: display-controller@fd900000 {
1885 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1886 reg = <0xfd900100 0x22000>;
1887 reg-names = "mdp_phys";
1889 interrupt-parent = <&mdss>;
1892 clocks = <&mmcc MDSS_AHB_CLK>,
1893 <&mmcc MDSS_AXI_CLK>,
1894 <&mmcc MDSS_MDP_CLK>,
1895 <&mmcc MDSS_VSYNC_CLK>;
1896 clock-names = "iface", "bus", "core", "vsync";
1898 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1899 interconnect-names = "mdp0-mem";
1902 #address-cells = <1>;
1907 mdp5_intf1_out: endpoint {
1908 remote-endpoint = <&mdss_dsi0_in>;
1914 mdp5_intf2_out: endpoint {
1915 remote-endpoint = <&mdss_dsi1_in>;
1921 mdss_dsi0: dsi@fd922800 {
1922 compatible = "qcom,msm8974-dsi-ctrl",
1923 "qcom,mdss-dsi-ctrl";
1924 reg = <0xfd922800 0x1f8>;
1925 reg-names = "dsi_ctrl";
1927 interrupt-parent = <&mdss>;
1930 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1931 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1933 clocks = <&mmcc MDSS_MDP_CLK>,
1934 <&mmcc MDSS_AHB_CLK>,
1935 <&mmcc MDSS_AXI_CLK>,
1936 <&mmcc MDSS_BYTE0_CLK>,
1937 <&mmcc MDSS_PCLK0_CLK>,
1938 <&mmcc MDSS_ESC0_CLK>,
1939 <&mmcc MMSS_MISC_AHB_CLK>;
1940 clock-names = "mdp_core",
1948 phys = <&mdss_dsi0_phy>;
1950 status = "disabled";
1952 #address-cells = <1>;
1956 #address-cells = <1>;
1961 mdss_dsi0_in: endpoint {
1962 remote-endpoint = <&mdp5_intf1_out>;
1968 mdss_dsi0_out: endpoint {
1974 mdss_dsi0_phy: phy@fd922a00 {
1975 compatible = "qcom,dsi-phy-28nm-hpm";
1976 reg = <0xfd922a00 0xd4>,
1979 reg-names = "dsi_pll",
1981 "dsi_phy_regulator";
1986 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1987 clock-names = "iface", "ref";
1989 status = "disabled";
1992 mdss_dsi1: dsi@fd922e00 {
1993 compatible = "qcom,msm8974-dsi-ctrl",
1994 "qcom,mdss-dsi-ctrl";
1995 reg = <0xfd922e00 0x1f8>;
1996 reg-names = "dsi_ctrl";
1998 interrupt-parent = <&mdss>;
2001 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2002 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2004 clocks = <&mmcc MDSS_MDP_CLK>,
2005 <&mmcc MDSS_AHB_CLK>,
2006 <&mmcc MDSS_AXI_CLK>,
2007 <&mmcc MDSS_BYTE1_CLK>,
2008 <&mmcc MDSS_PCLK1_CLK>,
2009 <&mmcc MDSS_ESC1_CLK>,
2010 <&mmcc MMSS_MISC_AHB_CLK>;
2011 clock-names = "mdp_core",
2019 phys = <&mdss_dsi1_phy>;
2021 status = "disabled";
2023 #address-cells = <1>;
2027 #address-cells = <1>;
2032 mdss_dsi1_in: endpoint {
2033 remote-endpoint = <&mdp5_intf2_out>;
2039 mdss_dsi1_out: endpoint {
2045 mdss_dsi1_phy: phy@fd923000 {
2046 compatible = "qcom,dsi-phy-28nm-hpm";
2047 reg = <0xfd923000 0xd4>,
2050 reg-names = "dsi_pll",
2052 "dsi_phy_regulator";
2057 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2058 clock-names = "iface", "ref";
2060 status = "disabled";
2065 compatible = "qcom,msm8974-cci";
2066 #address-cells = <1>;
2068 reg = <0xfda0c000 0x1000>;
2069 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
2070 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2071 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
2072 <&mmcc CAMSS_CCI_CCI_CLK>;
2073 clock-names = "camss_top_ahb",
2077 pinctrl-names = "default", "sleep";
2078 pinctrl-0 = <&cci_default>;
2079 pinctrl-1 = <&cci_sleep>;
2081 status = "disabled";
2083 cci_i2c0: i2c-bus@0 {
2085 clock-frequency = <100000>;
2086 #address-cells = <1>;
2090 cci_i2c1: i2c-bus@1 {
2092 clock-frequency = <100000>;
2093 #address-cells = <1>;
2098 gpu: adreno@fdb00000 {
2099 compatible = "qcom,adreno-330.1", "qcom,adreno";
2100 reg = <0xfdb00000 0x10000>;
2101 reg-names = "kgsl_3d0_reg_memory";
2103 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2104 interrupt-names = "kgsl_3d0_irq";
2106 clocks = <&mmcc OXILI_GFX3D_CLK>,
2107 <&mmcc OXILICX_AHB_CLK>,
2108 <&mmcc OXILICX_AXI_CLK>;
2109 clock-names = "core", "iface", "mem_iface";
2112 power-domains = <&mmcc OXILICX_GDSC>;
2113 operating-points-v2 = <&gpu_opp_table>;
2115 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
2116 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
2117 interconnect-names = "gfx-mem", "ocmem";
2119 // iommus = <&gpu_iommu 0>;
2121 status = "disabled";
2123 gpu_opp_table: opp-table {
2124 compatible = "operating-points-v2";
2127 opp-hz = /bits/ 64 <320000000>;
2131 opp-hz = /bits/ 64 <200000000>;
2135 opp-hz = /bits/ 64 <27000000>;
2141 compatible = "qcom,msm8974-ocmem";
2142 reg = <0xfdd00000 0x2000>,
2143 <0xfec00000 0x180000>;
2144 reg-names = "ctrl", "mem";
2145 ranges = <0 0xfec00000 0x180000>;
2146 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
2147 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
2148 clock-names = "core", "iface";
2150 #address-cells = <1>;
2153 gmu_sram: gmu-sram@0 {
2154 reg = <0x0 0x100000>;
2158 remoteproc_adsp: remoteproc@fe200000 {
2159 compatible = "qcom,msm8974-adsp-pil";
2160 reg = <0xfe200000 0x100>;
2162 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2163 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2164 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2165 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2166 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2167 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2169 clocks = <&xo_board>;
2172 memory-region = <&adsp_region>;
2174 qcom,smem-states = <&adsp_smp2p_out 0>;
2175 qcom,smem-state-names = "stop";
2177 status = "disabled";
2180 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2182 qcom,ipc = <&apcs 8 8>;
2183 qcom,smd-edge = <1>;
2188 imem: sram@fe805000 {
2189 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2190 reg = <0xfe805000 0x1000>;
2193 compatible = "syscon-reboot-mode";
2201 polling-delay-passive = <250>;
2202 polling-delay = <1000>;
2204 thermal-sensors = <&tsens 5>;
2208 temperature = <75000>;
2209 hysteresis = <2000>;
2213 temperature = <110000>;
2214 hysteresis = <2000>;
2221 polling-delay-passive = <250>;
2222 polling-delay = <1000>;
2224 thermal-sensors = <&tsens 6>;
2228 temperature = <75000>;
2229 hysteresis = <2000>;
2233 temperature = <110000>;
2234 hysteresis = <2000>;
2241 polling-delay-passive = <250>;
2242 polling-delay = <1000>;
2244 thermal-sensors = <&tsens 7>;
2248 temperature = <75000>;
2249 hysteresis = <2000>;
2253 temperature = <110000>;
2254 hysteresis = <2000>;
2261 polling-delay-passive = <250>;
2262 polling-delay = <1000>;
2264 thermal-sensors = <&tsens 8>;
2268 temperature = <75000>;
2269 hysteresis = <2000>;
2273 temperature = <110000>;
2274 hysteresis = <2000>;
2281 polling-delay-passive = <250>;
2282 polling-delay = <1000>;
2284 thermal-sensors = <&tsens 1>;
2287 q6_dsp_alert0: trip-point0 {
2288 temperature = <90000>;
2289 hysteresis = <2000>;
2296 polling-delay-passive = <250>;
2297 polling-delay = <1000>;
2299 thermal-sensors = <&tsens 2>;
2302 modemtx_alert0: trip-point0 {
2303 temperature = <90000>;
2304 hysteresis = <2000>;
2311 polling-delay-passive = <250>;
2312 polling-delay = <1000>;
2314 thermal-sensors = <&tsens 3>;
2317 video_alert0: trip-point0 {
2318 temperature = <95000>;
2319 hysteresis = <2000>;
2326 polling-delay-passive = <250>;
2327 polling-delay = <1000>;
2329 thermal-sensors = <&tsens 4>;
2332 wlan_alert0: trip-point0 {
2333 temperature = <105000>;
2334 hysteresis = <2000>;
2341 polling-delay-passive = <250>;
2342 polling-delay = <1000>;
2344 thermal-sensors = <&tsens 9>;
2347 gpu1_alert0: trip-point0 {
2348 temperature = <90000>;
2349 hysteresis = <2000>;
2355 gpu-bottom-thermal {
2356 polling-delay-passive = <250>;
2357 polling-delay = <1000>;
2359 thermal-sensors = <&tsens 10>;
2362 gpu2_alert0: trip-point0 {
2363 temperature = <90000>;
2364 hysteresis = <2000>;
2372 compatible = "arm,armv7-timer";
2373 interrupts = <GIC_PPI 2 0xf08>,
2377 clock-frequency = <19200000>;
2380 vreg_boost: vreg-boost {
2381 compatible = "regulator-fixed";
2383 regulator-name = "vreg-boost";
2384 regulator-min-microvolt = <3150000>;
2385 regulator-max-microvolt = <3150000>;
2387 regulator-always-on;
2390 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
2393 pinctrl-names = "default";
2394 pinctrl-0 = <&boost_bypass_n_pin>;
2397 vreg_vph_pwr: vreg-vph-pwr {
2398 compatible = "regulator-fixed";
2399 regulator-name = "vph-pwr";
2401 regulator-min-microvolt = <3600000>;
2402 regulator-max-microvolt = <3600000>;
2404 regulator-always-on;