arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 500000  880000
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52                         /* cooling options */
  53                         cooling-min-level = <0>;
  54                         cooling-max-level = <2>;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                 };
  57                 cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x1>;
  61                 };
  62         };
  63
  64         thermal-zones {
  65                 #include "omap4-cpu-thermal.dtsi"
  66                 #include "omap5-gpu-thermal.dtsi"
  67                 #include "omap5-core-thermal.dtsi"
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 /* PPI secure/nonsecure IRQ */
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  77         };
  78
  79         gic: interrupt-controller@48211000 {
  80                 compatible = "arm,cortex-a15-gic";
  81                 interrupt-controller;
  82                 #interrupt-cells = <3>;
  83                 reg = <0x48211000 0x1000>,
  84                       <0x48212000 0x1000>,
  85                       <0x48214000 0x2000>,
  86                       <0x48216000 0x2000>;
  87         };
  88
  89         /*
  90          * The soc node represents the soc top level view. It is uses for IPs
  91          * that are not memory mapped in the MPU view or for the MPU itself.
  92          */
  93         soc {
  94                 compatible = "ti,omap-infra";
  95                 mpu {
  96                         compatible = "ti,omap5-mpu";
  97                         ti,hwmods = "mpu";
  98                 };
  99         };
 100
 101         /*
 102          * XXX: Use a flat representation of the OMAP3 interconnect.
 103          * The real OMAP interconnect network is quite complex.
 104          * Since that will not bring real advantage to represent that in DT for
 105          * the moment, just use a fake OCP bus entry to represent the whole bus
 106          * hierarchy.
 107          */
 108         ocp {
 109                 compatible = "ti,omap4-l3-noc", "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges;
 113                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 114                 reg = <0x44000000 0x2000>,
 115                       <0x44800000 0x3000>,
 116                       <0x45000000 0x4000>;
 117                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 119
 120                 prm: prm@4ae06000 {
 121                         compatible = "ti,omap5-prm";
 122                         reg = <0x4ae06000 0x3000>;
 123
 124                         prm_clocks: clocks {
 125                                 #address-cells = <1>;
 126                                 #size-cells = <0>;
 127                         };
 128
 129                         prm_clockdomains: clockdomains {
 130                         };
 131                 };
 132
 133                 cm_core_aon: cm_core_aon@4a004000 {
 134                         compatible = "ti,omap5-cm-core-aon";
 135                         reg = <0x4a004000 0x2000>;
 136
 137                         cm_core_aon_clocks: clocks {
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140                         };
 141
 142                         cm_core_aon_clockdomains: clockdomains {
 143                         };
 144                 };
 145
 146                 scrm: scrm@4ae0a000 {
 147                         compatible = "ti,omap5-scrm";
 148                         reg = <0x4ae0a000 0x2000>;
 149
 150                         scrm_clocks: clocks {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153                         };
 154
 155                         scrm_clockdomains: clockdomains {
 156                         };
 157                 };
 158
 159                 cm_core: cm_core@4a008000 {
 160                         compatible = "ti,omap5-cm-core";
 161                         reg = <0x4a008000 0x3000>;
 162
 163                         cm_core_clocks: clocks {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                         };
 167
 168                         cm_core_clockdomains: clockdomains {
 169                         };
 170                 };
 171
 172                 counter32k: counter@4ae04000 {
 173                         compatible = "ti,omap-counter32k";
 174                         reg = <0x4ae04000 0x40>;
 175                         ti,hwmods = "counter_32k";
 176                 };
 177
 178                 omap5_pmx_core: pinmux@4a002840 {
 179                         compatible = "ti,omap4-padconf", "pinctrl-single";
 180                         reg = <0x4a002840 0x01b6>;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         pinctrl-single,register-width = <16>;
 184                         pinctrl-single,function-mask = <0x7fff>;
 185                 };
 186                 omap5_pmx_wkup: pinmux@4ae0c840 {
 187                         compatible = "ti,omap4-padconf", "pinctrl-single";
 188                         reg = <0x4ae0c840 0x0038>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         pinctrl-single,register-width = <16>;
 192                         pinctrl-single,function-mask = <0x7fff>;
 193                 };
 194
 195                 omap5_padconf_global: tisyscon@4a002da0 {
 196                         compatible = "syscon";
 197                         reg = <0x4A002da0 0xec>;
 198                 };
 199
 200                 pbias_regulator: pbias_regulator {
 201                         compatible = "ti,pbias-omap";
 202                         reg = <0x60 0x4>;
 203                         syscon = <&omap5_padconf_global>;
 204                         pbias_mmc_reg: pbias_mmc_omap5 {
 205                                 regulator-name = "pbias_mmc_omap5";
 206                                 regulator-min-microvolt = <1800000>;
 207                                 regulator-max-microvolt = <3000000>;
 208                         };
 209                 };
 210
 211                 sdma: dma-controller@4a056000 {
 212                         compatible = "ti,omap4430-sdma";
 213                         reg = <0x4a056000 0x1000>;
 214                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 218                         #dma-cells = <1>;
 219                         #dma-channels = <32>;
 220                         #dma-requests = <127>;
 221                 };
 222
 223                 gpio1: gpio@4ae10000 {
 224                         compatible = "ti,omap4-gpio";
 225                         reg = <0x4ae10000 0x200>;
 226                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 227                         ti,hwmods = "gpio1";
 228                         ti,gpio-always-on;
 229                         gpio-controller;
 230                         #gpio-cells = <2>;
 231                         interrupt-controller;
 232                         #interrupt-cells = <2>;
 233                 };
 234
 235                 gpio2: gpio@48055000 {
 236                         compatible = "ti,omap4-gpio";
 237                         reg = <0x48055000 0x200>;
 238                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 239                         ti,hwmods = "gpio2";
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 gpio3: gpio@48057000 {
 247                         compatible = "ti,omap4-gpio";
 248                         reg = <0x48057000 0x200>;
 249                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 250                         ti,hwmods = "gpio3";
 251                         gpio-controller;
 252                         #gpio-cells = <2>;
 253                         interrupt-controller;
 254                         #interrupt-cells = <2>;
 255                 };
 256
 257                 gpio4: gpio@48059000 {
 258                         compatible = "ti,omap4-gpio";
 259                         reg = <0x48059000 0x200>;
 260                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 261                         ti,hwmods = "gpio4";
 262                         gpio-controller;
 263                         #gpio-cells = <2>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <2>;
 266                 };
 267
 268                 gpio5: gpio@4805b000 {
 269                         compatible = "ti,omap4-gpio";
 270                         reg = <0x4805b000 0x200>;
 271                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 272                         ti,hwmods = "gpio5";
 273                         gpio-controller;
 274                         #gpio-cells = <2>;
 275                         interrupt-controller;
 276                         #interrupt-cells = <2>;
 277                 };
 278
 279                 gpio6: gpio@4805d000 {
 280                         compatible = "ti,omap4-gpio";
 281                         reg = <0x4805d000 0x200>;
 282                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 283                         ti,hwmods = "gpio6";
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                 };
 289
 290                 gpio7: gpio@48051000 {
 291                         compatible = "ti,omap4-gpio";
 292                         reg = <0x48051000 0x200>;
 293                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 294                         ti,hwmods = "gpio7";
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 gpio8: gpio@48053000 {
 302                         compatible = "ti,omap4-gpio";
 303                         reg = <0x48053000 0x200>;
 304                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 305                         ti,hwmods = "gpio8";
 306                         gpio-controller;
 307                         #gpio-cells = <2>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                 };
 311
 312                 gpmc: gpmc@50000000 {
 313                         compatible = "ti,omap4430-gpmc";
 314                         reg = <0x50000000 0x1000>;
 315                         #address-cells = <2>;
 316                         #size-cells = <1>;
 317                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 318                         gpmc,num-cs = <8>;
 319                         gpmc,num-waitpins = <4>;
 320                         ti,hwmods = "gpmc";
 321                 };
 322
 323                 i2c1: i2c@48070000 {
 324                         compatible = "ti,omap4-i2c";
 325                         reg = <0x48070000 0x100>;
 326                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         ti,hwmods = "i2c1";
 330                 };
 331
 332                 i2c2: i2c@48072000 {
 333                         compatible = "ti,omap4-i2c";
 334                         reg = <0x48072000 0x100>;
 335                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338                         ti,hwmods = "i2c2";
 339                 };
 340
 341                 i2c3: i2c@48060000 {
 342                         compatible = "ti,omap4-i2c";
 343                         reg = <0x48060000 0x100>;
 344                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         ti,hwmods = "i2c3";
 348                 };
 349
 350                 i2c4: i2c@4807a000 {
 351                         compatible = "ti,omap4-i2c";
 352                         reg = <0x4807a000 0x100>;
 353                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         ti,hwmods = "i2c4";
 357                 };
 358
 359                 i2c5: i2c@4807c000 {
 360                         compatible = "ti,omap4-i2c";
 361                         reg = <0x4807c000 0x100>;
 362                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         ti,hwmods = "i2c5";
 366                 };
 367
 368                 hwspinlock: spinlock@4a0f6000 {
 369                         compatible = "ti,omap4-hwspinlock";
 370                         reg = <0x4a0f6000 0x1000>;
 371                         ti,hwmods = "spinlock";
 372                 };
 373
 374                 mcspi1: spi@48098000 {
 375                         compatible = "ti,omap4-mcspi";
 376                         reg = <0x48098000 0x200>;
 377                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         ti,hwmods = "mcspi1";
 381                         ti,spi-num-cs = <4>;
 382                         dmas = <&sdma 35>,
 383                                <&sdma 36>,
 384                                <&sdma 37>,
 385                                <&sdma 38>,
 386                                <&sdma 39>,
 387                                <&sdma 40>,
 388                                <&sdma 41>,
 389                                <&sdma 42>;
 390                         dma-names = "tx0", "rx0", "tx1", "rx1",
 391                                     "tx2", "rx2", "tx3", "rx3";
 392                 };
 393
 394                 mcspi2: spi@4809a000 {
 395                         compatible = "ti,omap4-mcspi";
 396                         reg = <0x4809a000 0x200>;
 397                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         ti,hwmods = "mcspi2";
 401                         ti,spi-num-cs = <2>;
 402                         dmas = <&sdma 43>,
 403                                <&sdma 44>,
 404                                <&sdma 45>,
 405                                <&sdma 46>;
 406                         dma-names = "tx0", "rx0", "tx1", "rx1";
 407                 };
 408
 409                 mcspi3: spi@480b8000 {
 410                         compatible = "ti,omap4-mcspi";
 411                         reg = <0x480b8000 0x200>;
 412                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         ti,hwmods = "mcspi3";
 416                         ti,spi-num-cs = <2>;
 417                         dmas = <&sdma 15>, <&sdma 16>;
 418                         dma-names = "tx0", "rx0";
 419                 };
 420
 421                 mcspi4: spi@480ba000 {
 422                         compatible = "ti,omap4-mcspi";
 423                         reg = <0x480ba000 0x200>;
 424                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         ti,hwmods = "mcspi4";
 428                         ti,spi-num-cs = <1>;
 429                         dmas = <&sdma 70>, <&sdma 71>;
 430                         dma-names = "tx0", "rx0";
 431                 };
 432
 433                 uart1: serial@4806a000 {
 434                         compatible = "ti,omap4-uart";
 435                         reg = <0x4806a000 0x100>;
 436                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 437                         ti,hwmods = "uart1";
 438                         clock-frequency = <48000000>;
 439                 };
 440
 441                 uart2: serial@4806c000 {
 442                         compatible = "ti,omap4-uart";
 443                         reg = <0x4806c000 0x100>;
 444                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 445                         ti,hwmods = "uart2";
 446                         clock-frequency = <48000000>;
 447                 };
 448
 449                 uart3: serial@48020000 {
 450                         compatible = "ti,omap4-uart";
 451                         reg = <0x48020000 0x100>;
 452                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 453                         ti,hwmods = "uart3";
 454                         clock-frequency = <48000000>;
 455                 };
 456
 457                 uart4: serial@4806e000 {
 458                         compatible = "ti,omap4-uart";
 459                         reg = <0x4806e000 0x100>;
 460                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 461                         ti,hwmods = "uart4";
 462                         clock-frequency = <48000000>;
 463                 };
 464
 465                 uart5: serial@48066000 {
 466                         compatible = "ti,omap4-uart";
 467                         reg = <0x48066000 0x100>;
 468                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 469                         ti,hwmods = "uart5";
 470                         clock-frequency = <48000000>;
 471                 };
 472
 473                 uart6: serial@48068000 {
 474                         compatible = "ti,omap4-uart";
 475                         reg = <0x48068000 0x100>;
 476                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 477                         ti,hwmods = "uart6";
 478                         clock-frequency = <48000000>;
 479                 };
 480
 481                 mmc1: mmc@4809c000 {
 482                         compatible = "ti,omap4-hsmmc";
 483                         reg = <0x4809c000 0x400>;
 484                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 485                         ti,hwmods = "mmc1";
 486                         ti,dual-volt;
 487                         ti,needs-special-reset;
 488                         dmas = <&sdma 61>, <&sdma 62>;
 489                         dma-names = "tx", "rx";
 490                         pbias-supply = <&pbias_mmc_reg>;
 491                 };
 492
 493                 mmc2: mmc@480b4000 {
 494                         compatible = "ti,omap4-hsmmc";
 495                         reg = <0x480b4000 0x400>;
 496                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 497                         ti,hwmods = "mmc2";
 498                         ti,needs-special-reset;
 499                         dmas = <&sdma 47>, <&sdma 48>;
 500                         dma-names = "tx", "rx";
 501                 };
 502
 503                 mmc3: mmc@480ad000 {
 504                         compatible = "ti,omap4-hsmmc";
 505                         reg = <0x480ad000 0x400>;
 506                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 507                         ti,hwmods = "mmc3";
 508                         ti,needs-special-reset;
 509                         dmas = <&sdma 77>, <&sdma 78>;
 510                         dma-names = "tx", "rx";
 511                 };
 512
 513                 mmc4: mmc@480d1000 {
 514                         compatible = "ti,omap4-hsmmc";
 515                         reg = <0x480d1000 0x400>;
 516                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 517                         ti,hwmods = "mmc4";
 518                         ti,needs-special-reset;
 519                         dmas = <&sdma 57>, <&sdma 58>;
 520                         dma-names = "tx", "rx";
 521                 };
 522
 523                 mmc5: mmc@480d5000 {
 524                         compatible = "ti,omap4-hsmmc";
 525                         reg = <0x480d5000 0x400>;
 526                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 527                         ti,hwmods = "mmc5";
 528                         ti,needs-special-reset;
 529                         dmas = <&sdma 59>, <&sdma 60>;
 530                         dma-names = "tx", "rx";
 531                 };
 532
 533                 keypad: keypad@4ae1c000 {
 534                         compatible = "ti,omap4-keypad";
 535                         reg = <0x4ae1c000 0x400>;
 536                         ti,hwmods = "kbd";
 537                 };
 538
 539                 mcpdm: mcpdm@40132000 {
 540                         compatible = "ti,omap4-mcpdm";
 541                         reg = <0x40132000 0x7f>, /* MPU private access */
 542                               <0x49032000 0x7f>; /* L3 Interconnect */
 543                         reg-names = "mpu", "dma";
 544                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 545                         ti,hwmods = "mcpdm";
 546                         dmas = <&sdma 65>,
 547                                <&sdma 66>;
 548                         dma-names = "up_link", "dn_link";
 549                 };
 550
 551                 dmic: dmic@4012e000 {
 552                         compatible = "ti,omap4-dmic";
 553                         reg = <0x4012e000 0x7f>, /* MPU private access */
 554                               <0x4902e000 0x7f>; /* L3 Interconnect */
 555                         reg-names = "mpu", "dma";
 556                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 557                         ti,hwmods = "dmic";
 558                         dmas = <&sdma 67>;
 559                         dma-names = "up_link";
 560                 };
 561
 562                 mcbsp1: mcbsp@40122000 {
 563                         compatible = "ti,omap4-mcbsp";
 564                         reg = <0x40122000 0xff>, /* MPU private access */
 565                               <0x49022000 0xff>; /* L3 Interconnect */
 566                         reg-names = "mpu", "dma";
 567                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 568                         interrupt-names = "common";
 569                         ti,buffer-size = <128>;
 570                         ti,hwmods = "mcbsp1";
 571                         dmas = <&sdma 33>,
 572                                <&sdma 34>;
 573                         dma-names = "tx", "rx";
 574                 };
 575
 576                 mcbsp2: mcbsp@40124000 {
 577                         compatible = "ti,omap4-mcbsp";
 578                         reg = <0x40124000 0xff>, /* MPU private access */
 579                               <0x49024000 0xff>; /* L3 Interconnect */
 580                         reg-names = "mpu", "dma";
 581                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 582                         interrupt-names = "common";
 583                         ti,buffer-size = <128>;
 584                         ti,hwmods = "mcbsp2";
 585                         dmas = <&sdma 17>,
 586                                <&sdma 18>;
 587                         dma-names = "tx", "rx";
 588                 };
 589
 590                 mcbsp3: mcbsp@40126000 {
 591                         compatible = "ti,omap4-mcbsp";
 592                         reg = <0x40126000 0xff>, /* MPU private access */
 593                               <0x49026000 0xff>; /* L3 Interconnect */
 594                         reg-names = "mpu", "dma";
 595                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 596                         interrupt-names = "common";
 597                         ti,buffer-size = <128>;
 598                         ti,hwmods = "mcbsp3";
 599                         dmas = <&sdma 19>,
 600                                <&sdma 20>;
 601                         dma-names = "tx", "rx";
 602                 };
 603
 604                 timer1: timer@4ae18000 {
 605                         compatible = "ti,omap5430-timer";
 606                         reg = <0x4ae18000 0x80>;
 607                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 608                         ti,hwmods = "timer1";
 609                         ti,timer-alwon;
 610                 };
 611
 612                 timer2: timer@48032000 {
 613                         compatible = "ti,omap5430-timer";
 614                         reg = <0x48032000 0x80>;
 615                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 616                         ti,hwmods = "timer2";
 617                 };
 618
 619                 timer3: timer@48034000 {
 620                         compatible = "ti,omap5430-timer";
 621                         reg = <0x48034000 0x80>;
 622                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "timer3";
 624                 };
 625
 626                 timer4: timer@48036000 {
 627                         compatible = "ti,omap5430-timer";
 628                         reg = <0x48036000 0x80>;
 629                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 630                         ti,hwmods = "timer4";
 631                 };
 632
 633                 timer5: timer@40138000 {
 634                         compatible = "ti,omap5430-timer";
 635                         reg = <0x40138000 0x80>,
 636                               <0x49038000 0x80>;
 637                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 638                         ti,hwmods = "timer5";
 639                         ti,timer-dsp;
 640                         ti,timer-pwm;
 641                 };
 642
 643                 timer6: timer@4013a000 {
 644                         compatible = "ti,omap5430-timer";
 645                         reg = <0x4013a000 0x80>,
 646                               <0x4903a000 0x80>;
 647                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 648                         ti,hwmods = "timer6";
 649                         ti,timer-dsp;
 650                         ti,timer-pwm;
 651                 };
 652
 653                 timer7: timer@4013c000 {
 654                         compatible = "ti,omap5430-timer";
 655                         reg = <0x4013c000 0x80>,
 656                               <0x4903c000 0x80>;
 657                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "timer7";
 659                         ti,timer-dsp;
 660                 };
 661
 662                 timer8: timer@4013e000 {
 663                         compatible = "ti,omap5430-timer";
 664                         reg = <0x4013e000 0x80>,
 665                               <0x4903e000 0x80>;
 666                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 667                         ti,hwmods = "timer8";
 668                         ti,timer-dsp;
 669                         ti,timer-pwm;
 670                 };
 671
 672                 timer9: timer@4803e000 {
 673                         compatible = "ti,omap5430-timer";
 674                         reg = <0x4803e000 0x80>;
 675                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 676                         ti,hwmods = "timer9";
 677                         ti,timer-pwm;
 678                 };
 679
 680                 timer10: timer@48086000 {
 681                         compatible = "ti,omap5430-timer";
 682                         reg = <0x48086000 0x80>;
 683                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 684                         ti,hwmods = "timer10";
 685                         ti,timer-pwm;
 686                 };
 687
 688                 timer11: timer@48088000 {
 689                         compatible = "ti,omap5430-timer";
 690                         reg = <0x48088000 0x80>;
 691                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 692                         ti,hwmods = "timer11";
 693                         ti,timer-pwm;
 694                 };
 695
 696                 wdt2: wdt@4ae14000 {
 697                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 698                         reg = <0x4ae14000 0x80>;
 699                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 700                         ti,hwmods = "wd_timer2";
 701                 };
 702
 703                 emif1: emif@4c000000 {
 704                         compatible      = "ti,emif-4d5";
 705                         ti,hwmods       = "emif1";
 706                         ti,no-idle-on-init;
 707                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 708                         reg = <0x4c000000 0x400>;
 709                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 710                         hw-caps-read-idle-ctrl;
 711                         hw-caps-ll-interface;
 712                         hw-caps-temp-alert;
 713                 };
 714
 715                 emif2: emif@4d000000 {
 716                         compatible      = "ti,emif-4d5";
 717                         ti,hwmods       = "emif2";
 718                         ti,no-idle-on-init;
 719                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 720                         reg = <0x4d000000 0x400>;
 721                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 722                         hw-caps-read-idle-ctrl;
 723                         hw-caps-ll-interface;
 724                         hw-caps-temp-alert;
 725                 };
 726
 727                 omap_control_usb2phy: control-phy@4a002300 {
 728                         compatible = "ti,control-phy-usb2";
 729                         reg = <0x4a002300 0x4>;
 730                         reg-names = "power";
 731                 };
 732
 733                 omap_control_usb3phy: control-phy@4a002370 {
 734                         compatible = "ti,control-phy-pipe3";
 735                         reg = <0x4a002370 0x4>;
 736                         reg-names = "power";
 737                 };
 738
 739                 usb3: omap_dwc3@4a020000 {
 740                         compatible = "ti,dwc3";
 741                         ti,hwmods = "usb_otg_ss";
 742                         reg = <0x4a020000 0x10000>;
 743                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 744                         #address-cells = <1>;
 745                         #size-cells = <1>;
 746                         utmi-mode = <2>;
 747                         ranges;
 748                         dwc3@4a030000 {
 749                                 compatible = "snps,dwc3";
 750                                 reg = <0x4a030000 0x10000>;
 751                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 752                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
 753                                 dr_mode = "peripheral";
 754                                 tx-fifo-resize;
 755                         };
 756                 };
 757
 758                 ocp2scp@4a080000 {
 759                         compatible = "ti,omap-ocp2scp";
 760                         #address-cells = <1>;
 761                         #size-cells = <1>;
 762                         reg = <0x4a080000 0x20>;
 763                         ranges;
 764                         ti,hwmods = "ocp2scp1";
 765                         usb2_phy: usb2phy@4a084000 {
 766                                 compatible = "ti,omap-usb2";
 767                                 reg = <0x4a084000 0x7c>;
 768                                 ctrl-module = <&omap_control_usb2phy>;
 769                         };
 770
 771                         usb3_phy: usb3phy@4a084400 {
 772                                 compatible = "ti,omap-usb3";
 773                                 reg = <0x4a084400 0x80>,
 774                                       <0x4a084800 0x64>,
 775                                       <0x4a084c00 0x40>;
 776                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 777                                 ctrl-module = <&omap_control_usb3phy>;
 778                         };
 779                 };
 780
 781                 usbhstll: usbhstll@4a062000 {
 782                         compatible = "ti,usbhs-tll";
 783                         reg = <0x4a062000 0x1000>;
 784                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 785                         ti,hwmods = "usb_tll_hs";
 786                 };
 787
 788                 usbhshost: usbhshost@4a064000 {
 789                         compatible = "ti,usbhs-host";
 790                         reg = <0x4a064000 0x800>;
 791                         ti,hwmods = "usb_host_hs";
 792                         #address-cells = <1>;
 793                         #size-cells = <1>;
 794                         ranges;
 795
 796                         usbhsohci: ohci@4a064800 {
 797                                 compatible = "ti,ohci-omap3", "usb-ohci";
 798                                 reg = <0x4a064800 0x400>;
 799                                 interrupt-parent = <&gic>;
 800                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 801                         };
 802
 803                         usbhsehci: ehci@4a064c00 {
 804                                 compatible = "ti,ehci-omap", "usb-ehci";
 805                                 reg = <0x4a064c00 0x400>;
 806                                 interrupt-parent = <&gic>;
 807                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 808                         };
 809                 };
 810
 811                 bandgap: bandgap@4a0021e0 {
 812                         reg = <0x4a0021e0 0xc
 813                                0x4a00232c 0xc
 814                                0x4a002380 0x2c
 815                                0x4a0023C0 0x3c>;
 816                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 817                         compatible = "ti,omap5430-bandgap";
 818
 819                         #thermal-sensor-cells = <1>;
 820                 };
 821         };
 822 };
 823
 824 /include/ "omap54xx-clocks.dtsi"