2 * Device Tree Source for OMAP3 clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 virt_16_8m_ck: virt_16_8m_ck {
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
17 osc_sys_ck: osc_sys_ck {
19 compatible = "ti,mux-clock";
20 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
26 compatible = "ti,divider-clock";
27 clocks = <&osc_sys_ck>;
31 ti,index-starts-at-one;
34 sys_clkout1: sys_clkout1 {
36 compatible = "ti,gate-clock";
37 clocks = <&osc_sys_ck>;
42 dpll3_x2_ck: dpll3_x2_ck {
44 compatible = "fixed-factor-clock";
50 dpll3_m2x2_ck: dpll3_m2x2_ck {
52 compatible = "fixed-factor-clock";
53 clocks = <&dpll3_m2_ck>;
58 dpll4_x2_ck: dpll4_x2_ck {
60 compatible = "fixed-factor-clock";
66 corex2_fck: corex2_fck {
68 compatible = "fixed-factor-clock";
69 clocks = <&dpll3_m2x2_ck>;
74 wkup_l4_ick: wkup_l4_ick {
76 compatible = "fixed-factor-clock";
83 mcbsp5_mux_fck: mcbsp5_mux_fck {
85 compatible = "ti,composite-mux-clock";
86 clocks = <&core_96m_fck>, <&mcbsp_clks>;
91 mcbsp5_fck: mcbsp5_fck {
93 compatible = "ti,composite-clock";
94 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
97 mcbsp1_mux_fck: mcbsp1_mux_fck {
99 compatible = "ti,composite-mux-clock";
100 clocks = <&core_96m_fck>, <&mcbsp_clks>;
105 mcbsp1_fck: mcbsp1_fck {
107 compatible = "ti,composite-clock";
108 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
111 mcbsp2_mux_fck: mcbsp2_mux_fck {
113 compatible = "ti,composite-mux-clock";
114 clocks = <&per_96m_fck>, <&mcbsp_clks>;
119 mcbsp2_fck: mcbsp2_fck {
121 compatible = "ti,composite-clock";
122 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
125 mcbsp3_mux_fck: mcbsp3_mux_fck {
127 compatible = "ti,composite-mux-clock";
128 clocks = <&per_96m_fck>, <&mcbsp_clks>;
132 mcbsp3_fck: mcbsp3_fck {
134 compatible = "ti,composite-clock";
135 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
138 mcbsp4_mux_fck: mcbsp4_mux_fck {
140 compatible = "ti,composite-mux-clock";
141 clocks = <&per_96m_fck>, <&mcbsp_clks>;
146 mcbsp4_fck: mcbsp4_fck {
148 compatible = "ti,composite-clock";
149 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
153 dummy_apb_pclk: dummy_apb_pclk {
155 compatible = "fixed-clock";
156 clock-frequency = <0x0>;
159 omap_32k_fck: omap_32k_fck {
161 compatible = "fixed-clock";
162 clock-frequency = <32768>;
165 virt_12m_ck: virt_12m_ck {
167 compatible = "fixed-clock";
168 clock-frequency = <12000000>;
171 virt_13m_ck: virt_13m_ck {
173 compatible = "fixed-clock";
174 clock-frequency = <13000000>;
177 virt_19200000_ck: virt_19200000_ck {
179 compatible = "fixed-clock";
180 clock-frequency = <19200000>;
183 virt_26000000_ck: virt_26000000_ck {
185 compatible = "fixed-clock";
186 clock-frequency = <26000000>;
189 virt_38_4m_ck: virt_38_4m_ck {
191 compatible = "fixed-clock";
192 clock-frequency = <38400000>;
197 compatible = "ti,omap3-dpll-per-clock";
198 clocks = <&sys_ck>, <&sys_ck>;
199 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
202 dpll4_m2_ck: dpll4_m2_ck {
204 compatible = "ti,divider-clock";
205 clocks = <&dpll4_ck>;
208 ti,index-starts-at-one;
211 dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
213 compatible = "fixed-factor-clock";
214 clocks = <&dpll4_m2_ck>;
219 dpll4_m2x2_ck: dpll4_m2x2_ck {
221 compatible = "ti,gate-clock";
222 clocks = <&dpll4_m2x2_mul_ck>;
223 ti,bit-shift = <0x1b>;
225 ti,set-bit-to-disable;
228 omap_96m_alwon_fck: omap_96m_alwon_fck {
230 compatible = "fixed-factor-clock";
231 clocks = <&dpll4_m2x2_ck>;
238 compatible = "ti,omap3-dpll-core-clock";
239 clocks = <&sys_ck>, <&sys_ck>;
240 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
243 dpll3_m3_ck: dpll3_m3_ck {
245 compatible = "ti,divider-clock";
246 clocks = <&dpll3_ck>;
250 ti,index-starts-at-one;
253 dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
255 compatible = "fixed-factor-clock";
256 clocks = <&dpll3_m3_ck>;
261 dpll3_m3x2_ck: dpll3_m3x2_ck {
263 compatible = "ti,gate-clock";
264 clocks = <&dpll3_m3x2_mul_ck>;
265 ti,bit-shift = <0xc>;
267 ti,set-bit-to-disable;
270 emu_core_alwon_ck: emu_core_alwon_ck {
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll3_m3x2_ck>;
278 sys_altclk: sys_altclk {
280 compatible = "fixed-clock";
281 clock-frequency = <0x0>;
284 mcbsp_clks: mcbsp_clks {
286 compatible = "fixed-clock";
287 clock-frequency = <0x0>;
290 dpll3_m2_ck: dpll3_m2_ck {
292 compatible = "ti,divider-clock";
293 clocks = <&dpll3_ck>;
297 ti,index-starts-at-one;
302 compatible = "fixed-factor-clock";
303 clocks = <&dpll3_m2_ck>;
308 dpll1_fck: dpll1_fck {
310 compatible = "ti,divider-clock";
315 ti,index-starts-at-one;
320 compatible = "ti,omap3-dpll-clock";
321 clocks = <&sys_ck>, <&dpll1_fck>;
322 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
325 dpll1_x2_ck: dpll1_x2_ck {
327 compatible = "fixed-factor-clock";
328 clocks = <&dpll1_ck>;
333 dpll1_x2m2_ck: dpll1_x2m2_ck {
335 compatible = "ti,divider-clock";
336 clocks = <&dpll1_x2_ck>;
339 ti,index-starts-at-one;
342 cm_96m_fck: cm_96m_fck {
344 compatible = "fixed-factor-clock";
345 clocks = <&omap_96m_alwon_fck>;
350 omap_96m_fck: omap_96m_fck {
352 compatible = "ti,mux-clock";
353 clocks = <&cm_96m_fck>, <&sys_ck>;
358 dpll4_m3_ck: dpll4_m3_ck {
360 compatible = "ti,divider-clock";
361 clocks = <&dpll4_ck>;
365 ti,index-starts-at-one;
368 dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
370 compatible = "fixed-factor-clock";
371 clocks = <&dpll4_m3_ck>;
376 dpll4_m3x2_ck: dpll4_m3x2_ck {
378 compatible = "ti,gate-clock";
379 clocks = <&dpll4_m3x2_mul_ck>;
380 ti,bit-shift = <0x1c>;
382 ti,set-bit-to-disable;
385 omap_54m_fck: omap_54m_fck {
387 compatible = "ti,mux-clock";
388 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
393 cm_96m_d2_fck: cm_96m_d2_fck {
395 compatible = "fixed-factor-clock";
396 clocks = <&cm_96m_fck>;
401 omap_48m_fck: omap_48m_fck {
403 compatible = "ti,mux-clock";
404 clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
409 omap_12m_fck: omap_12m_fck {
411 compatible = "fixed-factor-clock";
412 clocks = <&omap_48m_fck>;
417 dpll4_m4_ck: dpll4_m4_ck {
419 compatible = "ti,divider-clock";
420 clocks = <&dpll4_ck>;
423 ti,index-starts-at-one;
426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
428 compatible = "ti,fixed-factor-clock";
429 clocks = <&dpll4_m4_ck>;
435 dpll4_m4x2_ck: dpll4_m4x2_ck {
437 compatible = "ti,gate-clock";
438 clocks = <&dpll4_m4x2_mul_ck>;
439 ti,bit-shift = <0x1d>;
441 ti,set-bit-to-disable;
445 dpll4_m5_ck: dpll4_m5_ck {
447 compatible = "ti,divider-clock";
448 clocks = <&dpll4_ck>;
451 ti,index-starts-at-one;
454 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
456 compatible = "ti,fixed-factor-clock";
457 clocks = <&dpll4_m5_ck>;
463 dpll4_m5x2_ck: dpll4_m5x2_ck {
465 compatible = "ti,gate-clock";
466 clocks = <&dpll4_m5x2_mul_ck>;
467 ti,bit-shift = <0x1e>;
469 ti,set-bit-to-disable;
472 dpll4_m6_ck: dpll4_m6_ck {
474 compatible = "ti,divider-clock";
475 clocks = <&dpll4_ck>;
479 ti,index-starts-at-one;
482 dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
484 compatible = "fixed-factor-clock";
485 clocks = <&dpll4_m6_ck>;
490 dpll4_m6x2_ck: dpll4_m6x2_ck {
492 compatible = "ti,gate-clock";
493 clocks = <&dpll4_m6x2_mul_ck>;
494 ti,bit-shift = <0x1f>;
496 ti,set-bit-to-disable;
499 emu_per_alwon_ck: emu_per_alwon_ck {
501 compatible = "fixed-factor-clock";
502 clocks = <&dpll4_m6x2_ck>;
507 clkout2_src_gate_ck: clkout2_src_gate_ck {
509 compatible = "ti,composite-no-wait-gate-clock";
515 clkout2_src_mux_ck: clkout2_src_mux_ck {
517 compatible = "ti,composite-mux-clock";
518 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
522 clkout2_src_ck: clkout2_src_ck {
524 compatible = "ti,composite-clock";
525 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
528 sys_clkout2: sys_clkout2 {
530 compatible = "ti,divider-clock";
531 clocks = <&clkout2_src_ck>;
535 ti,index-power-of-two;
540 compatible = "fixed-factor-clock";
541 clocks = <&dpll1_x2m2_ck>;
548 compatible = "ti,divider-clock";
554 emu_mpu_alwon_ck: emu_mpu_alwon_ck {
556 compatible = "fixed-factor-clock";
564 compatible = "ti,divider-clock";
568 ti,index-starts-at-one;
573 compatible = "ti,divider-clock";
578 ti,index-starts-at-one;
583 compatible = "ti,divider-clock";
588 ti,index-starts-at-one;
591 gpt10_gate_fck: gpt10_gate_fck {
593 compatible = "ti,composite-gate-clock";
599 gpt10_mux_fck: gpt10_mux_fck {
601 compatible = "ti,composite-mux-clock";
602 clocks = <&omap_32k_fck>, <&sys_ck>;
607 gpt10_fck: gpt10_fck {
609 compatible = "ti,composite-clock";
610 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
613 gpt11_gate_fck: gpt11_gate_fck {
615 compatible = "ti,composite-gate-clock";
621 gpt11_mux_fck: gpt11_mux_fck {
623 compatible = "ti,composite-mux-clock";
624 clocks = <&omap_32k_fck>, <&sys_ck>;
629 gpt11_fck: gpt11_fck {
631 compatible = "ti,composite-clock";
632 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
635 core_96m_fck: core_96m_fck {
637 compatible = "fixed-factor-clock";
638 clocks = <&omap_96m_fck>;
643 mmchs2_fck: mmchs2_fck {
645 compatible = "ti,wait-gate-clock";
646 clocks = <&core_96m_fck>;
651 mmchs1_fck: mmchs1_fck {
653 compatible = "ti,wait-gate-clock";
654 clocks = <&core_96m_fck>;
661 compatible = "ti,wait-gate-clock";
662 clocks = <&core_96m_fck>;
669 compatible = "ti,wait-gate-clock";
670 clocks = <&core_96m_fck>;
677 compatible = "ti,wait-gate-clock";
678 clocks = <&core_96m_fck>;
683 mcbsp5_gate_fck: mcbsp5_gate_fck {
685 compatible = "ti,composite-gate-clock";
686 clocks = <&mcbsp_clks>;
691 mcbsp1_gate_fck: mcbsp1_gate_fck {
693 compatible = "ti,composite-gate-clock";
694 clocks = <&mcbsp_clks>;
699 core_48m_fck: core_48m_fck {
701 compatible = "fixed-factor-clock";
702 clocks = <&omap_48m_fck>;
707 mcspi4_fck: mcspi4_fck {
709 compatible = "ti,wait-gate-clock";
710 clocks = <&core_48m_fck>;
715 mcspi3_fck: mcspi3_fck {
717 compatible = "ti,wait-gate-clock";
718 clocks = <&core_48m_fck>;
723 mcspi2_fck: mcspi2_fck {
725 compatible = "ti,wait-gate-clock";
726 clocks = <&core_48m_fck>;
731 mcspi1_fck: mcspi1_fck {
733 compatible = "ti,wait-gate-clock";
734 clocks = <&core_48m_fck>;
739 uart2_fck: uart2_fck {
741 compatible = "ti,wait-gate-clock";
742 clocks = <&core_48m_fck>;
747 uart1_fck: uart1_fck {
749 compatible = "ti,wait-gate-clock";
750 clocks = <&core_48m_fck>;
755 core_12m_fck: core_12m_fck {
757 compatible = "fixed-factor-clock";
758 clocks = <&omap_12m_fck>;
765 compatible = "ti,wait-gate-clock";
766 clocks = <&core_12m_fck>;
771 core_l3_ick: core_l3_ick {
773 compatible = "fixed-factor-clock";
781 compatible = "ti,wait-gate-clock";
782 clocks = <&core_l3_ick>;
789 compatible = "fixed-factor-clock";
790 clocks = <&core_l3_ick>;
795 core_l4_ick: core_l4_ick {
797 compatible = "fixed-factor-clock";
803 mmchs2_ick: mmchs2_ick {
805 compatible = "ti,omap3-interface-clock";
806 clocks = <&core_l4_ick>;
811 mmchs1_ick: mmchs1_ick {
813 compatible = "ti,omap3-interface-clock";
814 clocks = <&core_l4_ick>;
821 compatible = "ti,omap3-interface-clock";
822 clocks = <&core_l4_ick>;
827 mcspi4_ick: mcspi4_ick {
829 compatible = "ti,omap3-interface-clock";
830 clocks = <&core_l4_ick>;
835 mcspi3_ick: mcspi3_ick {
837 compatible = "ti,omap3-interface-clock";
838 clocks = <&core_l4_ick>;
843 mcspi2_ick: mcspi2_ick {
845 compatible = "ti,omap3-interface-clock";
846 clocks = <&core_l4_ick>;
851 mcspi1_ick: mcspi1_ick {
853 compatible = "ti,omap3-interface-clock";
854 clocks = <&core_l4_ick>;
861 compatible = "ti,omap3-interface-clock";
862 clocks = <&core_l4_ick>;
869 compatible = "ti,omap3-interface-clock";
870 clocks = <&core_l4_ick>;
877 compatible = "ti,omap3-interface-clock";
878 clocks = <&core_l4_ick>;
883 uart2_ick: uart2_ick {
885 compatible = "ti,omap3-interface-clock";
886 clocks = <&core_l4_ick>;
891 uart1_ick: uart1_ick {
893 compatible = "ti,omap3-interface-clock";
894 clocks = <&core_l4_ick>;
899 gpt11_ick: gpt11_ick {
901 compatible = "ti,omap3-interface-clock";
902 clocks = <&core_l4_ick>;
907 gpt10_ick: gpt10_ick {
909 compatible = "ti,omap3-interface-clock";
910 clocks = <&core_l4_ick>;
915 mcbsp5_ick: mcbsp5_ick {
917 compatible = "ti,omap3-interface-clock";
918 clocks = <&core_l4_ick>;
923 mcbsp1_ick: mcbsp1_ick {
925 compatible = "ti,omap3-interface-clock";
926 clocks = <&core_l4_ick>;
931 omapctrl_ick: omapctrl_ick {
933 compatible = "ti,omap3-interface-clock";
934 clocks = <&core_l4_ick>;
939 dss_tv_fck: dss_tv_fck {
941 compatible = "ti,gate-clock";
942 clocks = <&omap_54m_fck>;
947 dss_96m_fck: dss_96m_fck {
949 compatible = "ti,gate-clock";
950 clocks = <&omap_96m_fck>;
955 dss2_alwon_fck: dss2_alwon_fck {
957 compatible = "ti,gate-clock";
965 compatible = "fixed-clock";
966 clock-frequency = <0>;
969 gpt1_gate_fck: gpt1_gate_fck {
971 compatible = "ti,composite-gate-clock";
977 gpt1_mux_fck: gpt1_mux_fck {
979 compatible = "ti,composite-mux-clock";
980 clocks = <&omap_32k_fck>, <&sys_ck>;
986 compatible = "ti,composite-clock";
987 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
992 compatible = "ti,omap3-interface-clock";
993 clocks = <&core_l4_ick>;
998 wkup_32k_fck: wkup_32k_fck {
1000 compatible = "fixed-factor-clock";
1001 clocks = <&omap_32k_fck>;
1006 gpio1_dbck: gpio1_dbck {
1008 compatible = "ti,gate-clock";
1009 clocks = <&wkup_32k_fck>;
1014 sha12_ick: sha12_ick {
1016 compatible = "ti,omap3-interface-clock";
1017 clocks = <&core_l4_ick>;
1019 ti,bit-shift = <27>;
1022 wdt2_fck: wdt2_fck {
1024 compatible = "ti,wait-gate-clock";
1025 clocks = <&wkup_32k_fck>;
1030 wdt2_ick: wdt2_ick {
1032 compatible = "ti,omap3-interface-clock";
1033 clocks = <&wkup_l4_ick>;
1038 wdt1_ick: wdt1_ick {
1040 compatible = "ti,omap3-interface-clock";
1041 clocks = <&wkup_l4_ick>;
1046 gpio1_ick: gpio1_ick {
1048 compatible = "ti,omap3-interface-clock";
1049 clocks = <&wkup_l4_ick>;
1054 omap_32ksync_ick: omap_32ksync_ick {
1056 compatible = "ti,omap3-interface-clock";
1057 clocks = <&wkup_l4_ick>;
1062 gpt12_ick: gpt12_ick {
1064 compatible = "ti,omap3-interface-clock";
1065 clocks = <&wkup_l4_ick>;
1070 gpt1_ick: gpt1_ick {
1072 compatible = "ti,omap3-interface-clock";
1073 clocks = <&wkup_l4_ick>;
1078 per_96m_fck: per_96m_fck {
1080 compatible = "fixed-factor-clock";
1081 clocks = <&omap_96m_alwon_fck>;
1086 per_48m_fck: per_48m_fck {
1088 compatible = "fixed-factor-clock";
1089 clocks = <&omap_48m_fck>;
1094 uart3_fck: uart3_fck {
1096 compatible = "ti,wait-gate-clock";
1097 clocks = <&per_48m_fck>;
1099 ti,bit-shift = <11>;
1102 gpt2_gate_fck: gpt2_gate_fck {
1104 compatible = "ti,composite-gate-clock";
1110 gpt2_mux_fck: gpt2_mux_fck {
1112 compatible = "ti,composite-mux-clock";
1113 clocks = <&omap_32k_fck>, <&sys_ck>;
1117 gpt2_fck: gpt2_fck {
1119 compatible = "ti,composite-clock";
1120 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1123 gpt3_gate_fck: gpt3_gate_fck {
1125 compatible = "ti,composite-gate-clock";
1131 gpt3_mux_fck: gpt3_mux_fck {
1133 compatible = "ti,composite-mux-clock";
1134 clocks = <&omap_32k_fck>, <&sys_ck>;
1139 gpt3_fck: gpt3_fck {
1141 compatible = "ti,composite-clock";
1142 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1145 gpt4_gate_fck: gpt4_gate_fck {
1147 compatible = "ti,composite-gate-clock";
1153 gpt4_mux_fck: gpt4_mux_fck {
1155 compatible = "ti,composite-mux-clock";
1156 clocks = <&omap_32k_fck>, <&sys_ck>;
1161 gpt4_fck: gpt4_fck {
1163 compatible = "ti,composite-clock";
1164 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1167 gpt5_gate_fck: gpt5_gate_fck {
1169 compatible = "ti,composite-gate-clock";
1175 gpt5_mux_fck: gpt5_mux_fck {
1177 compatible = "ti,composite-mux-clock";
1178 clocks = <&omap_32k_fck>, <&sys_ck>;
1183 gpt5_fck: gpt5_fck {
1185 compatible = "ti,composite-clock";
1186 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1189 gpt6_gate_fck: gpt6_gate_fck {
1191 compatible = "ti,composite-gate-clock";
1197 gpt6_mux_fck: gpt6_mux_fck {
1199 compatible = "ti,composite-mux-clock";
1200 clocks = <&omap_32k_fck>, <&sys_ck>;
1205 gpt6_fck: gpt6_fck {
1207 compatible = "ti,composite-clock";
1208 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1211 gpt7_gate_fck: gpt7_gate_fck {
1213 compatible = "ti,composite-gate-clock";
1219 gpt7_mux_fck: gpt7_mux_fck {
1221 compatible = "ti,composite-mux-clock";
1222 clocks = <&omap_32k_fck>, <&sys_ck>;
1227 gpt7_fck: gpt7_fck {
1229 compatible = "ti,composite-clock";
1230 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1233 gpt8_gate_fck: gpt8_gate_fck {
1235 compatible = "ti,composite-gate-clock";
1241 gpt8_mux_fck: gpt8_mux_fck {
1243 compatible = "ti,composite-mux-clock";
1244 clocks = <&omap_32k_fck>, <&sys_ck>;
1249 gpt8_fck: gpt8_fck {
1251 compatible = "ti,composite-clock";
1252 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1255 gpt9_gate_fck: gpt9_gate_fck {
1257 compatible = "ti,composite-gate-clock";
1259 ti,bit-shift = <10>;
1263 gpt9_mux_fck: gpt9_mux_fck {
1265 compatible = "ti,composite-mux-clock";
1266 clocks = <&omap_32k_fck>, <&sys_ck>;
1271 gpt9_fck: gpt9_fck {
1273 compatible = "ti,composite-clock";
1274 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1277 per_32k_alwon_fck: per_32k_alwon_fck {
1279 compatible = "fixed-factor-clock";
1280 clocks = <&omap_32k_fck>;
1285 gpio6_dbck: gpio6_dbck {
1287 compatible = "ti,gate-clock";
1288 clocks = <&per_32k_alwon_fck>;
1290 ti,bit-shift = <17>;
1293 gpio5_dbck: gpio5_dbck {
1295 compatible = "ti,gate-clock";
1296 clocks = <&per_32k_alwon_fck>;
1298 ti,bit-shift = <16>;
1301 gpio4_dbck: gpio4_dbck {
1303 compatible = "ti,gate-clock";
1304 clocks = <&per_32k_alwon_fck>;
1306 ti,bit-shift = <15>;
1309 gpio3_dbck: gpio3_dbck {
1311 compatible = "ti,gate-clock";
1312 clocks = <&per_32k_alwon_fck>;
1314 ti,bit-shift = <14>;
1317 gpio2_dbck: gpio2_dbck {
1319 compatible = "ti,gate-clock";
1320 clocks = <&per_32k_alwon_fck>;
1322 ti,bit-shift = <13>;
1325 wdt3_fck: wdt3_fck {
1327 compatible = "ti,wait-gate-clock";
1328 clocks = <&per_32k_alwon_fck>;
1330 ti,bit-shift = <12>;
1333 per_l4_ick: per_l4_ick {
1335 compatible = "fixed-factor-clock";
1341 gpio6_ick: gpio6_ick {
1343 compatible = "ti,omap3-interface-clock";
1344 clocks = <&per_l4_ick>;
1346 ti,bit-shift = <17>;
1349 gpio5_ick: gpio5_ick {
1351 compatible = "ti,omap3-interface-clock";
1352 clocks = <&per_l4_ick>;
1354 ti,bit-shift = <16>;
1357 gpio4_ick: gpio4_ick {
1359 compatible = "ti,omap3-interface-clock";
1360 clocks = <&per_l4_ick>;
1362 ti,bit-shift = <15>;
1365 gpio3_ick: gpio3_ick {
1367 compatible = "ti,omap3-interface-clock";
1368 clocks = <&per_l4_ick>;
1370 ti,bit-shift = <14>;
1373 gpio2_ick: gpio2_ick {
1375 compatible = "ti,omap3-interface-clock";
1376 clocks = <&per_l4_ick>;
1378 ti,bit-shift = <13>;
1381 wdt3_ick: wdt3_ick {
1383 compatible = "ti,omap3-interface-clock";
1384 clocks = <&per_l4_ick>;
1386 ti,bit-shift = <12>;
1389 uart3_ick: uart3_ick {
1391 compatible = "ti,omap3-interface-clock";
1392 clocks = <&per_l4_ick>;
1394 ti,bit-shift = <11>;
1397 uart4_ick: uart4_ick {
1399 compatible = "ti,omap3-interface-clock";
1400 clocks = <&per_l4_ick>;
1402 ti,bit-shift = <18>;
1405 gpt9_ick: gpt9_ick {
1407 compatible = "ti,omap3-interface-clock";
1408 clocks = <&per_l4_ick>;
1410 ti,bit-shift = <10>;
1413 gpt8_ick: gpt8_ick {
1415 compatible = "ti,omap3-interface-clock";
1416 clocks = <&per_l4_ick>;
1421 gpt7_ick: gpt7_ick {
1423 compatible = "ti,omap3-interface-clock";
1424 clocks = <&per_l4_ick>;
1429 gpt6_ick: gpt6_ick {
1431 compatible = "ti,omap3-interface-clock";
1432 clocks = <&per_l4_ick>;
1437 gpt5_ick: gpt5_ick {
1439 compatible = "ti,omap3-interface-clock";
1440 clocks = <&per_l4_ick>;
1445 gpt4_ick: gpt4_ick {
1447 compatible = "ti,omap3-interface-clock";
1448 clocks = <&per_l4_ick>;
1453 gpt3_ick: gpt3_ick {
1455 compatible = "ti,omap3-interface-clock";
1456 clocks = <&per_l4_ick>;
1461 gpt2_ick: gpt2_ick {
1463 compatible = "ti,omap3-interface-clock";
1464 clocks = <&per_l4_ick>;
1469 mcbsp2_ick: mcbsp2_ick {
1471 compatible = "ti,omap3-interface-clock";
1472 clocks = <&per_l4_ick>;
1477 mcbsp3_ick: mcbsp3_ick {
1479 compatible = "ti,omap3-interface-clock";
1480 clocks = <&per_l4_ick>;
1485 mcbsp4_ick: mcbsp4_ick {
1487 compatible = "ti,omap3-interface-clock";
1488 clocks = <&per_l4_ick>;
1493 mcbsp2_gate_fck: mcbsp2_gate_fck {
1495 compatible = "ti,composite-gate-clock";
1496 clocks = <&mcbsp_clks>;
1501 mcbsp3_gate_fck: mcbsp3_gate_fck {
1503 compatible = "ti,composite-gate-clock";
1504 clocks = <&mcbsp_clks>;
1509 mcbsp4_gate_fck: mcbsp4_gate_fck {
1511 compatible = "ti,composite-gate-clock";
1512 clocks = <&mcbsp_clks>;
1517 emu_src_mux_ck: emu_src_mux_ck {
1519 compatible = "ti,mux-clock";
1520 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1524 emu_src_ck: emu_src_ck {
1526 compatible = "ti,clkdm-gate-clock";
1527 clocks = <&emu_src_mux_ck>;
1530 pclk_fck: pclk_fck {
1532 compatible = "ti,divider-clock";
1533 clocks = <&emu_src_ck>;
1537 ti,index-starts-at-one;
1540 pclkx2_fck: pclkx2_fck {
1542 compatible = "ti,divider-clock";
1543 clocks = <&emu_src_ck>;
1547 ti,index-starts-at-one;
1550 atclk_fck: atclk_fck {
1552 compatible = "ti,divider-clock";
1553 clocks = <&emu_src_ck>;
1557 ti,index-starts-at-one;
1560 traceclk_src_fck: traceclk_src_fck {
1562 compatible = "ti,mux-clock";
1563 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1568 traceclk_fck: traceclk_fck {
1570 compatible = "ti,divider-clock";
1571 clocks = <&traceclk_src_fck>;
1572 ti,bit-shift = <11>;
1575 ti,index-starts-at-one;
1578 secure_32k_fck: secure_32k_fck {
1580 compatible = "fixed-clock";
1581 clock-frequency = <32768>;
1584 gpt12_fck: gpt12_fck {
1586 compatible = "fixed-factor-clock";
1587 clocks = <&secure_32k_fck>;
1592 wdt1_fck: wdt1_fck {
1594 compatible = "fixed-factor-clock";
1595 clocks = <&secure_32k_fck>;
1602 core_l3_clkdm: core_l3_clkdm {
1603 compatible = "ti,clockdomain";
1604 clocks = <&sdrc_ick>;
1607 dpll3_clkdm: dpll3_clkdm {
1608 compatible = "ti,clockdomain";
1609 clocks = <&dpll3_ck>;
1612 dpll1_clkdm: dpll1_clkdm {
1613 compatible = "ti,clockdomain";
1614 clocks = <&dpll1_ck>;
1617 per_clkdm: per_clkdm {
1618 compatible = "ti,clockdomain";
1619 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1620 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1621 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1622 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1623 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1624 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1625 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1629 emu_clkdm: emu_clkdm {
1630 compatible = "ti,clockdomain";
1631 clocks = <&emu_src_ck>;
1634 dpll4_clkdm: dpll4_clkdm {
1635 compatible = "ti,clockdomain";
1636 clocks = <&dpll4_ck>;
1639 wkup_clkdm: wkup_clkdm {
1640 compatible = "ti,clockdomain";
1641 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1642 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1646 dss_clkdm: dss_clkdm {
1647 compatible = "ti,clockdomain";
1648 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1651 core_l4_clkdm: core_l4_clkdm {
1652 compatible = "ti,clockdomain";
1653 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1654 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1655 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1656 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1657 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1658 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1659 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1660 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1661 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;