arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2014-2022 Toradex
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  * Copyright 2011 Linaro Ltd.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/pwm/pwm.h>
  10
  11 / {
  12         model = "Toradex Apalis iMX6Q/D Module";
  13         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  14
  15         aliases {
  16                 mmc0 = &usdhc3; /* eMMC */
  17                 mmc1 = &usdhc1; /* MMC1 slot */
  18                 mmc2 = &usdhc2; /* SD1 slot */
  19                 /delete-property/ mmc3;
  20         };
  21
  22         /* Will be filled by the bootloader */
  23         memory@10000000 {
  24                 device_type = "memory";
  25                 reg = <0x10000000 0>;
  26         };
  27
  28         backlight: backlight {
  29                 compatible = "pwm-backlight";
  30                 brightness-levels = <0 45 63 88 119 158 203 255>;
  31                 default-brightness-level = <4>;
  32                 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  35                 power-supply = <&reg_module_3v3>;
  36                 pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>;
  37                 status = "disabled";
  38         };
  39
  40         clk_ov5640_osc: clk-ov5640-osc {
  41                 compatible = "fixed-clock";
  42                 #clock-cells = <0>;
  43                 clock-frequency = <24000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 pinctrl-names = "default";
  49                 pinctrl-0 = <&pinctrl_gpio_keys>;
  50
  51                 key-wakeup {
  52                         debounce-interval = <10>;
  53                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  54                         label = "Wake-Up";
  55                         linux,code = <KEY_WAKEUP>;
  56                         wakeup-source;
  57                 };
  58         };
  59
  60         lcd_display: disp0 {
  61                 compatible = "fsl,imx-parallel-display";
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64                 interface-pix-fmt = "rgb24";
  65                 pinctrl-names = "default";
  66                 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
  67                 status = "disabled";
  68
  69                 port@0 {
  70                         reg = <0>;
  71
  72                         lcd_display_in: endpoint {
  73                                 remote-endpoint = <&ipu1_di1_disp1>;
  74                         };
  75                 };
  76
  77                 port@1 {
  78                         reg = <1>;
  79
  80                         lcd_display_out: endpoint {
  81                                 remote-endpoint = <&lcd_panel_in>;
  82                         };
  83                 };
  84         };
  85
  86         panel_dpi: panel-dpi {
  87                 compatible = "edt,et057090dhu";
  88                 backlight = <&backlight>;
  89
  90                 status = "disabled";
  91
  92                 port {
  93                         lcd_panel_in: endpoint {
  94                                 remote-endpoint = <&lcd_display_out>;
  95                         };
  96                 };
  97         };
  98
  99         panel_lvds: panel-lvds {
 100                 compatible = "panel-lvds";
 101                 backlight = <&backlight>;
 102                 status = "disabled";
 103
 104                 port {
 105                         lvds_panel_in: endpoint {
 106                                 remote-endpoint = <&lvds0_out>;
 107                         };
 108                 };
 109         };
 110
 111         reg_module_3v3: regulator-module-3v3 {
 112                 compatible = "regulator-fixed";
 113                 regulator-always-on;
 114                 regulator-max-microvolt = <3300000>;
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-name = "+V3.3";
 117         };
 118
 119         reg_module_3v3_audio: regulator-module-3v3-audio {
 120                 compatible = "regulator-fixed";
 121                 regulator-always-on;
 122                 regulator-max-microvolt = <3300000>;
 123                 regulator-min-microvolt = <3300000>;
 124                 regulator-name = "+V3.3_AUDIO";
 125         };
 126
 127         reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd {
 128                 compatible = "regulator-fixed";
 129                 regulator-always-on;
 130                 regulator-max-microvolt = <1800000>;
 131                 regulator-min-microvolt = <1800000>;
 132                 regulator-name = "DOVDD/DVDD_1.8V";
 133                 /* Note: The CSI module uses on-board 3.3V_SW supply */
 134                 vin-supply = <&reg_module_3v3>;
 135         };
 136
 137         reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd {
 138                 compatible = "regulator-fixed";
 139                 regulator-always-on;
 140                 regulator-max-microvolt = <2800000>;
 141                 regulator-min-microvolt = <2800000>;
 142                 regulator-name = "AVDD/AFVDD_2.8V";
 143                 /* Note: The CSI module uses on-board 3.3V_SW supply */
 144                 vin-supply = <&reg_module_3v3>;
 145         };
 146
 147         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 148                 compatible = "regulator-fixed";
 149                 enable-active-high;
 150                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 151                 pinctrl-names = "default";
 152                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
 153                 regulator-max-microvolt = <5000000>;
 154                 regulator-min-microvolt = <5000000>;
 155                 regulator-name = "usb_otg_vbus";
 156                 status = "disabled";
 157         };
 158
 159         /* on module USB hub */
 160         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
 161                 compatible = "regulator-fixed";
 162                 enable-active-high;
 163                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 164                 pinctrl-names = "default";
 165                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
 166                 regulator-max-microvolt = <5000000>;
 167                 regulator-min-microvolt = <5000000>;
 168                 regulator-name = "usb_host_vbus_hub";
 169                 startup-delay-us = <2000>;
 170                 status = "okay";
 171         };
 172
 173         reg_usb_host_vbus: regulator-usb-host-vbus {
 174                 compatible = "regulator-fixed";
 175                 enable-active-high;
 176                 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 177                 pinctrl-names = "default";
 178                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
 179                 regulator-max-microvolt = <5000000>;
 180                 regulator-min-microvolt = <5000000>;
 181                 regulator-name = "usb_host_vbus";
 182                 vin-supply = <&reg_usb_host_vbus_hub>;
 183                 status = "disabled";
 184         };
 185
 186         sound {
 187                 compatible = "fsl,imx-audio-sgtl5000";
 188                 audio-codec = <&codec>;
 189                 audio-routing =
 190                         "LINE_IN", "Line In Jack",
 191                         "MIC_IN", "Mic Jack",
 192                         "Mic Jack", "Mic Bias",
 193                         "Headphone Jack", "HP_OUT";
 194                 model = "imx6q-apalis-sgtl5000";
 195                 mux-ext-port = <4>;
 196                 mux-int-port = <1>;
 197                 ssi-controller = <&ssi1>;
 198         };
 199
 200         sound_spdif: sound-spdif {
 201                 compatible = "fsl,imx-audio-spdif";
 202                 spdif-controller = <&spdif>;
 203                 spdif-in;
 204                 spdif-out;
 205                 model = "imx-spdif";
 206                 status = "disabled";
 207         };
 208 };
 209
 210 &audmux {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_audmux>;
 213         status = "okay";
 214 };
 215
 216 &can1 {
 217         pinctrl-names = "default", "sleep";
 218         pinctrl-0 = <&pinctrl_flexcan1_default>;
 219         pinctrl-1 = <&pinctrl_flexcan1_sleep>;
 220         status = "disabled";
 221 };
 222
 223 &can2 {
 224         pinctrl-names = "default", "sleep";
 225         pinctrl-0 = <&pinctrl_flexcan2_default>;
 226         pinctrl-1 = <&pinctrl_flexcan2_sleep>;
 227         status = "disabled";
 228 };
 229
 230 &clks {
 231         fsl,pmic-stby-poweroff;
 232 };
 233
 234 /* Apalis SPI1 */
 235 &ecspi1 {
 236         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&pinctrl_ecspi1>;
 239         status = "disabled";
 240 };
 241
 242 /* Apalis SPI2 */
 243 &ecspi2 {
 244         cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&pinctrl_ecspi2>;
 247         status = "disabled";
 248 };
 249
 250 &gpio1 {
 251         gpio-line-names = "MXM3_84",
 252                           "MXM3_4",
 253                           "MXM3_15/GPIO7",
 254                           "MXM3_96",
 255                           "MXM3_37",
 256                           "",
 257                           "MXM3_17/GPIO8",
 258                           "MXM3_14",
 259                           "MXM3_12",
 260                           "MXM3_2",
 261                           "MXM3_184",
 262                           "MXM3_180",
 263                           "MXM3_178",
 264                           "MXM3_176",
 265                           "MXM3_188",
 266                           "MXM3_186",
 267                           "MXM3_160",
 268                           "MXM3_162",
 269                           "MXM3_150",
 270                           "MXM3_144",
 271                           "MXM3_154",
 272                           "MXM3_146",
 273                           "",
 274                           "",
 275                           "MXM3_72";
 276 };
 277
 278 &gpio2 {
 279         gpio-line-names = "MXM3_148",
 280                           "MXM3_152",
 281                           "MXM3_156",
 282                           "MXM3_158",
 283                           "MXM3_1/GPIO1",
 284                           "MXM3_3/GPIO2",
 285                           "MXM3_5/GPIO3",
 286                           "MXM3_7/GPIO4",
 287                           "MXM3_95",
 288                           "MXM3_6",
 289                           "MXM3_8",
 290                           "MXM3_123",
 291                           "MXM3_126",
 292                           "MXM3_128",
 293                           "MXM3_130",
 294                           "MXM3_132",
 295                           "MXM3_253",
 296                           "MXM3_251",
 297                           "MXM3_283",
 298                           "MXM3_281",
 299                           "MXM3_279",
 300                           "MXM3_277",
 301                           "MXM3_243",
 302                           "MXM3_235",
 303                           "MXM3_231",
 304                           "MXM3_229",
 305                           "MXM3_233",
 306                           "MXM3_198",
 307                           "MXM3_275",
 308                           "MXM3_273",
 309                           "MXM3_207",
 310                           "MXM3_122";
 311 };
 312
 313 &gpio3 {
 314         gpio-line-names = "MXM3_271",
 315                           "MXM3_269",
 316                           "MXM3_301",
 317                           "MXM3_299",
 318                           "MXM3_297",
 319                           "MXM3_295",
 320                           "MXM3_293",
 321                           "MXM3_291",
 322                           "MXM3_289",
 323                           "MXM3_287",
 324                           "MXM3_249",
 325                           "MXM3_247",
 326                           "MXM3_245",
 327                           "MXM3_286",
 328                           "MXM3_239",
 329                           "MXM3_35",
 330                           "MXM3_205",
 331                           "MXM3_203",
 332                           "MXM3_201",
 333                           "MXM3_116",
 334                           "MXM3_114",
 335                           "MXM3_262",
 336                           "MXM3_274",
 337                           "MXM3_124",
 338                           "MXM3_110",
 339                           "MXM3_120",
 340                           "MXM3_263",
 341                           "MXM3_265",
 342                           "",
 343                           "MXM3_135",
 344                           "MXM3_261",
 345                           "MXM3_259";
 346 };
 347
 348 &gpio4 {
 349         gpio-line-names = "",
 350                           "",
 351                           "",
 352                           "",
 353                           "",
 354                           "MXM3_194",
 355                           "MXM3_136",
 356                           "MXM3_134",
 357                           "MXM3_140",
 358                           "MXM3_138",
 359                           "",
 360                           "MXM3_220",
 361                           "",
 362                           "",
 363                           "MXM3_18",
 364                           "MXM3_16",
 365                           "",
 366                           "",
 367                           "MXM3_214",
 368                           "MXM3_216",
 369                           "MXM3_164";
 370 };
 371
 372 &gpio5 {
 373         gpio-line-names = "MXM3_159",
 374                           "",
 375                           "",
 376                           "",
 377                           "MXM3_257",
 378                           "",
 379                           "",
 380                           "",
 381                           "",
 382                           "",
 383                           "MXM3_200",
 384                           "MXM3_196",
 385                           "MXM3_204",
 386                           "MXM3_202",
 387                           "",
 388                           "",
 389                           "",
 390                           "",
 391                           "MXM3_191",
 392                           "MXM3_197",
 393                           "MXM3_77",
 394                           "MXM3_195",
 395                           "MXM3_221",
 396                           "MXM3_225",
 397                           "MXM3_223",
 398                           "MXM3_227",
 399                           "MXM3_209",
 400                           "MXM3_211",
 401                           "MXM3_118",
 402                           "MXM3_112",
 403                           "MXM3_187",
 404                           "MXM3_185";
 405 };
 406
 407 &gpio6 {
 408         gpio-line-names = "MXM3_183",
 409                           "MXM3_181",
 410                           "MXM3_179",
 411                           "MXM3_177",
 412                           "MXM3_175",
 413                           "MXM3_173",
 414                           "MXM3_255",
 415                           "MXM3_83",
 416                           "MXM3_91",
 417                           "MXM3_13/GPIO6",
 418                           "MXM3_11/GPIO5",
 419                           "MXM3_79",
 420                           "",
 421                           "",
 422                           "MXM3_190",
 423                           "MXM3_193",
 424                           "MXM3_89";
 425 };
 426
 427 &gpio7 {
 428         gpio-line-names = "",
 429                           "",
 430                           "",
 431                           "",
 432                           "",
 433                           "",
 434                           "",
 435                           "",
 436                           "",
 437                           "MXM3_99",
 438                           "MXM3_85",
 439                           "MXM3_217",
 440                           "MXM3_215";
 441 };
 442
 443 &gpr {
 444         ipu1_csi0_mux {
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 status = "disabled";
 448
 449                 port@1 {
 450                         reg = <1>;
 451                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 452                                 remote-endpoint = <&adv7280_to_ipu1_csi0_mux>;
 453                         };
 454                 };
 455         };
 456 };
 457
 458 &fec {
 459         pinctrl-names = "default";
 460         pinctrl-0 = <&pinctrl_enet>;
 461         phy-mode = "rgmii-id";
 462         phy-handle = <&ethphy>;
 463         phy-reset-duration = <10>;
 464         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 465         status = "okay";
 466
 467         mdio {
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470
 471                 ethphy: ethernet-phy@7 {
 472                         interrupt-parent = <&gpio1>;
 473                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 474                         reg = <7>;
 475                 };
 476         };
 477 };
 478
 479 &hdmi {
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>;
 482         status = "disabled";
 483 };
 484
 485 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 486 &i2c1 {
 487         clock-frequency = <100000>;
 488         pinctrl-names = "default", "gpio";
 489         pinctrl-0 = <&pinctrl_i2c1>;
 490         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 491         scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 492         sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 493         status = "disabled";
 494
 495         atmel_mxt_ts: touchscreen@4a {
 496                 compatible = "atmel,maxtouch";
 497                 /* These GPIOs are muxed with the iomuxc node */
 498                 interrupt-parent = <&gpio6>;
 499                 interrupts = <10 IRQ_TYPE_EDGE_FALLING>;        /* MXM3_11 */
 500                 reg = <0x4a>;
 501                 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;       /* MXM3_13 */
 502                 status = "disabled";
 503         };
 504 };
 505
 506 /*
 507  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 508  * touch screen controller
 509  */
 510 &i2c2 {
 511         clock-frequency = <100000>;
 512         pinctrl-names = "default", "gpio";
 513         pinctrl-0 = <&pinctrl_i2c2>;
 514         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 515         scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 516         sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 517         status = "okay";
 518
 519         pmic: pmic@8 {
 520                 compatible = "fsl,pfuze100";
 521                 fsl,pmic-stby-poweroff;
 522                 reg = <0x08>;
 523
 524                 regulators {
 525                         sw1a_reg: sw1ab {
 526                                 regulator-always-on;
 527                                 regulator-boot-on;
 528                                 regulator-max-microvolt = <1875000>;
 529                                 regulator-min-microvolt = <300000>;
 530                                 regulator-ramp-delay = <6250>;
 531                         };
 532
 533                         sw1c_reg: sw1c {
 534                                 regulator-always-on;
 535                                 regulator-boot-on;
 536                                 regulator-max-microvolt = <1875000>;
 537                                 regulator-min-microvolt = <300000>;
 538                                 regulator-ramp-delay = <6250>;
 539                         };
 540
 541                         sw3a_reg: sw3a {
 542                                 regulator-always-on;
 543                                 regulator-boot-on;
 544                                 regulator-max-microvolt = <1975000>;
 545                                 regulator-min-microvolt = <400000>;
 546                         };
 547
 548                         swbst_reg: swbst {
 549                                 regulator-always-on;
 550                                 regulator-boot-on;
 551                                 regulator-max-microvolt = <5150000>;
 552                                 regulator-min-microvolt = <5000000>;
 553                         };
 554
 555                         snvs_reg: vsnvs {
 556                                 regulator-always-on;
 557                                 regulator-boot-on;
 558                                 regulator-max-microvolt = <3000000>;
 559                                 regulator-min-microvolt = <1000000>;
 560                         };
 561
 562                         vref_reg: vrefddr {
 563                                 regulator-always-on;
 564                                 regulator-boot-on;
 565                         };
 566
 567                         vgen1_reg: vgen1 {
 568                                 regulator-always-on;
 569                                 regulator-boot-on;
 570                                 regulator-max-microvolt = <1550000>;
 571                                 regulator-min-microvolt = <800000>;
 572                         };
 573
 574                         vgen2_reg: vgen2 {
 575                                 regulator-always-on;
 576                                 regulator-boot-on;
 577                                 regulator-max-microvolt = <1550000>;
 578                                 regulator-min-microvolt = <800000>;
 579                         };
 580
 581                         vgen3_reg: vgen3 {
 582                                 regulator-always-on;
 583                                 regulator-boot-on;
 584                                 regulator-max-microvolt = <3300000>;
 585                                 regulator-min-microvolt = <1800000>;
 586                         };
 587
 588                         vgen4_reg: vgen4 {
 589                                 regulator-always-on;
 590                                 regulator-boot-on;
 591                                 regulator-max-microvolt = <1800000>;
 592                                 regulator-min-microvolt = <1800000>;
 593                         };
 594
 595                         vgen5_reg: vgen5 {
 596                                 regulator-always-on;
 597                                 regulator-boot-on;
 598                                 regulator-max-microvolt = <3300000>;
 599                                 regulator-min-microvolt = <1800000>;
 600                         };
 601
 602                         vgen6_reg: vgen6 {
 603                                 regulator-always-on;
 604                                 regulator-boot-on;
 605                                 regulator-max-microvolt = <3300000>;
 606                                 regulator-min-microvolt = <1800000>;
 607                         };
 608                 };
 609         };
 610
 611         codec: sgtl5000@a {
 612                 compatible = "fsl,sgtl5000";
 613                 #sound-dai-cells = <0>;
 614                 clocks = <&clks IMX6QDL_CLK_CKO>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&pinctrl_sgtl5000>;
 617                 reg = <0x0a>;
 618                 VDDA-supply = <&reg_module_3v3_audio>;
 619                 VDDIO-supply = <&reg_module_3v3>;
 620                 VDDD-supply = <&vgen4_reg>;
 621         };
 622
 623         /* STMPE811 touch screen controller */
 624         stmpe811@41 {
 625                 compatible = "st,stmpe811";
 626                 blocks = <0x5>;
 627                 id = <0>;
 628                 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 629                 interrupt-parent = <&gpio4>;
 630                 irq-trigger = <0x1>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&pinctrl_touch_int>;
 633                 reg = <0x41>;
 634                 /* 3.25 MHz ADC clock speed */
 635                 st,adc-freq = <1>;
 636                 /* 12-bit ADC */
 637                 st,mod-12b = <1>;
 638                 /* internal ADC reference */
 639                 st,ref-sel = <0>;
 640                 /* ADC conversion time: 80 clocks */
 641                 st,sample-time = <4>;
 642
 643                 stmpe_ts: stmpe_touchscreen {
 644                         compatible = "st,stmpe-ts";
 645                         /* 8 sample average control */
 646                         st,ave-ctrl = <3>;
 647                         /* 7 length fractional part in z */
 648                         st,fraction-z = <7>;
 649                         /*
 650                          * 50 mA typical 80 mA max touchscreen drivers
 651                          * current limit value
 652                          */
 653                         st,i-drive = <1>;
 654                         /* 1 ms panel driver settling time */
 655                         st,settling = <3>;
 656                         /* 5 ms touch detect interrupt delay */
 657                         st,touch-det-delay = <5>;
 658                         status = "disabled";
 659                 };
 660
 661                 stmpe_adc: stmpe_adc {
 662                         compatible = "st,stmpe-adc";
 663                         #io-channel-cells = <1>;
 664                         /* forbid to use ADC channels 3-0 (touch) */
 665                         st,norequest-mask = <0x0F>;
 666                 };
 667         };
 668 };
 669
 670 /*
 671  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 672  * board)
 673  */
 674 &i2c3 {
 675         clock-frequency = <100000>;
 676         pinctrl-names = "default", "gpio";
 677         pinctrl-0 = <&pinctrl_i2c3>;
 678         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 679         scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 680         sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 681         status = "disabled";
 682
 683         adv_7280: adv7280@21 {
 684                 compatible = "adi,adv7280";
 685                 adv,force-bt656-4;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&pinctrl_ipu1_csi0>;
 688                 reg = <0x21>;
 689                 status = "disabled";
 690
 691                 port {
 692                         adv7280_to_ipu1_csi0_mux: endpoint {
 693                                 bus-width = <8>;
 694                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 695                         };
 696                 };
 697         };
 698
 699         ov5640_csi_cam: ov5640_mipi@3c {
 700                 compatible = "ovti,ov5640";
 701                 AVDD-supply = <&reg_ov5640_2v8_a_vdd>;
 702                 DOVDD-supply = <&reg_ov5640_1v8_d_o_vdd>;
 703                 DVDD-supply = <&reg_ov5640_1v8_d_o_vdd>;
 704                 clock-names = "xclk";
 705                 clocks = <&clks IMX6QDL_CLK_CKO2>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&pinctrl_cam_mclk>;
 708                 /* These GPIOs are muxed with the iomuxc node */
 709                 powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
 710                 reg = <0x3c>;
 711                 reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 712                 status = "disabled";
 713
 714                 port {
 715                         ov5640_to_mipi_csi2: endpoint {
 716                                 clock-lanes = <0>;
 717                                 data-lanes = <1 2>;
 718                                 remote-endpoint = <&mipi_csi_from_ov5640>;
 719                         };
 720                 };
 721         };
 722 };
 723
 724 &ipu1_di1_disp1 {
 725         remote-endpoint = <&lcd_display_in>;
 726 };
 727
 728 &ldb {
 729         lvds-channel@0 {
 730                 port@4 {
 731                         reg = <4>;
 732
 733                         lvds0_out: endpoint {
 734                                 remote-endpoint = <&lvds_panel_in>;
 735                         };
 736                 };
 737         };
 738
 739         lvds-channel@1 {
 740                 fsl,data-mapping = "spwg";
 741                 fsl,data-width = <18>;
 742
 743                 port@4 {
 744                         reg = <4>;
 745
 746                         lvds1_out: endpoint {
 747                         };
 748                 };
 749         };
 750 };
 751
 752 &mipi_csi {
 753         #address-cells = <1>;
 754         #size-cells = <0>;
 755         status = "disabled";
 756
 757         port@0 {
 758                 reg = <0>;
 759
 760                 mipi_csi_from_ov5640: endpoint {
 761                         clock-lanes = <0>;
 762                         data-lanes = <1 2>;
 763                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 764                 };
 765         };
 766 };
 767
 768 &pwm1 {
 769         pinctrl-names = "default";
 770         pinctrl-0 = <&pinctrl_pwm1>;
 771         status = "disabled";
 772 };
 773
 774 &pwm2 {
 775         pinctrl-names = "default";
 776         pinctrl-0 = <&pinctrl_pwm2>;
 777         status = "disabled";
 778 };
 779
 780 &pwm3 {
 781         pinctrl-names = "default";
 782         pinctrl-0 = <&pinctrl_pwm3>;
 783         status = "disabled";
 784 };
 785
 786 &pwm4 {
 787         pinctrl-names = "default";
 788         pinctrl-0 = <&pinctrl_pwm4>;
 789         status = "disabled";
 790 };
 791
 792 &spdif {
 793         pinctrl-names = "default";
 794         pinctrl-0 = <&pinctrl_spdif>;
 795         status = "disabled";
 796 };
 797
 798 &ssi1 {
 799         status = "okay";
 800 };
 801
 802 &uart1 {
 803         fsl,dte-mode;
 804         pinctrl-names = "default";
 805         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 806         uart-has-rtscts;
 807         status = "disabled";
 808 };
 809
 810 &uart2 {
 811         fsl,dte-mode;
 812         pinctrl-names = "default";
 813         pinctrl-0 = <&pinctrl_uart2_dte>;
 814         uart-has-rtscts;
 815         status = "disabled";
 816 };
 817
 818 &uart4 {
 819         fsl,dte-mode;
 820         pinctrl-names = "default";
 821         pinctrl-0 = <&pinctrl_uart4_dte>;
 822         status = "disabled";
 823 };
 824
 825 &uart5 {
 826         fsl,dte-mode;
 827         pinctrl-names = "default";
 828         pinctrl-0 = <&pinctrl_uart5_dte>;
 829         status = "disabled";
 830 };
 831
 832 &usbotg {
 833         pinctrl-names = "default";
 834         pinctrl-0 = <&pinctrl_usbotg>;
 835         status = "disabled";
 836 };
 837
 838 /* MMC1 */
 839 &usdhc1 {
 840         bus-width = <8>;
 841         cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
 842         disable-wp;
 843         no-1-8-v;
 844         pinctrl-names = "default";
 845         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
 846         vqmmc-supply = <&reg_module_3v3>;
 847         status = "disabled";
 848 };
 849
 850 /* SD1 */
 851 &usdhc2 {
 852         bus-width = <4>;
 853         disable-wp;
 854         no-1-8-v;
 855         pinctrl-names = "default";
 856         pinctrl-0 = <&pinctrl_usdhc2>;
 857         vqmmc-supply = <&reg_module_3v3>;
 858         status = "disabled";
 859 };
 860
 861 /* eMMC */
 862 &usdhc3 {
 863         bus-width = <8>;
 864         no-1-8-v;
 865         non-removable;
 866         pinctrl-names = "default";
 867         pinctrl-0 = <&pinctrl_usdhc3>;
 868         vqmmc-supply = <&reg_module_3v3>;
 869         status = "okay";
 870 };
 871
 872 &weim {
 873         status = "disabled";
 874 };
 875
 876 &iomuxc {
 877         /* Mux the Apalis GPIOs */
 878         pinctrl-names = "default";
 879         pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
 880                      &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
 881                      &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
 882                      &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
 883                     >;
 884
 885         pinctrl_apalis_gpio1: apalisgpio1grp {
 886                 fsl,pins = <
 887                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 888                 >;
 889         };
 890
 891         pinctrl_apalis_gpio2: apalisgpio2grp {
 892                 fsl,pins = <
 893                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 894                 >;
 895         };
 896
 897         pinctrl_apalis_gpio3: apalisgpio3grp {
 898                 fsl,pins = <
 899                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 900                 >;
 901         };
 902
 903         pinctrl_apalis_gpio4: apalisgpio4grp {
 904                 fsl,pins = <
 905                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 906                 >;
 907         };
 908
 909         pinctrl_apalis_gpio5: apalisgpio5grp {
 910                 fsl,pins = <
 911                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 912                 >;
 913         };
 914
 915         pinctrl_apalis_gpio6: apalisgpio6grp {
 916                 fsl,pins = <
 917                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 918                 >;
 919         };
 920
 921         pinctrl_apalis_gpio7: apalisgpio7grp {
 922                 fsl,pins = <
 923                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 924                 >;
 925         };
 926
 927         pinctrl_apalis_gpio8: apalisgpio8grp {
 928                 fsl,pins = <
 929                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 930                 >;
 931         };
 932
 933         pinctrl_audmux: audmuxgrp {
 934                 fsl,pins = <
 935                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 936                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 937                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 938                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 939                 >;
 940         };
 941
 942         pinctrl_cam_mclk: cammclkgrp {
 943                 fsl,pins = <
 944                         /* CAM sys_mclk */
 945                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 946                 >;
 947         };
 948
 949         pinctrl_ecspi1: ecspi1grp {
 950                 fsl,pins = <
 951                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
 952                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
 953                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
 954                         /* SPI1 cs */
 955                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
 956                 >;
 957         };
 958
 959         pinctrl_ecspi2: ecspi2grp {
 960                 fsl,pins = <
 961                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 962                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 963                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 964                         /* SPI2 cs */
 965                         MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
 966                 >;
 967         };
 968
 969         pinctrl_enet: enetgrp {
 970                 fsl,pins = <
 971                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 972                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 973                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 974                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 975                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 976                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 977                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 978                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 979                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 980                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 981                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 982                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 983                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 984                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 985                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 986                         /* Ethernet PHY reset */
 987                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 988                         /* Ethernet PHY interrupt */
 989                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 990                 >;
 991         };
 992
 993         pinctrl_flexcan1_default: flexcan1defgrp {
 994                 fsl,pins = <
 995                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 996                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 997                 >;
 998         };
 999
1000         pinctrl_flexcan1_sleep: flexcan1slpgrp {
1001                 fsl,pins = <
1002                         MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
1003                         MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
1004                 >;
1005         };
1006
1007         pinctrl_flexcan2_default: flexcan2defgrp {
1008                 fsl,pins = <
1009                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
1010                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
1011                 >;
1012         };
1013         pinctrl_flexcan2_sleep: flexcan2slpgrp {
1014                 fsl,pins = <
1015                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
1016                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
1017                 >;
1018         };
1019
1020         pinctrl_gpio_bl_on: gpioblongrp {
1021                 fsl,pins = <
1022                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
1023                 >;
1024         };
1025
1026         pinctrl_gpio_keys: gpio1io04grp {
1027                 fsl,pins = <
1028                         /* Power button */
1029                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
1030                 >;
1031         };
1032
1033         pinctrl_hdmi_cec: hdmicecgrp {
1034                 fsl,pins = <
1035                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
1036                 >;
1037         };
1038
1039         pinctrl_hdmi_ddc: hdmiddcgrp {
1040                 fsl,pins = <
1041                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
1042                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
1043                 >;
1044         };
1045
1046         pinctrl_i2c1: i2c1grp {
1047                 fsl,pins = <
1048                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
1049                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
1050                 >;
1051         };
1052
1053         pinctrl_i2c1_gpio: i2c1gpiogrp {
1054                 fsl,pins = <
1055                         MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
1056                         MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
1057                 >;
1058         };
1059
1060         pinctrl_i2c2: i2c2grp {
1061                 fsl,pins = <
1062                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
1063                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
1064                 >;
1065         };
1066
1067         pinctrl_i2c2_gpio: i2c2gpiogrp {
1068                 fsl,pins = <
1069                         MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
1070                         MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
1071                 >;
1072         };
1073
1074         pinctrl_i2c3: i2c3grp {
1075                 fsl,pins = <
1076                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
1077                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
1078                 >;
1079         };
1080
1081         pinctrl_i2c3_gpio: i2c3gpiogrp {
1082                 fsl,pins = <
1083                         MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
1084                         MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
1085                 >;
1086         };
1087
1088         pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
1089                 fsl,pins = <
1090                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
1091                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
1092                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
1093                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
1094                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
1095                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
1096                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
1097                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
1098                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
1099                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
1100                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
1101                 >;
1102         };
1103
1104         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
1105                 fsl,pins = <
1106                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
1107                         /* DE */
1108                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
1109                         /* HSync */
1110                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
1111                         /* VSync */
1112                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
1113                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
1114                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
1115                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
1116                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
1117                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
1118                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
1119                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
1120                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
1121                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
1122                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
1123                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
1124                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
1125                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
1126                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
1127                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
1128                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
1129                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
1130                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
1131                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
1132                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
1133                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
1134                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
1135                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
1136                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
1137                 >;
1138         };
1139
1140         pinctrl_ipu2_vdac: ipu2vdacgrp {
1141                 fsl,pins = <
1142                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
1143                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
1144                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
1145                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
1146                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
1147                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
1148                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
1149                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
1150                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
1151                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
1152                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
1153                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
1154                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
1155                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
1156                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
1157                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
1158                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
1159                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
1160                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
1161                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
1162                 >;
1163         };
1164
1165         pinctrl_mmc_cd: mmccdgrp {
1166                 fsl,pins = <
1167                          /* MMC1 CD */
1168                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
1169                 >;
1170         };
1171
1172         pinctrl_pwm1: pwm1grp {
1173                 fsl,pins = <
1174                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
1175                 >;
1176         };
1177
1178         pinctrl_pwm2: pwm2grp {
1179                 fsl,pins = <
1180                         MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
1181                 >;
1182         };
1183
1184         pinctrl_pwm3: pwm3grp {
1185                 fsl,pins = <
1186                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1187                 >;
1188         };
1189
1190         pinctrl_pwm4: pwm4grp {
1191                 fsl,pins = <
1192                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
1193                 >;
1194         };
1195
1196         pinctrl_regulator_usbh_pwr: regusbhpwrgrp {
1197                 fsl,pins = <
1198                         /* USBH_EN */
1199                         MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
1200                 >;
1201         };
1202
1203         pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp {
1204                 fsl,pins = <
1205                         /* USBH_HUB_EN */
1206                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
1207                 >;
1208         };
1209
1210         pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp {
1211                 fsl,pins = <
1212                         /* USBO1 power en */
1213                         MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
1214                 >;
1215         };
1216
1217         pinctrl_reset_moci: resetmocigrp {
1218                 fsl,pins = <
1219                         /* RESET_MOCI control */
1220                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
1221                 >;
1222         };
1223
1224         pinctrl_sd_cd: sdcdgrp {
1225                 fsl,pins = <
1226                         /* SD1 CD */
1227                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
1228                 >;
1229         };
1230
1231         pinctrl_sgtl5000: sgtl5000grp {
1232                 fsl,pins = <
1233                         MX6QDL_PAD_GPIO_5__CCM_CLKO1    0x130b0
1234                 >;
1235         };
1236
1237         pinctrl_spdif: spdifgrp {
1238                 fsl,pins = <
1239                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
1240                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1241                 >;
1242         };
1243
1244         pinctrl_touch_int: touchintgrp {
1245                 fsl,pins = <
1246                         /* STMPE811 interrupt */
1247                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
1248                 >;
1249         };
1250
1251         /* Additional DTR, DSR, DCD */
1252         pinctrl_uart1_ctrl: uart1ctrlgrp {
1253                 fsl,pins = <
1254                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
1255                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
1256                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
1257                 >;
1258         };
1259
1260         pinctrl_uart1_dce: uart1dcegrp {
1261                 fsl,pins = <
1262                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1263                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1264                 >;
1265         };
1266
1267         /* DTE mode */
1268         pinctrl_uart1_dte: uart1dtegrp {
1269                 fsl,pins = <
1270                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
1271                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
1272                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
1273                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
1274                 >;
1275         };
1276
1277         pinctrl_uart2_dce: uart2dcegrp {
1278                 fsl,pins = <
1279                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
1280                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
1281                 >;
1282         };
1283
1284         /* DTE mode */
1285         pinctrl_uart2_dte: uart2dtegrp {
1286                 fsl,pins = <
1287                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
1288                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
1289                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
1290                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
1291                 >;
1292         };
1293
1294         pinctrl_uart4_dce: uart4dcegrp {
1295                 fsl,pins = <
1296                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1297                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1298                 >;
1299         };
1300
1301         /* DTE mode */
1302         pinctrl_uart4_dte: uart4dtegrp {
1303                 fsl,pins = <
1304                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
1305                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
1306                 >;
1307         };
1308
1309         pinctrl_uart5_dce: uart5dcegrp {
1310                 fsl,pins = <
1311                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
1312                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
1313                 >;
1314         };
1315
1316         /* DTE mode */
1317         pinctrl_uart5_dte: uart5dtegrp {
1318                 fsl,pins = <
1319                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
1320                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
1321                 >;
1322         };
1323
1324         pinctrl_usbotg: usbotggrp {
1325                 fsl,pins = <
1326                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1327                 >;
1328         };
1329
1330         pinctrl_usdhc1_4bit: usdhc1-4bitgrp {
1331                 fsl,pins = <
1332                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
1333                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
1334                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
1335                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
1336                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
1337                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
1338                 >;
1339         };
1340
1341         pinctrl_usdhc1_8bit: usdhc1-8bitgrp {
1342                 fsl,pins = <
1343                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
1344                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
1345                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
1346                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
1347                 >;
1348         };
1349
1350         pinctrl_usdhc2: usdhc2grp {
1351                 fsl,pins = <
1352                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
1353                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
1354                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
1355                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
1356                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
1357                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
1358                 >;
1359         };
1360
1361         pinctrl_usdhc3: usdhc3grp {
1362                 fsl,pins = <
1363                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
1364                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
1365                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1366                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1367                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1368                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1369                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1370                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1371                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1372                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1373                         /* eMMC reset */
1374                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
1375                 >;
1376         };
1377 };