1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
4 * Author: John Crispin <john@phrozen.org>
5 * Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt2701-clk.h>
12 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
13 #include <dt-bindings/power/mt2701-power.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/memory/mt2701-larb-port.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
18 #include <dt-bindings/thermal/thermal.h>
21 compatible = "mediatek,mt7623";
22 interrupt-parent = <&sysirq>;
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
74 enable-method = "mediatek,mt6589-smp";
78 compatible = "arm,cortex-a7";
80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
81 <&apmixedsys CLK_APMIXED_MAINPLL>;
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
85 clock-frequency = <1300000000>;
90 compatible = "arm,cortex-a7";
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
93 <&apmixedsys CLK_APMIXED_MAINPLL>;
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
97 clock-frequency = <1300000000>;
102 compatible = "arm,cortex-a7";
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
105 <&apmixedsys CLK_APMIXED_MAINPLL>;
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
114 compatible = "arm,cortex-a7";
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
117 <&apmixedsys CLK_APMIXED_MAINPLL>;
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
126 compatible = "arm,cortex-a7-pmu";
127 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
130 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
134 system_clk: dummy13m {
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
159 thermal-sensors = <&thermal 0>;
162 cpu_passive: cpu-passive {
163 temperature = <47000>;
168 cpu_active: cpu-active {
169 temperature = <67000>;
175 temperature = <87000>;
181 temperature = <107000>;
189 trip = <&cpu_passive>;
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 trip = <&cpu_active>;
195 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
200 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
207 compatible = "arm,armv7-timer";
208 interrupt-parent = <&gic>;
209 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
210 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
213 clock-frequency = <13000000>;
214 arm,cpu-registers-not-fw-configured;
217 topckgen: syscon@10000000 {
218 compatible = "mediatek,mt7623-topckgen",
219 "mediatek,mt2701-topckgen",
221 reg = <0 0x10000000 0 0x1000>;
225 infracfg: syscon@10001000 {
226 compatible = "mediatek,mt7623-infracfg",
227 "mediatek,mt2701-infracfg",
229 reg = <0 0x10001000 0 0x1000>;
234 pericfg: syscon@10003000 {
235 compatible = "mediatek,mt7623-pericfg",
236 "mediatek,mt2701-pericfg",
238 reg = <0 0x10003000 0 0x1000>;
243 pio: pinctrl@10005000 {
244 compatible = "mediatek,mt7623-pinctrl";
245 reg = <0 0x1000b000 0 0x1000>;
246 mediatek,pctl-regmap = <&syscfg_pctl_a>;
250 interrupt-controller;
251 interrupt-parent = <&gic>;
252 #interrupt-cells = <2>;
253 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
257 syscfg_pctl_a: syscfg@10005000 {
258 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
259 reg = <0 0x10005000 0 0x1000>;
262 scpsys: scpsys@10006000 {
263 compatible = "mediatek,mt7623-scpsys",
264 "mediatek,mt2701-scpsys",
266 #power-domain-cells = <1>;
267 reg = <0 0x10006000 0 0x1000>;
268 infracfg = <&infracfg>;
269 clocks = <&topckgen CLK_TOP_MM_SEL>,
270 <&topckgen CLK_TOP_MFG_SEL>,
271 <&topckgen CLK_TOP_ETHIF_SEL>;
272 clock-names = "mm", "mfg", "ethif";
275 watchdog: watchdog@10007000 {
276 compatible = "mediatek,mt7623-wdt",
277 "mediatek,mt6589-wdt";
278 reg = <0 0x10007000 0 0x100>;
281 timer: timer@10008000 {
282 compatible = "mediatek,mt7623-timer",
283 "mediatek,mt6577-timer";
284 reg = <0 0x10008000 0 0x80>;
285 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
286 clocks = <&system_clk>, <&rtc32k>;
287 clock-names = "system-clk", "rtc-clk";
290 smi_common: smi@1000c000 {
291 compatible = "mediatek,mt7623-smi-common",
292 "mediatek,mt2701-smi-common";
293 reg = <0 0x1000c000 0 0x1000>;
294 clocks = <&infracfg CLK_INFRA_SMI>,
295 <&mmsys CLK_MM_SMI_COMMON>,
296 <&infracfg CLK_INFRA_SMI>;
297 clock-names = "apb", "smi", "async";
298 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
301 pwrap: pwrap@1000d000 {
302 compatible = "mediatek,mt7623-pwrap",
303 "mediatek,mt2701-pwrap";
304 reg = <0 0x1000d000 0 0x1000>;
306 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
307 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
308 reset-names = "pwrap";
309 clocks = <&infracfg CLK_INFRA_PMICSPI>,
310 <&infracfg CLK_INFRA_PMICWRAP>;
311 clock-names = "spi", "wrap";
315 compatible = "mediatek,mt7623-cir";
316 reg = <0 0x10013000 0 0x1000>;
317 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
318 clocks = <&infracfg CLK_INFRA_IRRX>;
323 sysirq: interrupt-controller@10200100 {
324 compatible = "mediatek,mt7623-sysirq",
325 "mediatek,mt6577-sysirq";
326 interrupt-controller;
327 #interrupt-cells = <3>;
328 interrupt-parent = <&gic>;
329 reg = <0 0x10200100 0 0x1c>;
332 iommu: mmsys_iommu@10205000 {
333 compatible = "mediatek,mt7623-m4u",
334 "mediatek,mt2701-m4u";
335 reg = <0 0x10205000 0 0x1000>;
336 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
337 clocks = <&infracfg CLK_INFRA_M4U>;
338 clock-names = "bclk";
339 mediatek,larbs = <&larb0 &larb1 &larb2>;
343 efuse: efuse@10206000 {
344 compatible = "mediatek,mt7623-efuse",
345 "mediatek,mt8173-efuse";
346 reg = <0 0x10206000 0 0x1000>;
347 #address-cells = <1>;
349 thermal_calibration_data: calib@424 {
354 apmixedsys: syscon@10209000 {
355 compatible = "mediatek,mt7623-apmixedsys",
356 "mediatek,mt2701-apmixedsys",
358 reg = <0 0x10209000 0 0x1000>;
363 compatible = "mediatek,mt7623-rng";
364 reg = <0 0x1020f000 0 0x1000>;
365 clocks = <&infracfg CLK_INFRA_TRNG>;
369 gic: interrupt-controller@10211000 {
370 compatible = "arm,cortex-a7-gic";
371 interrupt-controller;
372 #interrupt-cells = <3>;
373 interrupt-parent = <&gic>;
374 reg = <0 0x10211000 0 0x1000>,
375 <0 0x10212000 0 0x2000>,
376 <0 0x10214000 0 0x2000>,
377 <0 0x10216000 0 0x2000>;
380 auxadc: adc@11001000 {
381 compatible = "mediatek,mt7623-auxadc",
382 "mediatek,mt2701-auxadc";
383 reg = <0 0x11001000 0 0x1000>;
384 clocks = <&pericfg CLK_PERI_AUXADC>;
385 clock-names = "main";
386 #io-channel-cells = <1>;
389 uart0: serial@11002000 {
390 compatible = "mediatek,mt7623-uart",
391 "mediatek,mt6577-uart";
392 reg = <0 0x11002000 0 0x400>;
393 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
394 clocks = <&pericfg CLK_PERI_UART0_SEL>,
395 <&pericfg CLK_PERI_UART0>;
396 clock-names = "baud", "bus";
400 uart1: serial@11003000 {
401 compatible = "mediatek,mt7623-uart",
402 "mediatek,mt6577-uart";
403 reg = <0 0x11003000 0 0x400>;
404 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
405 clocks = <&pericfg CLK_PERI_UART1_SEL>,
406 <&pericfg CLK_PERI_UART1>;
407 clock-names = "baud", "bus";
411 uart2: serial@11004000 {
412 compatible = "mediatek,mt7623-uart",
413 "mediatek,mt6577-uart";
414 reg = <0 0x11004000 0 0x400>;
415 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
416 clocks = <&pericfg CLK_PERI_UART2_SEL>,
417 <&pericfg CLK_PERI_UART2>;
418 clock-names = "baud", "bus";
422 uart3: serial@11005000 {
423 compatible = "mediatek,mt7623-uart",
424 "mediatek,mt6577-uart";
425 reg = <0 0x11005000 0 0x400>;
426 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
427 clocks = <&pericfg CLK_PERI_UART3_SEL>,
428 <&pericfg CLK_PERI_UART3>;
429 clock-names = "baud", "bus";
434 compatible = "mediatek,mt7623-pwm";
435 reg = <0 0x11006000 0 0x1000>;
437 clocks = <&topckgen CLK_TOP_PWM_SEL>,
438 <&pericfg CLK_PERI_PWM>,
439 <&pericfg CLK_PERI_PWM1>,
440 <&pericfg CLK_PERI_PWM2>,
441 <&pericfg CLK_PERI_PWM3>,
442 <&pericfg CLK_PERI_PWM4>,
443 <&pericfg CLK_PERI_PWM5>;
444 clock-names = "top", "main", "pwm1", "pwm2",
445 "pwm3", "pwm4", "pwm5";
450 compatible = "mediatek,mt7623-i2c",
451 "mediatek,mt6577-i2c";
452 reg = <0 0x11007000 0 0x70>,
453 <0 0x11000200 0 0x80>;
454 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
456 clocks = <&pericfg CLK_PERI_I2C0>,
457 <&pericfg CLK_PERI_AP_DMA>;
458 clock-names = "main", "dma";
459 #address-cells = <1>;
465 compatible = "mediatek,mt7623-i2c",
466 "mediatek,mt6577-i2c";
467 reg = <0 0x11008000 0 0x70>,
468 <0 0x11000280 0 0x80>;
469 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
471 clocks = <&pericfg CLK_PERI_I2C1>,
472 <&pericfg CLK_PERI_AP_DMA>;
473 clock-names = "main", "dma";
474 #address-cells = <1>;
480 compatible = "mediatek,mt7623-i2c",
481 "mediatek,mt6577-i2c";
482 reg = <0 0x11009000 0 0x70>,
483 <0 0x11000300 0 0x80>;
484 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
486 clocks = <&pericfg CLK_PERI_I2C2>,
487 <&pericfg CLK_PERI_AP_DMA>;
488 clock-names = "main", "dma";
489 #address-cells = <1>;
495 compatible = "mediatek,mt7623-spi",
496 "mediatek,mt2701-spi";
497 #address-cells = <1>;
499 reg = <0 0x1100a000 0 0x100>;
500 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
501 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
502 <&topckgen CLK_TOP_SPI0_SEL>,
503 <&pericfg CLK_PERI_SPI0>;
504 clock-names = "parent-clk", "sel-clk", "spi-clk";
508 thermal: thermal@1100b000 {
509 #thermal-sensor-cells = <1>;
510 compatible = "mediatek,mt7623-thermal",
511 "mediatek,mt2701-thermal";
512 reg = <0 0x1100b000 0 0x1000>;
513 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
514 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
515 clock-names = "therm", "auxadc";
516 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
517 reset-names = "therm";
518 mediatek,auxadc = <&auxadc>;
519 mediatek,apmixedsys = <&apmixedsys>;
520 nvmem-cells = <&thermal_calibration_data>;
521 nvmem-cell-names = "calibration-data";
524 btif: serial@1100c000 {
525 compatible = "mediatek,mt7623-btif",
527 reg = <0 0x1100c000 0 0x1000>;
528 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
529 clocks = <&pericfg CLK_PERI_BTIF>;
530 clock-names = "main";
536 nandc: nfi@1100d000 {
537 compatible = "mediatek,mt7623-nfc",
538 "mediatek,mt2701-nfc";
539 reg = <0 0x1100d000 0 0x1000>;
540 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
541 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
542 clocks = <&pericfg CLK_PERI_NFI>,
543 <&pericfg CLK_PERI_NFI_PAD>;
544 clock-names = "nfi_clk", "pad_clk";
547 #address-cells = <1>;
552 compatible = "mediatek,mt7623-ecc",
553 "mediatek,mt2701-ecc";
554 reg = <0 0x1100e000 0 0x1000>;
555 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
556 clocks = <&pericfg CLK_PERI_NFI_ECC>;
557 clock-names = "nfiecc_clk";
561 nor_flash: spi@11014000 {
562 compatible = "mediatek,mt7623-nor",
563 "mediatek,mt8173-nor";
564 reg = <0 0x11014000 0 0x1000>;
565 clocks = <&pericfg CLK_PERI_FLASH>,
566 <&topckgen CLK_TOP_FLASH_SEL>;
567 clock-names = "spi", "sf";
568 #address-cells = <1>;
574 compatible = "mediatek,mt7623-spi",
575 "mediatek,mt2701-spi";
576 #address-cells = <1>;
578 reg = <0 0x11016000 0 0x100>;
579 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
580 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
581 <&topckgen CLK_TOP_SPI1_SEL>,
582 <&pericfg CLK_PERI_SPI1>;
583 clock-names = "parent-clk", "sel-clk", "spi-clk";
588 compatible = "mediatek,mt7623-spi",
589 "mediatek,mt2701-spi";
590 #address-cells = <1>;
592 reg = <0 0x11017000 0 0x1000>;
593 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
594 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
595 <&topckgen CLK_TOP_SPI2_SEL>,
596 <&pericfg CLK_PERI_SPI2>;
597 clock-names = "parent-clk", "sel-clk", "spi-clk";
601 audsys: clock-controller@11220000 {
602 compatible = "mediatek,mt7623-audsys",
603 "mediatek,mt2701-audsys",
605 reg = <0 0x11220000 0 0x2000>;
608 afe: audio-controller {
609 compatible = "mediatek,mt7623-audio",
610 "mediatek,mt2701-audio";
611 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
612 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
613 interrupt-names = "afe", "asys";
614 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
616 clocks = <&infracfg CLK_INFRA_AUDIO>,
617 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
618 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
619 <&topckgen CLK_TOP_AUD_48K_TIMING>,
620 <&topckgen CLK_TOP_AUD_44K_TIMING>,
621 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
622 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
623 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
624 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
625 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
626 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
627 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
628 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
629 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
630 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
631 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
632 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
633 <&audsys CLK_AUD_I2SO1>,
634 <&audsys CLK_AUD_I2SO2>,
635 <&audsys CLK_AUD_I2SO3>,
636 <&audsys CLK_AUD_I2SO4>,
637 <&audsys CLK_AUD_I2SIN1>,
638 <&audsys CLK_AUD_I2SIN2>,
639 <&audsys CLK_AUD_I2SIN3>,
640 <&audsys CLK_AUD_I2SIN4>,
641 <&audsys CLK_AUD_ASRCO1>,
642 <&audsys CLK_AUD_ASRCO2>,
643 <&audsys CLK_AUD_ASRCO3>,
644 <&audsys CLK_AUD_ASRCO4>,
645 <&audsys CLK_AUD_AFE>,
646 <&audsys CLK_AUD_AFE_CONN>,
647 <&audsys CLK_AUD_A1SYS>,
648 <&audsys CLK_AUD_A2SYS>,
649 <&audsys CLK_AUD_AFE_MRGIF>;
651 clock-names = "infra_sys_audio_clk",
652 "top_audio_mux1_sel",
653 "top_audio_mux2_sel",
654 "top_audio_a1sys_hp",
655 "top_audio_a2sys_hp",
686 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
687 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
688 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
689 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
690 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
691 <&topckgen CLK_TOP_AUD2PLL_90M>;
692 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
697 compatible = "mediatek,mt7623-mmc",
698 "mediatek,mt2701-mmc";
699 reg = <0 0x11230000 0 0x1000>;
700 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
701 clocks = <&pericfg CLK_PERI_MSDC30_0>,
702 <&topckgen CLK_TOP_MSDC30_0_SEL>;
703 clock-names = "source", "hclk";
708 compatible = "mediatek,mt7623-mmc",
709 "mediatek,mt2701-mmc";
710 reg = <0 0x11240000 0 0x1000>;
711 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
712 clocks = <&pericfg CLK_PERI_MSDC30_1>,
713 <&topckgen CLK_TOP_MSDC30_1_SEL>;
714 clock-names = "source", "hclk";
718 g3dsys: syscon@13000000 {
719 compatible = "mediatek,mt7623-g3dsys",
720 "mediatek,mt2701-g3dsys",
722 reg = <0 0x13000000 0 0x200>;
727 mmsys: syscon@14000000 {
728 compatible = "mediatek,mt7623-mmsys",
729 "mediatek,mt2701-mmsys",
731 reg = <0 0x14000000 0 0x1000>;
735 larb0: larb@14010000 {
736 compatible = "mediatek,mt7623-smi-larb",
737 "mediatek,mt2701-smi-larb";
738 reg = <0 0x14010000 0 0x1000>;
739 mediatek,smi = <&smi_common>;
740 mediatek,larb-id = <0>;
741 clocks = <&mmsys CLK_MM_SMI_LARB0>,
742 <&mmsys CLK_MM_SMI_LARB0>;
743 clock-names = "apb", "smi";
744 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
747 imgsys: syscon@15000000 {
748 compatible = "mediatek,mt7623-imgsys",
749 "mediatek,mt2701-imgsys",
751 reg = <0 0x15000000 0 0x1000>;
755 larb2: larb@15001000 {
756 compatible = "mediatek,mt7623-smi-larb",
757 "mediatek,mt2701-smi-larb";
758 reg = <0 0x15001000 0 0x1000>;
759 mediatek,smi = <&smi_common>;
760 mediatek,larb-id = <2>;
761 clocks = <&imgsys CLK_IMG_SMI_COMM>,
762 <&imgsys CLK_IMG_SMI_COMM>;
763 clock-names = "apb", "smi";
764 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
767 jpegdec: jpegdec@15004000 {
768 compatible = "mediatek,mt7623-jpgdec",
769 "mediatek,mt2701-jpgdec";
770 reg = <0 0x15004000 0 0x1000>;
771 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
772 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
773 <&imgsys CLK_IMG_JPGDEC>;
774 clock-names = "jpgdec-smi",
776 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
777 mediatek,larb = <&larb2>;
778 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
779 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
782 vdecsys: syscon@16000000 {
783 compatible = "mediatek,mt7623-vdecsys",
784 "mediatek,mt2701-vdecsys",
786 reg = <0 0x16000000 0 0x1000>;
790 larb1: larb@16010000 {
791 compatible = "mediatek,mt7623-smi-larb",
792 "mediatek,mt2701-smi-larb";
793 reg = <0 0x16010000 0 0x1000>;
794 mediatek,smi = <&smi_common>;
795 mediatek,larb-id = <1>;
796 clocks = <&vdecsys CLK_VDEC_CKGEN>,
797 <&vdecsys CLK_VDEC_LARB>;
798 clock-names = "apb", "smi";
799 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
802 hifsys: syscon@1a000000 {
803 compatible = "mediatek,mt7623-hifsys",
804 "mediatek,mt2701-hifsys",
806 reg = <0 0x1a000000 0 0x1000>;
811 pcie: pcie@1a140000 {
812 compatible = "mediatek,mt7623-pcie";
814 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
815 <0 0x1a142000 0 0x1000>, /* Port0 registers */
816 <0 0x1a143000 0 0x1000>, /* Port1 registers */
817 <0 0x1a144000 0 0x1000>; /* Port2 registers */
818 reg-names = "subsys", "port0", "port1", "port2";
819 #address-cells = <3>;
821 #interrupt-cells = <1>;
822 interrupt-map-mask = <0xf800 0 0 0>;
823 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
824 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
825 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
826 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
827 <&hifsys CLK_HIFSYS_PCIE0>,
828 <&hifsys CLK_HIFSYS_PCIE1>,
829 <&hifsys CLK_HIFSYS_PCIE2>;
830 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
831 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
832 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
833 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
834 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
835 phys = <&pcie0_port PHY_TYPE_PCIE>,
836 <&pcie1_port PHY_TYPE_PCIE>,
837 <&u3port1 PHY_TYPE_PCIE>;
838 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
839 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
840 bus-range = <0x00 0xff>;
842 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
843 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
846 reg = <0x0000 0 0 0 0>;
847 #address-cells = <3>;
849 #interrupt-cells = <1>;
850 interrupt-map-mask = <0 0 0 0>;
851 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
857 reg = <0x0800 0 0 0 0>;
858 #address-cells = <3>;
860 #interrupt-cells = <1>;
861 interrupt-map-mask = <0 0 0 0>;
862 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
868 reg = <0x1000 0 0 0 0>;
869 #address-cells = <3>;
871 #interrupt-cells = <1>;
872 interrupt-map-mask = <0 0 0 0>;
873 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
879 pcie0_phy: pcie-phy@1a149000 {
880 compatible = "mediatek,generic-tphy-v1";
881 reg = <0 0x1a149000 0 0x0700>;
882 #address-cells = <2>;
887 pcie0_port: pcie-phy@1a149900 {
888 reg = <0 0x1a149900 0 0x0700>;
896 pcie1_phy: pcie-phy@1a14a000 {
897 compatible = "mediatek,generic-tphy-v1";
898 reg = <0 0x1a14a000 0 0x0700>;
899 #address-cells = <2>;
904 pcie1_port: pcie-phy@1a14a900 {
905 reg = <0 0x1a14a900 0 0x0700>;
914 compatible = "mediatek,mt7623-xhci",
915 "mediatek,mt8173-xhci";
916 reg = <0 0x1a1c0000 0 0x1000>,
917 <0 0x1a1c4700 0 0x0100>;
918 reg-names = "mac", "ippc";
919 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
920 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
921 <&topckgen CLK_TOP_ETHIF_SEL>;
922 clock-names = "sys_ck", "ref_ck";
923 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
924 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
928 u3phy1: usb-phy@1a1c4000 {
929 compatible = "mediatek,mt7623-u3phy",
930 "mediatek,mt2701-u3phy";
931 reg = <0 0x1a1c4000 0 0x0700>;
932 #address-cells = <2>;
937 u2port0: usb-phy@1a1c4800 {
938 reg = <0 0x1a1c4800 0 0x0100>;
939 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
945 u3port0: usb-phy@1a1c4900 {
946 reg = <0 0x1a1c4900 0 0x0700>;
955 compatible = "mediatek,mt7623-xhci",
956 "mediatek,mt8173-xhci";
957 reg = <0 0x1a240000 0 0x1000>,
958 <0 0x1a244700 0 0x0100>;
959 reg-names = "mac", "ippc";
960 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
961 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
962 <&topckgen CLK_TOP_ETHIF_SEL>;
963 clock-names = "sys_ck", "ref_ck";
964 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
965 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
969 u3phy2: usb-phy@1a244000 {
970 compatible = "mediatek,mt7623-u3phy",
971 "mediatek,mt2701-u3phy";
972 reg = <0 0x1a244000 0 0x0700>;
973 #address-cells = <2>;
978 u2port1: usb-phy@1a244800 {
979 reg = <0 0x1a244800 0 0x0100>;
980 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
986 u3port1: usb-phy@1a244900 {
987 reg = <0 0x1a244900 0 0x0700>;
995 ethsys: syscon@1b000000 {
996 compatible = "mediatek,mt7623-ethsys",
997 "mediatek,mt2701-ethsys",
999 reg = <0 0x1b000000 0 0x1000>;
1004 hsdma: dma-controller@1b007000 {
1005 compatible = "mediatek,mt7623-hsdma";
1006 reg = <0 0x1b007000 0 0x1000>;
1007 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
1008 clocks = <ðsys CLK_ETHSYS_HSDMA>;
1009 clock-names = "hsdma";
1010 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1014 eth: ethernet@1b100000 {
1015 compatible = "mediatek,mt7623-eth",
1016 "mediatek,mt2701-eth",
1018 reg = <0 0x1b100000 0 0x20000>;
1019 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
1020 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
1021 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1022 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
1023 <ðsys CLK_ETHSYS_ESW>,
1024 <ðsys CLK_ETHSYS_GP1>,
1025 <ðsys CLK_ETHSYS_GP2>,
1026 <&apmixedsys CLK_APMIXED_TRGPLL>;
1027 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
1028 resets = <ðsys MT2701_ETHSYS_FE_RST>,
1029 <ðsys MT2701_ETHSYS_GMAC_RST>,
1030 <ðsys MT2701_ETHSYS_PPE_RST>;
1031 reset-names = "fe", "gmac", "ppe";
1032 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1033 mediatek,ethsys = <ðsys>;
1034 mediatek,pctl = <&syscfg_pctl_a>;
1035 #address-cells = <1>;
1037 status = "disabled";
1040 crypto: crypto@1b240000 {
1041 compatible = "mediatek,eip97-crypto";
1042 reg = <0 0x1b240000 0 0x20000>;
1043 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
1044 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
1045 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
1046 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
1047 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
1048 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
1049 clock-names = "cryp";
1050 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1051 status = "disabled";
1054 bdpsys: syscon@1c000000 {
1055 compatible = "mediatek,mt7623-bdpsys",
1056 "mediatek,mt2701-bdpsys",
1058 reg = <0 0x1c000000 0 0x1000>;
1064 cir_pins_a:cir-default {
1066 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
1071 i2c0_pins_a: i2c0-default {
1073 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
1074 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
1079 i2c1_pins_a: i2c1-default {
1081 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
1082 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
1087 i2c1_pins_b: i2c1-alt {
1089 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1090 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1095 i2c2_pins_a: i2c2-default {
1097 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1098 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1103 i2c2_pins_b: i2c2-alt {
1105 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1106 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1111 i2s0_pins_a: i2s0-default {
1113 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1114 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1115 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1116 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1117 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1118 drive-strength = <MTK_DRIVE_12mA>;
1123 i2s1_pins_a: i2s1-default {
1125 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1126 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1127 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1128 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1129 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1130 drive-strength = <MTK_DRIVE_12mA>;
1135 key_pins_a: keys-alt {
1137 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1138 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1143 led_pins_a: leds-alt {
1145 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1146 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1147 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1151 mmc0_pins_default: mmc0default {
1153 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1154 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1155 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1156 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1157 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1158 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1159 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1160 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1161 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1167 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1172 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1177 mmc0_pins_uhs: mmc0 {
1179 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1180 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1181 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1182 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1183 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1184 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1185 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1186 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1187 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1189 drive-strength = <MTK_DRIVE_2mA>;
1190 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1194 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1195 drive-strength = <MTK_DRIVE_2mA>;
1196 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1200 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1205 mmc1_pins_default: mmc1default {
1207 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1208 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1209 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1210 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1211 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1213 drive-strength = <MTK_DRIVE_4mA>;
1214 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1218 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1220 drive-strength = <MTK_DRIVE_4mA>;
1224 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1230 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1235 mmc1_pins_uhs: mmc1 {
1237 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1238 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1239 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1240 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1241 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1243 drive-strength = <MTK_DRIVE_4mA>;
1244 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1248 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1249 drive-strength = <MTK_DRIVE_4mA>;
1250 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1254 nand_pins_default: nanddefault {
1256 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1257 drive-strength = <MTK_DRIVE_8mA>;
1258 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1262 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1263 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1264 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1265 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1266 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1267 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1268 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1269 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1270 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1272 drive-strength = <MTK_DRIVE_8mA>;
1277 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1278 drive-strength = <MTK_DRIVE_8mA>;
1279 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1283 pcie_default: pcie_pin_default {
1285 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1286 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1291 pwm_pins_a: pwm-default {
1293 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1294 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1295 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1296 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1297 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1301 spi0_pins_a: spi0-default {
1303 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1304 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1305 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1306 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1311 spi1_pins_a: spi1-default {
1313 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1314 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1315 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1316 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1320 spi2_pins_a: spi2-default {
1322 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1323 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1324 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1325 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1329 uart0_pins_a: uart0-default {
1331 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1332 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1336 uart1_pins_a: uart1-default {
1338 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1339 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1343 uart2_pins_a: uart2-default {
1345 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1346 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1350 uart2_pins_b: uart2-alt {
1352 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1353 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;