1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
41 compatible = "arm,cortex-a7";
47 intc: interrupt-controller@40021000 {
48 compatible = "arm,cortex-a7-gic";
49 #interrupt-cells = <3>;
51 reg = <0x40021000 0x1000>,
56 compatible = "fixed-clock";
57 clock-frequency = <32768>;
58 clock-output-names = "rosc";
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-output-names = "sosc";
70 compatible = "fixed-clock";
71 clock-frequency = <16000000>;
72 clock-output-names = "sirc";
77 compatible = "fixed-clock";
78 clock-frequency = <48000000>;
79 clock-output-names = "firc";
84 compatible = "fixed-clock";
85 clock-frequency = <480000000>;
86 clock-output-names = "upll";
91 compatible = "fixed-clock";
92 clock-frequency = <480000000>;
93 clock-output-names = "mpll";
97 ahbbridge0: bus@40000000 {
98 compatible = "simple-bus";
101 reg = <0x40000000 0x800000>;
104 crypto: crypto@40240000 {
105 compatible = "fsl,sec-v4.0";
106 #address-cells = <1>;
108 reg = <0x40240000 0x10000>;
109 ranges = <0 0x40240000 0x10000>;
110 clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
111 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
112 clock-names = "aclk", "ipg";
115 compatible = "fsl,sec-v4.0-job-ring";
116 reg = <0x1000 0x1000>;
117 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
121 compatible = "fsl,sec-v4.0-job-ring";
122 reg = <0x2000 0x1000>;
123 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
127 lpuart4: serial@402d0000 {
128 compatible = "fsl,imx7ulp-lpuart";
129 reg = <0x402d0000 0x1000>;
130 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
133 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
134 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
135 assigned-clock-rates = <24000000>;
139 lpuart5: serial@402e0000 {
140 compatible = "fsl,imx7ulp-lpuart";
141 reg = <0x402e0000 0x1000>;
142 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
145 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
146 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
147 assigned-clock-rates = <48000000>;
152 compatible = "fsl,imx7ulp-pwm";
153 reg = <0x40250000 0x1000>;
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
162 compatible = "fsl,imx7ulp-tpm";
163 reg = <0x40260000 0x1000>;
164 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
166 <&pcc2 IMX7ULP_CLK_LPTPM5>;
167 clock-names = "ipg", "per";
170 usbotg1: usb@40330000 {
171 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
172 reg = <0x40330000 0x200>;
173 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&pcc2 IMX7ULP_CLK_USB0>;
176 fsl,usbmisc = <&usbmisc1 0>;
177 ahb-burst-config = <0x0>;
178 tx-burst-size-dword = <0x8>;
179 rx-burst-size-dword = <0x8>;
183 usbmisc1: usbmisc@40330200 {
184 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
186 reg = <0x40330200 0x200>;
189 usbphy1: usb-phy@0x40350000 {
190 compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
191 reg = <0x40350000 0x1000>;
192 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
197 usdhc0: mmc@40370000 {
198 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
199 reg = <0x40370000 0x10000>;
200 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
202 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
203 <&pcc2 IMX7ULP_CLK_USDHC0>;
204 clock-names ="ipg", "ahb", "per";
205 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
206 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
208 fsl,tuning-start-tap = <20>;
209 fsl,tuning-step= <2>;
213 usdhc1: mmc@40380000 {
214 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
215 reg = <0x40380000 0x10000>;
216 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
218 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
219 <&pcc2 IMX7ULP_CLK_USDHC1>;
220 clock-names ="ipg", "ahb", "per";
221 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
222 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
224 fsl,tuning-start-tap = <20>;
225 fsl,tuning-step= <2>;
229 scg1: clock-controller@403e0000 {
230 compatible = "fsl,imx7ulp-scg1";
231 reg = <0x403e0000 0x10000>;
232 clocks = <&rosc>, <&sosc>, <&sirc>,
233 <&firc>, <&upll>, <&mpll>;
234 clock-names = "rosc", "sosc", "sirc",
235 "firc", "upll", "mpll";
239 pcc2: clock-controller@403f0000 {
240 compatible = "fsl,imx7ulp-pcc2";
241 reg = <0x403f0000 0x10000>;
243 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
244 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
245 <&scg1 IMX7ULP_CLK_DDR_DIV>,
246 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
247 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
248 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
249 <&scg1 IMX7ULP_CLK_UPLL>,
250 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
251 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
252 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
253 <&scg1 IMX7ULP_CLK_ROSC>,
254 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
255 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
256 "apll_pfd2", "apll_pfd1", "apll_pfd0",
257 "upll", "sosc_bus_clk", "mpll",
258 "firc_bus_clk", "rosc", "spll_bus_clk";
259 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
260 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
263 smc1: clock-controller@40410000 {
264 compatible = "fsl,imx7ulp-smc1";
265 reg = <0x40410000 0x1000>;
267 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
268 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
269 clock-names = "divcore", "hsrun_divcore";
272 pcc3: clock-controller@40b30000 {
273 compatible = "fsl,imx7ulp-pcc3";
274 reg = <0x40b30000 0x10000>;
276 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
277 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
278 <&scg1 IMX7ULP_CLK_DDR_DIV>,
279 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
280 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
281 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
282 <&scg1 IMX7ULP_CLK_UPLL>,
283 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
284 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
285 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
286 <&scg1 IMX7ULP_CLK_ROSC>,
287 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
288 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
289 "apll_pfd2", "apll_pfd1", "apll_pfd0",
290 "upll", "sosc_bus_clk", "mpll",
291 "firc_bus_clk", "rosc", "spll_bus_clk";
295 ahbbridge1: bus@40800000 {
296 compatible = "simple-bus";
297 #address-cells = <1>;
299 reg = <0x40800000 0x800000>;
302 lpi2c6: i2c@40a40000 {
303 compatible = "fsl,imx7ulp-lpi2c";
304 reg = <0x40a40000 0x10000>;
305 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
308 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
309 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
310 assigned-clock-rates = <48000000>;
314 lpi2c7: i2c@40a50000 {
315 compatible = "fsl,imx7ulp-lpi2c";
316 reg = <0x40a50000 0x10000>;
317 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
320 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
321 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
322 assigned-clock-rates = <48000000>;
326 lpuart6: serial@40a60000 {
327 compatible = "fsl,imx7ulp-lpuart";
328 reg = <0x40a60000 0x1000>;
329 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
332 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
333 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
334 assigned-clock-rates = <48000000>;
338 lpuart7: serial@40a70000 {
339 compatible = "fsl,imx7ulp-lpuart";
340 reg = <0x40a70000 0x1000>;
341 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
344 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
345 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
346 assigned-clock-rates = <48000000>;
350 memory-controller@40ab0000 {
351 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
352 reg = <0x40ab0000 0x1000>;
353 clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
356 iomuxc1: pinctrl@40ac0000 {
357 compatible = "fsl,imx7ulp-iomuxc1";
358 reg = <0x40ac0000 0x1000>;
361 gpio_ptc: gpio@40ae0000 {
362 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
363 reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
366 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
370 <&pcc3 IMX7ULP_CLK_PCTLC>;
371 clock-names = "gpio", "port";
372 gpio-ranges = <&iomuxc1 0 0 32>;
375 gpio_ptd: gpio@40af0000 {
376 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
377 reg = <0x40af0000 0x1000 0x400f0040 0x40>;
380 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
384 <&pcc3 IMX7ULP_CLK_PCTLD>;
385 clock-names = "gpio", "port";
386 gpio-ranges = <&iomuxc1 0 32 32>;
389 gpio_pte: gpio@40b00000 {
390 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
391 reg = <0x40b00000 0x1000 0x400f0080 0x40>;
394 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
398 <&pcc3 IMX7ULP_CLK_PCTLE>;
399 clock-names = "gpio", "port";
400 gpio-ranges = <&iomuxc1 0 64 32>;
403 gpio_ptf: gpio@40b10000 {
404 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
405 reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
408 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
412 <&pcc3 IMX7ULP_CLK_PCTLF>;
413 clock-names = "gpio", "port";
414 gpio-ranges = <&iomuxc1 0 96 32>;
418 m4aips1: bus@41080000 {
419 compatible = "simple-bus";
420 #address-cells = <1>;
422 reg = <0x41080000 0x80000>;
426 compatible = "fsl,imx7ulp-sim", "syscon";
427 reg = <0x410a3000 0x1000>;
430 ocotp: ocotp-ctrl@410a6000 {
431 compatible = "fsl,imx7ulp-ocotp", "syscon";
432 reg = <0x410a6000 0x4000>;
433 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;