2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 * The decompressor and also some bootloaders rely on a
21 * pre-existing /chosen node to be available to insert the
22 * command line and merge other ATAGS info.
23 * Also for U-Boot there must be a pre-existing /memory node.
26 memory { device_type = "memory"; reg = <0 0>; };
65 compatible = "fsl,imx-ckil", "fixed-clock";
67 clock-frequency = <32768>;
71 compatible = "fsl,imx-ckih1", "fixed-clock";
73 clock-frequency = <0>;
77 compatible = "fsl,imx-osc", "fixed-clock";
79 clock-frequency = <24000000>;
86 compatible = "simple-bus";
87 interrupt-parent = <&gpc>;
90 dma_apbh: dma-apbh@00110000 {
91 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
92 reg = <0x00110000 0x2000>;
93 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>,
95 <0 13 IRQ_TYPE_LEVEL_HIGH>,
96 <0 13 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
100 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
103 gpmi: gpmi-nand@00112000 {
104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-names = "bch";
111 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
112 <&clks IMX6QDL_CLK_GPMI_APB>,
113 <&clks IMX6QDL_CLK_GPMI_BCH>,
114 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
115 <&clks IMX6QDL_CLK_PER1_BCH>;
116 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
117 "gpmi_bch_apb", "per1_bch";
118 dmas = <&dma_apbh 0>;
124 #address-cells = <1>;
126 reg = <0x00120000 0x9000>;
127 interrupts = <0 115 0x04>;
129 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
130 <&clks IMX6QDL_CLK_HDMI_ISFR>;
131 clock-names = "iahb", "isfr";
137 hdmi_mux_0: endpoint {
138 remote-endpoint = <&ipu1_di0_hdmi>;
145 hdmi_mux_1: endpoint {
146 remote-endpoint = <&ipu1_di1_hdmi>;
151 gpu_3d: gpu@00130000 {
152 compatible = "vivante,gc";
153 reg = <0x00130000 0x4000>;
154 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
156 <&clks IMX6QDL_CLK_GPU3D_CORE>,
157 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
158 clock-names = "bus", "core", "shader";
159 power-domains = <&pd_pu>;
162 gpu_2d: gpu@00134000 {
163 compatible = "vivante,gc";
164 reg = <0x00134000 0x4000>;
165 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
167 <&clks IMX6QDL_CLK_GPU2D_CORE>;
168 clock-names = "bus", "core";
169 power-domains = <&pd_pu>;
173 compatible = "arm,cortex-a9-twd-timer";
174 reg = <0x00a00600 0x20>;
175 interrupts = <1 13 0xf01>;
176 interrupt-parent = <&intc>;
177 clocks = <&clks IMX6QDL_CLK_TWD>;
180 intc: interrupt-controller@00a01000 {
181 compatible = "arm,cortex-a9-gic";
182 #interrupt-cells = <3>;
183 interrupt-controller;
184 reg = <0x00a01000 0x1000>,
186 interrupt-parent = <&intc>;
189 L2: l2-cache@00a02000 {
190 compatible = "arm,pl310-cache";
191 reg = <0x00a02000 0x1000>;
192 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
195 arm,tag-latency = <4 2 3>;
196 arm,data-latency = <4 2 3>;
201 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
202 reg = <0x01ffc000 0x04000>,
203 <0x01f00000 0x80000>;
204 reg-names = "dbi", "config";
205 #address-cells = <3>;
208 bus-range = <0x00 0xff>;
209 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
210 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
212 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-names = "msi";
214 #interrupt-cells = <1>;
215 interrupt-map-mask = <0 0 0 0x7>;
216 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
218 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
219 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
221 <&clks IMX6QDL_CLK_LVDS1_GATE>,
222 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
223 clock-names = "pcie", "pcie_bus", "pcie_phy";
228 compatible = "arm,cortex-a9-pmu";
229 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
232 aips-bus@02000000 { /* AIPS1 */
233 compatible = "fsl,aips-bus", "simple-bus";
234 #address-cells = <1>;
236 reg = <0x02000000 0x100000>;
240 compatible = "fsl,spba-bus", "simple-bus";
241 #address-cells = <1>;
243 reg = <0x02000000 0x40000>;
246 spdif: spdif@02004000 {
247 compatible = "fsl,imx35-spdif";
248 reg = <0x02004000 0x4000>;
249 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
250 dmas = <&sdma 14 18 0>,
252 dma-names = "rx", "tx";
253 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
254 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
255 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
256 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
257 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
258 clock-names = "core", "rxtx0",
266 ecspi1: ecspi@02008000 {
267 #address-cells = <1>;
269 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
270 reg = <0x02008000 0x4000>;
271 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
273 <&clks IMX6QDL_CLK_ECSPI1>;
274 clock-names = "ipg", "per";
275 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
276 dma-names = "rx", "tx";
280 ecspi2: ecspi@0200c000 {
281 #address-cells = <1>;
283 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
284 reg = <0x0200c000 0x4000>;
285 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
287 <&clks IMX6QDL_CLK_ECSPI2>;
288 clock-names = "ipg", "per";
289 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
290 dma-names = "rx", "tx";
294 ecspi3: ecspi@02010000 {
295 #address-cells = <1>;
297 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
298 reg = <0x02010000 0x4000>;
299 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
301 <&clks IMX6QDL_CLK_ECSPI3>;
302 clock-names = "ipg", "per";
303 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
304 dma-names = "rx", "tx";
308 ecspi4: ecspi@02014000 {
309 #address-cells = <1>;
311 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
312 reg = <0x02014000 0x4000>;
313 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
315 <&clks IMX6QDL_CLK_ECSPI4>;
316 clock-names = "ipg", "per";
317 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
318 dma-names = "rx", "tx";
322 uart1: serial@02020000 {
323 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
324 reg = <0x02020000 0x4000>;
325 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
327 <&clks IMX6QDL_CLK_UART_SERIAL>;
328 clock-names = "ipg", "per";
329 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
330 dma-names = "rx", "tx";
334 esai: esai@02024000 {
335 #sound-dai-cells = <0>;
336 compatible = "fsl,imx35-esai";
337 reg = <0x02024000 0x4000>;
338 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
340 <&clks IMX6QDL_CLK_ESAI_MEM>,
341 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
342 <&clks IMX6QDL_CLK_ESAI_IPG>,
343 <&clks IMX6QDL_CLK_SPBA>;
344 clock-names = "core", "mem", "extal", "fsys", "spba";
345 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
346 dma-names = "rx", "tx";
351 #sound-dai-cells = <0>;
352 compatible = "fsl,imx6q-ssi",
354 reg = <0x02028000 0x4000>;
355 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
357 <&clks IMX6QDL_CLK_SSI1>;
358 clock-names = "ipg", "baud";
359 dmas = <&sdma 37 1 0>,
361 dma-names = "rx", "tx";
362 fsl,fifo-depth = <15>;
367 #sound-dai-cells = <0>;
368 compatible = "fsl,imx6q-ssi",
370 reg = <0x0202c000 0x4000>;
371 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
373 <&clks IMX6QDL_CLK_SSI2>;
374 clock-names = "ipg", "baud";
375 dmas = <&sdma 41 1 0>,
377 dma-names = "rx", "tx";
378 fsl,fifo-depth = <15>;
383 #sound-dai-cells = <0>;
384 compatible = "fsl,imx6q-ssi",
386 reg = <0x02030000 0x4000>;
387 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
389 <&clks IMX6QDL_CLK_SSI3>;
390 clock-names = "ipg", "baud";
391 dmas = <&sdma 45 1 0>,
393 dma-names = "rx", "tx";
394 fsl,fifo-depth = <15>;
398 asrc: asrc@02034000 {
399 compatible = "fsl,imx53-asrc";
400 reg = <0x02034000 0x4000>;
401 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
403 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
404 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
408 <&clks IMX6QDL_CLK_SPBA>;
409 clock-names = "mem", "ipg", "asrck_0",
410 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
411 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
412 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
413 "asrck_d", "asrck_e", "asrck_f", "spba";
414 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
415 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
416 dma-names = "rxa", "rxb", "rxc",
418 fsl,asrc-rate = <48000>;
419 fsl,asrc-width = <16>;
424 reg = <0x0203c000 0x4000>;
429 compatible = "cnm,coda960";
430 reg = <0x02040000 0x3c000>;
431 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
432 <0 3 IRQ_TYPE_LEVEL_HIGH>;
433 interrupt-names = "bit", "jpeg";
434 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
435 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
436 clock-names = "per", "ahb";
437 power-domains = <&pd_pu>;
442 aipstz@0207c000 { /* AIPSTZ1 */
443 reg = <0x0207c000 0x4000>;
448 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
449 reg = <0x02080000 0x4000>;
450 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clks IMX6QDL_CLK_IPG>,
452 <&clks IMX6QDL_CLK_PWM1>;
453 clock-names = "ipg", "per";
459 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
460 reg = <0x02084000 0x4000>;
461 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX6QDL_CLK_IPG>,
463 <&clks IMX6QDL_CLK_PWM2>;
464 clock-names = "ipg", "per";
470 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
471 reg = <0x02088000 0x4000>;
472 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&clks IMX6QDL_CLK_IPG>,
474 <&clks IMX6QDL_CLK_PWM3>;
475 clock-names = "ipg", "per";
481 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
482 reg = <0x0208c000 0x4000>;
483 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clks IMX6QDL_CLK_IPG>,
485 <&clks IMX6QDL_CLK_PWM4>;
486 clock-names = "ipg", "per";
490 can1: flexcan@02090000 {
491 compatible = "fsl,imx6q-flexcan";
492 reg = <0x02090000 0x4000>;
493 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
495 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
496 clock-names = "ipg", "per";
500 can2: flexcan@02094000 {
501 compatible = "fsl,imx6q-flexcan";
502 reg = <0x02094000 0x4000>;
503 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
505 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
506 clock-names = "ipg", "per";
511 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
512 reg = <0x02098000 0x4000>;
513 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
515 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
516 <&clks IMX6QDL_CLK_GPT_3M>;
517 clock-names = "ipg", "per", "osc_per";
520 gpio1: gpio@0209c000 {
521 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
522 reg = <0x0209c000 0x4000>;
523 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
524 <0 67 IRQ_TYPE_LEVEL_HIGH>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
531 gpio2: gpio@020a0000 {
532 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
533 reg = <0x020a0000 0x4000>;
534 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
535 <0 69 IRQ_TYPE_LEVEL_HIGH>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
542 gpio3: gpio@020a4000 {
543 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
544 reg = <0x020a4000 0x4000>;
545 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
546 <0 71 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
553 gpio4: gpio@020a8000 {
554 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
555 reg = <0x020a8000 0x4000>;
556 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
557 <0 73 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
564 gpio5: gpio@020ac000 {
565 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
566 reg = <0x020ac000 0x4000>;
567 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
568 <0 75 IRQ_TYPE_LEVEL_HIGH>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
575 gpio6: gpio@020b0000 {
576 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
577 reg = <0x020b0000 0x4000>;
578 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
579 <0 77 IRQ_TYPE_LEVEL_HIGH>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
586 gpio7: gpio@020b4000 {
587 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
588 reg = <0x020b4000 0x4000>;
589 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
590 <0 79 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
598 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
599 reg = <0x020b8000 0x4000>;
600 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&clks IMX6QDL_CLK_IPG>;
605 wdog1: wdog@020bc000 {
606 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
607 reg = <0x020bc000 0x4000>;
608 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&clks IMX6QDL_CLK_DUMMY>;
612 wdog2: wdog@020c0000 {
613 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
614 reg = <0x020c0000 0x4000>;
615 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&clks IMX6QDL_CLK_DUMMY>;
621 compatible = "fsl,imx6q-ccm";
622 reg = <0x020c4000 0x4000>;
623 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
624 <0 88 IRQ_TYPE_LEVEL_HIGH>;
628 anatop: anatop@020c8000 {
629 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
630 reg = <0x020c8000 0x1000>;
631 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
632 <0 54 IRQ_TYPE_LEVEL_HIGH>,
633 <0 127 IRQ_TYPE_LEVEL_HIGH>;
636 compatible = "fsl,anatop-regulator";
637 regulator-name = "vdd1p1";
638 regulator-min-microvolt = <1000000>;
639 regulator-max-microvolt = <1200000>;
641 anatop-reg-offset = <0x110>;
642 anatop-vol-bit-shift = <8>;
643 anatop-vol-bit-width = <5>;
644 anatop-min-bit-val = <4>;
645 anatop-min-voltage = <800000>;
646 anatop-max-voltage = <1375000>;
647 anatop-enable-bit = <0>;
651 compatible = "fsl,anatop-regulator";
652 regulator-name = "vdd3p0";
653 regulator-min-microvolt = <2800000>;
654 regulator-max-microvolt = <3150000>;
656 anatop-reg-offset = <0x120>;
657 anatop-vol-bit-shift = <8>;
658 anatop-vol-bit-width = <5>;
659 anatop-min-bit-val = <0>;
660 anatop-min-voltage = <2625000>;
661 anatop-max-voltage = <3400000>;
662 anatop-enable-bit = <0>;
666 compatible = "fsl,anatop-regulator";
667 regulator-name = "vdd2p5";
668 regulator-min-microvolt = <2250000>;
669 regulator-max-microvolt = <2750000>;
671 anatop-reg-offset = <0x130>;
672 anatop-vol-bit-shift = <8>;
673 anatop-vol-bit-width = <5>;
674 anatop-min-bit-val = <0>;
675 anatop-min-voltage = <2100000>;
676 anatop-max-voltage = <2875000>;
677 anatop-enable-bit = <0>;
680 reg_arm: regulator-vddcore {
681 compatible = "fsl,anatop-regulator";
682 regulator-name = "vddarm";
683 regulator-min-microvolt = <725000>;
684 regulator-max-microvolt = <1450000>;
686 anatop-reg-offset = <0x140>;
687 anatop-vol-bit-shift = <0>;
688 anatop-vol-bit-width = <5>;
689 anatop-delay-reg-offset = <0x170>;
690 anatop-delay-bit-shift = <24>;
691 anatop-delay-bit-width = <2>;
692 anatop-min-bit-val = <1>;
693 anatop-min-voltage = <725000>;
694 anatop-max-voltage = <1450000>;
697 reg_pu: regulator-vddpu {
698 compatible = "fsl,anatop-regulator";
699 regulator-name = "vddpu";
700 regulator-min-microvolt = <725000>;
701 regulator-max-microvolt = <1450000>;
702 regulator-enable-ramp-delay = <150>;
703 anatop-reg-offset = <0x140>;
704 anatop-vol-bit-shift = <9>;
705 anatop-vol-bit-width = <5>;
706 anatop-delay-reg-offset = <0x170>;
707 anatop-delay-bit-shift = <26>;
708 anatop-delay-bit-width = <2>;
709 anatop-min-bit-val = <1>;
710 anatop-min-voltage = <725000>;
711 anatop-max-voltage = <1450000>;
714 reg_soc: regulator-vddsoc {
715 compatible = "fsl,anatop-regulator";
716 regulator-name = "vddsoc";
717 regulator-min-microvolt = <725000>;
718 regulator-max-microvolt = <1450000>;
720 anatop-reg-offset = <0x140>;
721 anatop-vol-bit-shift = <18>;
722 anatop-vol-bit-width = <5>;
723 anatop-delay-reg-offset = <0x170>;
724 anatop-delay-bit-shift = <28>;
725 anatop-delay-bit-width = <2>;
726 anatop-min-bit-val = <1>;
727 anatop-min-voltage = <725000>;
728 anatop-max-voltage = <1450000>;
733 compatible = "fsl,imx6q-tempmon";
734 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
735 fsl,tempmon = <&anatop>;
736 fsl,tempmon-data = <&ocotp>;
737 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
740 usbphy1: usbphy@020c9000 {
741 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
742 reg = <0x020c9000 0x1000>;
743 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
745 fsl,anatop = <&anatop>;
748 usbphy2: usbphy@020ca000 {
749 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
750 reg = <0x020ca000 0x1000>;
751 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
753 fsl,anatop = <&anatop>;
756 snvs: snvs@020cc000 {
757 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
758 reg = <0x020cc000 0x4000>;
760 snvs_rtc: snvs-rtc-lp {
761 compatible = "fsl,sec-v4.0-mon-rtc-lp";
764 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
765 <0 20 IRQ_TYPE_LEVEL_HIGH>;
768 snvs_poweroff: snvs-poweroff {
769 compatible = "syscon-poweroff";
777 epit1: epit@020d0000 { /* EPIT1 */
778 reg = <0x020d0000 0x4000>;
779 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
782 epit2: epit@020d4000 { /* EPIT2 */
783 reg = <0x020d4000 0x4000>;
784 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
788 compatible = "fsl,imx6q-src", "fsl,imx51-src";
789 reg = <0x020d8000 0x4000>;
790 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
791 <0 96 IRQ_TYPE_LEVEL_HIGH>;
796 compatible = "fsl,imx6q-gpc";
797 reg = <0x020dc000 0x4000>;
798 interrupt-controller;
799 #interrupt-cells = <3>;
800 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
801 <0 90 IRQ_TYPE_LEVEL_HIGH>;
802 interrupt-parent = <&intc>;
803 clocks = <&clks IMX6QDL_CLK_IPG>;
807 #address-cells = <1>;
812 #power-domain-cells = <0>;
814 pd_pu: power-domain@1 {
816 #power-domain-cells = <0>;
817 power-supply = <®_pu>;
818 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
819 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
820 <&clks IMX6QDL_CLK_GPU2D_CORE>,
821 <&clks IMX6QDL_CLK_GPU2D_AXI>,
822 <&clks IMX6QDL_CLK_OPENVG_AXI>,
823 <&clks IMX6QDL_CLK_VPU_AXI>;
828 gpr: iomuxc-gpr@020e0000 {
829 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
830 reg = <0x020e0000 0x38>;
832 mux: mux-controller {
833 compatible = "mmio-mux";
834 #mux-control-cells = <1>;
838 iomuxc: iomuxc@020e0000 {
839 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
840 reg = <0x020e0000 0x4000>;
844 #address-cells = <1>;
846 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
851 #address-cells = <1>;
859 lvds0_mux_0: endpoint {
860 remote-endpoint = <&ipu1_di0_lvds0>;
867 lvds0_mux_1: endpoint {
868 remote-endpoint = <&ipu1_di1_lvds0>;
874 #address-cells = <1>;
882 lvds1_mux_0: endpoint {
883 remote-endpoint = <&ipu1_di0_lvds1>;
890 lvds1_mux_1: endpoint {
891 remote-endpoint = <&ipu1_di1_lvds1>;
897 dcic1: dcic@020e4000 {
898 reg = <0x020e4000 0x4000>;
899 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
902 dcic2: dcic@020e8000 {
903 reg = <0x020e8000 0x4000>;
904 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
907 sdma: sdma@020ec000 {
908 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
909 reg = <0x020ec000 0x4000>;
910 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6QDL_CLK_SDMA>,
912 <&clks IMX6QDL_CLK_SDMA>;
913 clock-names = "ipg", "ahb";
915 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
919 aips-bus@02100000 { /* AIPS2 */
920 compatible = "fsl,aips-bus", "simple-bus";
921 #address-cells = <1>;
923 reg = <0x02100000 0x100000>;
926 crypto: caam@2100000 {
927 compatible = "fsl,sec-v4.0";
929 #address-cells = <1>;
931 reg = <0x2100000 0x10000>;
932 ranges = <0 0x2100000 0x10000>;
933 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
934 <&clks IMX6QDL_CLK_CAAM_ACLK>,
935 <&clks IMX6QDL_CLK_CAAM_IPG>,
936 <&clks IMX6QDL_CLK_EIM_SLOW>;
937 clock-names = "mem", "aclk", "ipg", "emi_slow";
940 compatible = "fsl,sec-v4.0-job-ring";
941 reg = <0x1000 0x1000>;
942 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
946 compatible = "fsl,sec-v4.0-job-ring";
947 reg = <0x2000 0x1000>;
948 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
952 aipstz@0217c000 { /* AIPSTZ2 */
953 reg = <0x0217c000 0x4000>;
956 usbotg: usb@02184000 {
957 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
958 reg = <0x02184000 0x200>;
959 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&clks IMX6QDL_CLK_USBOH3>;
961 fsl,usbphy = <&usbphy1>;
962 fsl,usbmisc = <&usbmisc 0>;
963 ahb-burst-config = <0x0>;
964 tx-burst-size-dword = <0x10>;
965 rx-burst-size-dword = <0x10>;
969 usbh1: usb@02184200 {
970 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
971 reg = <0x02184200 0x200>;
972 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clks IMX6QDL_CLK_USBOH3>;
974 fsl,usbphy = <&usbphy2>;
975 fsl,usbmisc = <&usbmisc 1>;
977 ahb-burst-config = <0x0>;
978 tx-burst-size-dword = <0x10>;
979 rx-burst-size-dword = <0x10>;
983 usbh2: usb@02184400 {
984 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
985 reg = <0x02184400 0x200>;
986 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&clks IMX6QDL_CLK_USBOH3>;
988 fsl,usbmisc = <&usbmisc 2>;
990 ahb-burst-config = <0x0>;
991 tx-burst-size-dword = <0x10>;
992 rx-burst-size-dword = <0x10>;
996 usbh3: usb@02184600 {
997 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
998 reg = <0x02184600 0x200>;
999 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1001 fsl,usbmisc = <&usbmisc 3>;
1003 ahb-burst-config = <0x0>;
1004 tx-burst-size-dword = <0x10>;
1005 rx-burst-size-dword = <0x10>;
1006 status = "disabled";
1009 usbmisc: usbmisc@02184800 {
1011 compatible = "fsl,imx6q-usbmisc";
1012 reg = <0x02184800 0x200>;
1013 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1016 fec: ethernet@02188000 {
1017 compatible = "fsl,imx6q-fec";
1018 reg = <0x02188000 0x4000>;
1019 interrupts-extended =
1020 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1021 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&clks IMX6QDL_CLK_ENET>,
1023 <&clks IMX6QDL_CLK_ENET>,
1024 <&clks IMX6QDL_CLK_ENET_REF>;
1025 clock-names = "ipg", "ahb", "ptp";
1026 status = "disabled";
1030 reg = <0x0218c000 0x4000>;
1031 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1032 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1033 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1036 usdhc1: usdhc@02190000 {
1037 compatible = "fsl,imx6q-usdhc";
1038 reg = <0x02190000 0x4000>;
1039 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1041 <&clks IMX6QDL_CLK_USDHC1>,
1042 <&clks IMX6QDL_CLK_USDHC1>;
1043 clock-names = "ipg", "ahb", "per";
1045 status = "disabled";
1048 usdhc2: usdhc@02194000 {
1049 compatible = "fsl,imx6q-usdhc";
1050 reg = <0x02194000 0x4000>;
1051 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1053 <&clks IMX6QDL_CLK_USDHC2>,
1054 <&clks IMX6QDL_CLK_USDHC2>;
1055 clock-names = "ipg", "ahb", "per";
1057 status = "disabled";
1060 usdhc3: usdhc@02198000 {
1061 compatible = "fsl,imx6q-usdhc";
1062 reg = <0x02198000 0x4000>;
1063 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1065 <&clks IMX6QDL_CLK_USDHC3>,
1066 <&clks IMX6QDL_CLK_USDHC3>;
1067 clock-names = "ipg", "ahb", "per";
1069 status = "disabled";
1072 usdhc4: usdhc@0219c000 {
1073 compatible = "fsl,imx6q-usdhc";
1074 reg = <0x0219c000 0x4000>;
1075 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1077 <&clks IMX6QDL_CLK_USDHC4>,
1078 <&clks IMX6QDL_CLK_USDHC4>;
1079 clock-names = "ipg", "ahb", "per";
1081 status = "disabled";
1084 i2c1: i2c@021a0000 {
1085 #address-cells = <1>;
1087 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1088 reg = <0x021a0000 0x4000>;
1089 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&clks IMX6QDL_CLK_I2C1>;
1091 status = "disabled";
1094 i2c2: i2c@021a4000 {
1095 #address-cells = <1>;
1097 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1098 reg = <0x021a4000 0x4000>;
1099 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6QDL_CLK_I2C2>;
1101 status = "disabled";
1104 i2c3: i2c@021a8000 {
1105 #address-cells = <1>;
1107 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1108 reg = <0x021a8000 0x4000>;
1109 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&clks IMX6QDL_CLK_I2C3>;
1111 status = "disabled";
1115 reg = <0x021ac000 0x4000>;
1118 mmdc0: mmdc@021b0000 { /* MMDC0 */
1119 compatible = "fsl,imx6q-mmdc";
1120 reg = <0x021b0000 0x4000>;
1123 mmdc1: mmdc@021b4000 { /* MMDC1 */
1124 reg = <0x021b4000 0x4000>;
1127 weim: weim@021b8000 {
1128 #address-cells = <2>;
1130 compatible = "fsl,imx6q-weim";
1131 reg = <0x021b8000 0x4000>;
1132 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1133 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1134 fsl,weim-cs-gpr = <&gpr>;
1135 status = "disabled";
1138 ocotp: ocotp@021bc000 {
1139 compatible = "fsl,imx6q-ocotp", "syscon";
1140 reg = <0x021bc000 0x4000>;
1141 clocks = <&clks IMX6QDL_CLK_IIM>;
1144 tzasc@021d0000 { /* TZASC1 */
1145 reg = <0x021d0000 0x4000>;
1146 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1149 tzasc@021d4000 { /* TZASC2 */
1150 reg = <0x021d4000 0x4000>;
1151 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1154 audmux: audmux@021d8000 {
1155 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1156 reg = <0x021d8000 0x4000>;
1157 status = "disabled";
1160 mipi_csi: mipi@021dc000 {
1161 compatible = "fsl,imx6-mipi-csi2";
1162 reg = <0x021dc000 0x4000>;
1163 #address-cells = <1>;
1165 interrupts = <0 100 0x04>, <0 101 0x04>;
1166 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1167 <&clks IMX6QDL_CLK_VIDEO_27M>,
1168 <&clks IMX6QDL_CLK_EIM_PODF>;
1169 clock-names = "dphy", "ref", "pix";
1170 status = "disabled";
1173 mipi_dsi: mipi@021e0000 {
1174 #address-cells = <1>;
1176 reg = <0x021e0000 0x4000>;
1177 status = "disabled";
1180 #address-cells = <1>;
1186 mipi_mux_0: endpoint {
1187 remote-endpoint = <&ipu1_di0_mipi>;
1194 mipi_mux_1: endpoint {
1195 remote-endpoint = <&ipu1_di1_mipi>;
1202 compatible = "fsl,imx6q-vdoa";
1203 reg = <0x021e4000 0x4000>;
1204 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&clks IMX6QDL_CLK_VDOA>;
1208 uart2: serial@021e8000 {
1209 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1210 reg = <0x021e8000 0x4000>;
1211 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1212 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1213 <&clks IMX6QDL_CLK_UART_SERIAL>;
1214 clock-names = "ipg", "per";
1215 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1216 dma-names = "rx", "tx";
1217 status = "disabled";
1220 uart3: serial@021ec000 {
1221 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1222 reg = <0x021ec000 0x4000>;
1223 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1225 <&clks IMX6QDL_CLK_UART_SERIAL>;
1226 clock-names = "ipg", "per";
1227 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1228 dma-names = "rx", "tx";
1229 status = "disabled";
1232 uart4: serial@021f0000 {
1233 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1234 reg = <0x021f0000 0x4000>;
1235 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1237 <&clks IMX6QDL_CLK_UART_SERIAL>;
1238 clock-names = "ipg", "per";
1239 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1240 dma-names = "rx", "tx";
1241 status = "disabled";
1244 uart5: serial@021f4000 {
1245 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1246 reg = <0x021f4000 0x4000>;
1247 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1248 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1249 <&clks IMX6QDL_CLK_UART_SERIAL>;
1250 clock-names = "ipg", "per";
1251 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1252 dma-names = "rx", "tx";
1253 status = "disabled";
1257 ipu1: ipu@02400000 {
1258 #address-cells = <1>;
1260 compatible = "fsl,imx6q-ipu";
1261 reg = <0x02400000 0x400000>;
1262 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1263 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&clks IMX6QDL_CLK_IPU1>,
1265 <&clks IMX6QDL_CLK_IPU1_DI0>,
1266 <&clks IMX6QDL_CLK_IPU1_DI1>;
1267 clock-names = "bus", "di0", "di1";
1273 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1274 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1283 #address-cells = <1>;
1287 ipu1_di0_disp0: disp0-endpoint {
1290 ipu1_di0_hdmi: hdmi-endpoint {
1291 remote-endpoint = <&hdmi_mux_0>;
1294 ipu1_di0_mipi: mipi-endpoint {
1295 remote-endpoint = <&mipi_mux_0>;
1298 ipu1_di0_lvds0: lvds0-endpoint {
1299 remote-endpoint = <&lvds0_mux_0>;
1302 ipu1_di0_lvds1: lvds1-endpoint {
1303 remote-endpoint = <&lvds1_mux_0>;
1308 #address-cells = <1>;
1312 ipu1_di1_disp1: disp1-endpoint {
1315 ipu1_di1_hdmi: hdmi-endpoint {
1316 remote-endpoint = <&hdmi_mux_1>;
1319 ipu1_di1_mipi: mipi-endpoint {
1320 remote-endpoint = <&mipi_mux_1>;
1323 ipu1_di1_lvds0: lvds0-endpoint {
1324 remote-endpoint = <&lvds0_mux_1>;
1327 ipu1_di1_lvds1: lvds1-endpoint {
1328 remote-endpoint = <&lvds1_mux_1>;