arch/arm/boot/dts/imx6qdl-gw52xx.dtsi

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 led0 = &led0;
  18                 led1 = &led1;
  19                 led2 = &led2;
  20                 nand = &gpmi;
  21                 ssi0 = &ssi1;
  22                 usb0 = &usbh1;
  23                 usb1 = &usbotg;
  24         };
  25
  26         chosen {
  27                 bootargs = "console=ttymxc1,115200";
  28         };
  29
  30         backlight {
  31                 compatible = "pwm-backlight";
  32                 pwms = <&pwm4 0 5000000>;
  33                 brightness-levels = <0 4 8 16 32 64 128 255>;
  34                 default-brightness-level = <7>;
  35         };
  36
  37         leds {
  38                 compatible = "gpio-leds";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_gpio_leds>;
  41
  42                 led0: user1 {
  43                         label = "user1";
  44                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  45                         default-state = "on";
  46                         linux,default-trigger = "heartbeat";
  47                 };
  48
  49                 led1: user2 {
  50                         label = "user2";
  51                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  52                         default-state = "off";
  53                 };
  54
  55                 led2: user3 {
  56                         label = "user3";
  57                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  58                         default-state = "off";
  59                 };
  60         };
  61
  62         memory {
  63                 reg = <0x10000000 0x20000000>;
  64         };
  65
  66         pps {
  67                 compatible = "pps-gpio";
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_pps>;
  70                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  71                 status = "okay";
  72         };
  73
  74         reg_1p0v: regulator-1p0v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "1P0V";
  77                 regulator-min-microvolt = <1000000>;
  78                 regulator-max-microvolt = <1000000>;
  79                 regulator-always-on;
  80         };
  81
  82         reg_3p3v: regulator-3p3v {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "3P3V";
  85                 regulator-min-microvolt = <3300000>;
  86                 regulator-max-microvolt = <3300000>;
  87                 regulator-always-on;
  88         };
  89
  90         reg_5p0v: regulator-5p0v {
  91                 compatible = "regulator-fixed";
  92                 regulator-name = "5P0V";
  93                 regulator-min-microvolt = <5000000>;
  94                 regulator-max-microvolt = <5000000>;
  95                 regulator-always-on;
  96         };
  97
  98         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  99                 compatible = "regulator-fixed";
 100                 regulator-name = "usb_otg_vbus";
 101                 regulator-min-microvolt = <5000000>;
 102                 regulator-max-microvolt = <5000000>;
 103                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 104                 enable-active-high;
 105         };
 106
 107         sound {
 108                 compatible = "fsl,imx6q-ventana-sgtl5000",
 109                              "fsl,imx-audio-sgtl5000";
 110                 model = "sgtl5000-audio";
 111                 ssi-controller = <&ssi1>;
 112                 audio-codec = <&codec>;
 113                 audio-routing =
 114                         "MIC_IN", "Mic Jack",
 115                         "Mic Jack", "Mic Bias",
 116                         "Headphone Jack", "HP_OUT";
 117                 mux-int-port = <1>;
 118                 mux-ext-port = <4>;
 119         };
 120 };
 121
 122 &audmux {
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&pinctrl_audmux>;
 125         status = "okay";
 126 };
 127
 128 &can1 {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_flexcan1>;
 131         status = "okay";
 132 };
 133
 134 &clks {
 135         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 136                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 137         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 138                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 139 };
 140
 141 &ecspi3 {
 142         fsl,spi-num-chipselects = <1>;
 143         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_ecspi3>;
 146         status = "okay";
 147 };
 148
 149 &fec {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_enet>;
 152         phy-mode = "rgmii-id";
 153         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 154         status = "okay";
 155 };
 156
 157 &gpmi {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_gpmi_nand>;
 160         status = "okay";
 161 };
 162
 163 &hdmi {
 164         ddc-i2c-bus = <&i2c3>;
 165         status = "okay";
 166 };
 167
 168 &i2c1 {
 169         clock-frequency = <100000>;
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&pinctrl_i2c1>;
 172         status = "okay";
 173
 174         eeprom1: eeprom@50 {
 175                 compatible = "atmel,24c02";
 176                 reg = <0x50>;
 177                 pagesize = <16>;
 178         };
 179
 180         eeprom2: eeprom@51 {
 181                 compatible = "atmel,24c02";
 182                 reg = <0x51>;
 183                 pagesize = <16>;
 184         };
 185
 186         eeprom3: eeprom@52 {
 187                 compatible = "atmel,24c02";
 188                 reg = <0x52>;
 189                 pagesize = <16>;
 190         };
 191
 192         eeprom4: eeprom@53 {
 193                 compatible = "atmel,24c02";
 194                 reg = <0x53>;
 195                 pagesize = <16>;
 196         };
 197
 198         gpio: pca9555@23 {
 199                 compatible = "nxp,pca9555";
 200                 reg = <0x23>;
 201                 gpio-controller;
 202                 #gpio-cells = <2>;
 203         };
 204
 205         rtc: ds1672@68 {
 206                 compatible = "dallas,ds1672";
 207                 reg = <0x68>;
 208         };
 209 };
 210
 211 &i2c2 {
 212         clock-frequency = <100000>;
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_i2c2>;
 215         status = "okay";
 216
 217         ltc3676: pmic@3c {
 218                 compatible = "lltc,ltc3676";
 219                 reg = <0x3c>;
 220                 pinctrl-names = "default";
 221                 pinctrl-0 = <&pinctrl_pmic>;
 222                 interrupt-parent = <&gpio1>;
 223                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 224
 225                 regulators {
 226                         /* VDD_SOC (1+R1/R2 = 1.635) */
 227                         reg_vdd_soc: sw1 {
 228                                 regulator-name = "vddsoc";
 229                                 regulator-min-microvolt = <674400>;
 230                                 regulator-max-microvolt = <1308000>;
 231                                 lltc,fb-voltage-divider = <127000 200000>;
 232                                 regulator-ramp-delay = <7000>;
 233                                 regulator-boot-on;
 234                                 regulator-always-on;
 235                         };
 236
 237                         /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
 238                         reg_1p8v: sw2 {
 239                                 regulator-name = "vdd1p8";
 240                                 regulator-min-microvolt = <1033310>;
 241                                 regulator-max-microvolt = <2004000>;
 242                                 lltc,fb-voltage-divider = <301000 200000>;
 243                                 regulator-ramp-delay = <7000>;
 244                                 regulator-boot-on;
 245                                 regulator-always-on;
 246                         };
 247
 248                         /* VDD_ARM (1+R1/R2 = 1.635) */
 249                         reg_vdd_arm: sw3 {
 250                                 regulator-name = "vddarm";
 251                                 regulator-min-microvolt = <674400>;
 252                                 regulator-max-microvolt = <1308000>;
 253                                 lltc,fb-voltage-divider = <127000 200000>;
 254                                 regulator-ramp-delay = <7000>;
 255                                 regulator-boot-on;
 256                                 regulator-always-on;
 257                         };
 258
 259                         /* VDD_DDR (1+R1/R2 = 2.105) */
 260                         reg_vdd_ddr: sw4 {
 261                                 regulator-name = "vddddr";
 262                                 regulator-min-microvolt = <868310>;
 263                                 regulator-max-microvolt = <1684000>;
 264                                 lltc,fb-voltage-divider = <221000 200000>;
 265                                 regulator-ramp-delay = <7000>;
 266                                 regulator-boot-on;
 267                                 regulator-always-on;
 268                         };
 269
 270                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 271                         reg_2p5v: ldo2 {
 272                                 regulator-name = "vdd2p5";
 273                                 regulator-min-microvolt = <2490375>;
 274                                 regulator-max-microvolt = <2490375>;
 275                                 lltc,fb-voltage-divider = <487000 200000>;
 276                                 regulator-boot-on;
 277                                 regulator-always-on;
 278                         };
 279
 280                         /* VDD_AUD_1P8: Audio codec */
 281                         reg_aud_1p8v: ldo3 {
 282                                 regulator-name = "vdd1p8";
 283                                 regulator-min-microvolt = <1800000>;
 284                                 regulator-max-microvolt = <1800000>;
 285                                 regulator-boot-on;
 286                         };
 287
 288                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 289                         reg_3p0v: ldo4 {
 290                                 regulator-name = "vdd3p0";
 291                                 regulator-min-microvolt = <3023250>;
 292                                 regulator-max-microvolt = <3023250>;
 293                                 lltc,fb-voltage-divider = <634000 200000>;
 294                                 regulator-boot-on;
 295                                 regulator-always-on;
 296                         };
 297                 };
 298         };
 299 };
 300
 301 &i2c3 {
 302         clock-frequency = <100000>;
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&pinctrl_i2c3>;
 305         status = "okay";
 306
 307         codec: sgtl5000@0a {
 308                 compatible = "fsl,sgtl5000";
 309                 reg = <0x0a>;
 310                 clocks = <&clks IMX6QDL_CLK_CKO>;
 311                 VDDA-supply = <&reg_1p8v>;
 312                 VDDIO-supply = <&reg_3p3v>;
 313         };
 314
 315         touchscreen: egalax_ts@04 {
 316                 compatible = "eeti,egalax_ts";
 317                 reg = <0x04>;
 318                 interrupt-parent = <&gpio7>;
 319                 interrupts = <12 2>;
 320                 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 321         };
 322 };
 323
 324 &ldb {
 325         status = "okay";
 326
 327         lvds-channel@0 {
 328                 fsl,data-mapping = "spwg";
 329                 fsl,data-width = <18>;
 330                 status = "okay";
 331
 332                 display-timings {
 333                         native-mode = <&timing0>;
 334                         timing0: hsd100pxn1 {
 335                                 clock-frequency = <65000000>;
 336                                 hactive = <1024>;
 337                                 vactive = <768>;
 338                                 hback-porch = <220>;
 339                                 hfront-porch = <40>;
 340                                 vback-porch = <21>;
 341                                 vfront-porch = <7>;
 342                                 hsync-len = <60>;
 343                                 vsync-len = <10>;
 344                         };
 345                 };
 346         };
 347 };
 348
 349 &pcie {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_pcie>;
 352         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 353         status = "okay";
 354 };
 355
 356 &pwm2 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 359         status = "disabled";
 360 };
 361
 362 &pwm3 {
 363         pinctrl-names = "default";
 364         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 365         status = "disabled";
 366 };
 367
 368 &pwm4 {
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_pwm4>;
 371         status = "okay";
 372 };
 373
 374 &ssi1 {
 375         status = "okay";
 376 };
 377
 378 &uart1 {
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_uart1>;
 381         uart-has-rtscts;
 382         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 383         status = "okay";
 384 };
 385
 386 &uart2 {
 387         pinctrl-names = "default";
 388         pinctrl-0 = <&pinctrl_uart2>;
 389         status = "okay";
 390 };
 391
 392 &uart5 {
 393         pinctrl-names = "default";
 394         pinctrl-0 = <&pinctrl_uart5>;
 395         status = "okay";
 396 };
 397
 398 &usbotg {
 399         vbus-supply = <&reg_usb_otg_vbus>;
 400         pinctrl-names = "default";
 401         pinctrl-0 = <&pinctrl_usbotg>;
 402         disable-over-current;
 403         status = "okay";
 404 };
 405
 406 &usbh1 {
 407         status = "okay";
 408 };
 409
 410 &usdhc3 {
 411         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 412         pinctrl-0 = <&pinctrl_usdhc3>;
 413         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 414         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 415         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 416         vmmc-supply = <&reg_3p3v>;
 417         no-1-8-v; /* firmware will remove if board revision supports */
 418         status = "okay";
 419 };
 420
 421 &wdog1 {
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&pinctrl_wdog>;
 424         fsl,ext-reset-output;
 425 };
 426
 427 &iomuxc {
 428         imx6qdl-gw52xx {
 429                 pinctrl_audmux: audmuxgrp {
 430                         fsl,pins = <
 431                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 432                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 433                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 434                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 435                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0 /* AUD4_MCK */
 436                         >;
 437                 };
 438
 439                 pinctrl_ecspi3: escpi3grp {
 440                         fsl,pins = <
 441                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 442                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 443                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 444                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 445                         >;
 446                 };
 447
 448                 pinctrl_enet: enetgrp {
 449                         fsl,pins = <
 450                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 451                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 452                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 453                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 454                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 455                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 456                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 457                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 458                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 459                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 460                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 461                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 462                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 463                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 464                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 465                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 466                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0 /* PHY Reset */
 467                         >;
 468                 };
 469
 470                 pinctrl_flexcan1: flexcan1grp {
 471                         fsl,pins = <
 472                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 473                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 474                                 MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
 475                         >;
 476                 };
 477
 478                 pinctrl_gpio_leds: gpioledsgrp {
 479                         fsl,pins = <
 480                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 481                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 482                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 483                         >;
 484                 };
 485
 486                 pinctrl_gpmi_nand: gpminandgrp {
 487                         fsl,pins = <
 488                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 489                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 490                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 491                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 492                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 493                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 494                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 495                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 496                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 497                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 498                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 499                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 500                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 501                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 502                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 503                         >;
 504                 };
 505
 506                 pinctrl_i2c1: i2c1grp {
 507                         fsl,pins = <
 508                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 509                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 510                         >;
 511                 };
 512
 513                 pinctrl_i2c2: i2c2grp {
 514                         fsl,pins = <
 515                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 516                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 517                         >;
 518                 };
 519
 520                 pinctrl_i2c3: i2c3grp {
 521                         fsl,pins = <
 522                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 523                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 524                         >;
 525                 };
 526
 527                 pinctrl_pcie: pciegrp {
 528                         fsl,pins = <
 529                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE_RST# */
 530                         >;
 531                 };
 532
 533                 pinctrl_pmic: pmicgrp {
 534                         fsl,pins = <
 535                                 MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 536                         >;
 537                 };
 538
 539                 pinctrl_pps: ppsgrp {
 540                         fsl,pins = <
 541                                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 542                         >;
 543                 };
 544
 545                 pinctrl_pwm2: pwm2grp {
 546                         fsl,pins = <
 547                                 MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 548                         >;
 549                 };
 550
 551                 pinctrl_pwm3: pwm3grp {
 552                         fsl,pins = <
 553                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 554                         >;
 555                 };
 556
 557                 pinctrl_pwm4: pwm4grp {
 558                         fsl,pins = <
 559                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 560                         >;
 561                 };
 562
 563                 pinctrl_uart1: uart1grp {
 564                         fsl,pins = <
 565                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 566                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 567                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 568                         >;
 569                 };
 570
 571                 pinctrl_uart2: uart2grp {
 572                         fsl,pins = <
 573                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 574                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 575                         >;
 576                 };
 577
 578                 pinctrl_uart5: uart5grp {
 579                         fsl,pins = <
 580                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 581                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 582                         >;
 583                 };
 584
 585                 pinctrl_usbotg: usbotggrp {
 586                         fsl,pins = <
 587                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 588                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0 /* OTG_PWR_EN */
 589                         >;
 590                 };
 591
 592                 pinctrl_usdhc3: usdhc3grp {
 593                         fsl,pins = <
 594                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 595                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 596                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 597                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 598                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 599                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 600                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 601                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 602                         >;
 603                 };
 604
 605                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 606                         fsl,pins = <
 607                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 608                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 609                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 610                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 611                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 612                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 613                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 614                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 615                         >;
 616                 };
 617
 618                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 619                         fsl,pins = <
 620                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 621                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 622                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 623                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 624                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 625                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 626                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 627                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 628                         >;
 629                 };
 630
 631                 pinctrl_wdog: wdoggrp {
 632                         fsl,pins = <
 633                                 MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 634                         >;
 635                 };
 636         };
 637 };