2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "imx53-pinfunc.h"
14 #include <dt-bindings/clock/imx5-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
23 * The decompressor and also some bootloaders rely on a
24 * pre-existing /chosen node to be available to insert the
25 * command line and merge other ATAGS info.
26 * Also for U-Boot there must be a pre-existing /memory node.
29 memory { device_type = "memory"; reg = <0 0>; };
62 compatible = "arm,cortex-a8";
64 clocks = <&clks IMX5_CLK_ARM>;
65 clock-latency = <61036>;
66 voltage-tolerance = <5>;
79 compatible = "fsl,imx-display-subsystem";
80 ports = <&ipu_di0>, <&ipu_di1>;
83 tzic: tz-interrupt-controller@0fffc000 {
84 compatible = "fsl,imx53-tzic", "fsl,tzic";
86 #interrupt-cells = <1>;
87 reg = <0x0fffc000 0x4000>;
95 compatible = "fsl,imx-ckil", "fixed-clock";
97 clock-frequency = <32768>;
101 compatible = "fsl,imx-ckih1", "fixed-clock";
103 clock-frequency = <22579200>;
107 compatible = "fsl,imx-ckih2", "fixed-clock";
109 clock-frequency = <0>;
113 compatible = "fsl,imx-osc", "fixed-clock";
115 clock-frequency = <24000000>;
120 #address-cells = <1>;
122 compatible = "simple-bus";
123 interrupt-parent = <&tzic>;
126 sata: sata@10000000 {
127 compatible = "fsl,imx53-ahci";
128 reg = <0x10000000 0x1000>;
130 clocks = <&clks IMX5_CLK_SATA_GATE>,
131 <&clks IMX5_CLK_SATA_REF>,
132 <&clks IMX5_CLK_AHB>;
133 clock-names = "sata", "sata_ref", "ahb";
138 #address-cells = <1>;
140 compatible = "fsl,imx53-ipu";
141 reg = <0x18000000 0x08000000>;
142 interrupts = <11 10>;
143 clocks = <&clks IMX5_CLK_IPU_GATE>,
144 <&clks IMX5_CLK_IPU_DI0_GATE>,
145 <&clks IMX5_CLK_IPU_DI1_GATE>;
146 clock-names = "bus", "di0", "di1";
158 #address-cells = <1>;
162 ipu_di0_disp0: endpoint@0 {
166 ipu_di0_lvds0: endpoint@1 {
168 remote-endpoint = <&lvds0_in>;
173 #address-cells = <1>;
177 ipu_di1_disp1: endpoint@0 {
181 ipu_di1_lvds1: endpoint@1 {
183 remote-endpoint = <&lvds1_in>;
186 ipu_di1_tve: endpoint@2 {
188 remote-endpoint = <&tve_in>;
193 aips@50000000 { /* AIPS1 */
194 compatible = "fsl,aips-bus", "simple-bus";
195 #address-cells = <1>;
197 reg = <0x50000000 0x10000000>;
201 compatible = "fsl,spba-bus", "simple-bus";
202 #address-cells = <1>;
204 reg = <0x50000000 0x40000>;
207 esdhc1: esdhc@50004000 {
208 compatible = "fsl,imx53-esdhc";
209 reg = <0x50004000 0x4000>;
211 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
212 <&clks IMX5_CLK_DUMMY>,
213 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
214 clock-names = "ipg", "ahb", "per";
219 esdhc2: esdhc@50008000 {
220 compatible = "fsl,imx53-esdhc";
221 reg = <0x50008000 0x4000>;
223 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
224 <&clks IMX5_CLK_DUMMY>,
225 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
226 clock-names = "ipg", "ahb", "per";
231 uart3: serial@5000c000 {
232 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
233 reg = <0x5000c000 0x4000>;
235 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
236 <&clks IMX5_CLK_UART3_PER_GATE>;
237 clock-names = "ipg", "per";
238 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
239 dma-names = "rx", "tx";
243 ecspi1: ecspi@50010000 {
244 #address-cells = <1>;
246 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
247 reg = <0x50010000 0x4000>;
249 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
250 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
251 clock-names = "ipg", "per";
256 #sound-dai-cells = <0>;
257 compatible = "fsl,imx53-ssi",
260 reg = <0x50014000 0x4000>;
262 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
263 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
264 clock-names = "ipg", "baud";
265 dmas = <&sdma 24 1 0>,
267 dma-names = "rx", "tx";
268 fsl,fifo-depth = <15>;
272 esdhc3: esdhc@50020000 {
273 compatible = "fsl,imx53-esdhc";
274 reg = <0x50020000 0x4000>;
276 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
277 <&clks IMX5_CLK_DUMMY>,
278 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
279 clock-names = "ipg", "ahb", "per";
284 esdhc4: esdhc@50024000 {
285 compatible = "fsl,imx53-esdhc";
286 reg = <0x50024000 0x4000>;
288 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
289 <&clks IMX5_CLK_DUMMY>,
290 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
291 clock-names = "ipg", "ahb", "per";
297 aipstz1: bridge@53f00000 {
298 compatible = "fsl,imx53-aipstz";
299 reg = <0x53f00000 0x60>;
303 compatible = "usb-nop-xceiv";
304 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
305 clock-names = "main_clk";
310 compatible = "usb-nop-xceiv";
311 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
312 clock-names = "main_clk";
316 usbotg: usb@53f80000 {
317 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
318 reg = <0x53f80000 0x0200>;
320 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
321 fsl,usbmisc = <&usbmisc 0>;
322 fsl,usbphy = <&usbphy0>;
326 usbh1: usb@53f80200 {
327 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
328 reg = <0x53f80200 0x0200>;
330 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
331 fsl,usbmisc = <&usbmisc 1>;
332 fsl,usbphy = <&usbphy1>;
337 usbh2: usb@53f80400 {
338 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
339 reg = <0x53f80400 0x0200>;
341 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
342 fsl,usbmisc = <&usbmisc 2>;
347 usbh3: usb@53f80600 {
348 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
349 reg = <0x53f80600 0x0200>;
351 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
352 fsl,usbmisc = <&usbmisc 3>;
357 usbmisc: usbmisc@53f80800 {
359 compatible = "fsl,imx53-usbmisc";
360 reg = <0x53f80800 0x200>;
361 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
364 gpio1: gpio@53f84000 {
365 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
366 reg = <0x53f84000 0x4000>;
367 interrupts = <50 51>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
374 gpio2: gpio@53f88000 {
375 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
376 reg = <0x53f88000 0x4000>;
377 interrupts = <52 53>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
384 gpio3: gpio@53f8c000 {
385 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
386 reg = <0x53f8c000 0x4000>;
387 interrupts = <54 55>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
394 gpio4: gpio@53f90000 {
395 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
396 reg = <0x53f90000 0x4000>;
397 interrupts = <56 57>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
405 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
406 reg = <0x53f94000 0x4000>;
408 clocks = <&clks IMX5_CLK_DUMMY>;
412 wdog1: wdog@53f98000 {
413 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
414 reg = <0x53f98000 0x4000>;
416 clocks = <&clks IMX5_CLK_DUMMY>;
419 wdog2: wdog@53f9c000 {
420 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
421 reg = <0x53f9c000 0x4000>;
423 clocks = <&clks IMX5_CLK_DUMMY>;
427 gpt: timer@53fa0000 {
428 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
429 reg = <0x53fa0000 0x4000>;
431 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
432 <&clks IMX5_CLK_GPT_HF_GATE>;
433 clock-names = "ipg", "per";
436 srtc: srtc@53fa4000 {
437 compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
438 reg = <0x53fa4000 0x4000>;
440 interrupt-parent = <&tzic>;
441 clocks = <&clks IMX5_CLK_SRTC_GATE>;
445 iomuxc: iomuxc@53fa8000 {
446 compatible = "fsl,imx53-iomuxc";
447 reg = <0x53fa8000 0x4000>;
450 gpr: iomuxc-gpr@53fa8000 {
451 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
452 reg = <0x53fa8000 0xc>;
456 #address-cells = <1>;
458 compatible = "fsl,imx53-ldb";
459 reg = <0x53fa8008 0x4>;
461 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
462 <&clks IMX5_CLK_LDB_DI1_SEL>,
463 <&clks IMX5_CLK_IPU_DI0_SEL>,
464 <&clks IMX5_CLK_IPU_DI1_SEL>,
465 <&clks IMX5_CLK_LDB_DI0_GATE>,
466 <&clks IMX5_CLK_LDB_DI1_GATE>;
467 clock-names = "di0_pll", "di1_pll",
468 "di0_sel", "di1_sel",
473 #address-cells = <1>;
482 remote-endpoint = <&ipu_di0_lvds0>;
488 #address-cells = <1>;
497 remote-endpoint = <&ipu_di1_lvds1>;
505 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
506 reg = <0x53fb4000 0x4000>;
507 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
508 <&clks IMX5_CLK_PWM1_HF_GATE>;
509 clock-names = "ipg", "per";
515 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
516 reg = <0x53fb8000 0x4000>;
517 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
518 <&clks IMX5_CLK_PWM2_HF_GATE>;
519 clock-names = "ipg", "per";
523 uart1: serial@53fbc000 {
524 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
525 reg = <0x53fbc000 0x4000>;
527 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
528 <&clks IMX5_CLK_UART1_PER_GATE>;
529 clock-names = "ipg", "per";
530 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
531 dma-names = "rx", "tx";
535 uart2: serial@53fc0000 {
536 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
537 reg = <0x53fc0000 0x4000>;
539 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
540 <&clks IMX5_CLK_UART2_PER_GATE>;
541 clock-names = "ipg", "per";
542 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
543 dma-names = "rx", "tx";
548 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
549 reg = <0x53fc8000 0x4000>;
551 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
552 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
553 clock-names = "ipg", "per";
558 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
559 reg = <0x53fcc000 0x4000>;
561 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
562 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
563 clock-names = "ipg", "per";
568 compatible = "fsl,imx53-src", "fsl,imx51-src";
569 reg = <0x53fd0000 0x4000>;
574 compatible = "fsl,imx53-ccm";
575 reg = <0x53fd4000 0x4000>;
576 interrupts = <0 71 0x04 0 72 0x04>;
580 gpio5: gpio@53fdc000 {
581 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
582 reg = <0x53fdc000 0x4000>;
583 interrupts = <103 104>;
586 interrupt-controller;
587 #interrupt-cells = <2>;
590 gpio6: gpio@53fe0000 {
591 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
592 reg = <0x53fe0000 0x4000>;
593 interrupts = <105 106>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
600 gpio7: gpio@53fe4000 {
601 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
602 reg = <0x53fe4000 0x4000>;
603 interrupts = <107 108>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
611 #address-cells = <1>;
613 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
614 reg = <0x53fec000 0x4000>;
616 clocks = <&clks IMX5_CLK_I2C3_GATE>;
620 uart4: serial@53ff0000 {
621 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
622 reg = <0x53ff0000 0x4000>;
624 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
625 <&clks IMX5_CLK_UART4_PER_GATE>;
626 clock-names = "ipg", "per";
627 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
628 dma-names = "rx", "tx";
633 aips@60000000 { /* AIPS2 */
634 compatible = "fsl,aips-bus", "simple-bus";
635 #address-cells = <1>;
637 reg = <0x60000000 0x10000000>;
640 aipstz2: bridge@63f00000 {
641 compatible = "fsl,imx53-aipstz";
642 reg = <0x63f00000 0x60>;
646 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
647 reg = <0x63f98000 0x4000>;
649 clocks = <&clks IMX5_CLK_IIM_GATE>;
652 uart5: serial@63f90000 {
653 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
654 reg = <0x63f90000 0x4000>;
656 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
657 <&clks IMX5_CLK_UART5_PER_GATE>;
658 clock-names = "ipg", "per";
659 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
660 dma-names = "rx", "tx";
664 owire: owire@63fa4000 {
665 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
666 reg = <0x63fa4000 0x4000>;
667 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
671 ecspi2: ecspi@63fac000 {
672 #address-cells = <1>;
674 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
675 reg = <0x63fac000 0x4000>;
677 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
678 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
679 clock-names = "ipg", "per";
683 sdma: sdma@63fb0000 {
684 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
685 reg = <0x63fb0000 0x4000>;
687 clocks = <&clks IMX5_CLK_SDMA_GATE>,
688 <&clks IMX5_CLK_SDMA_GATE>;
689 clock-names = "ipg", "ahb";
691 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
694 cspi: cspi@63fc0000 {
695 #address-cells = <1>;
697 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
698 reg = <0x63fc0000 0x4000>;
700 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
701 <&clks IMX5_CLK_CSPI_IPG_GATE>;
702 clock-names = "ipg", "per";
707 #address-cells = <1>;
709 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
710 reg = <0x63fc4000 0x4000>;
712 clocks = <&clks IMX5_CLK_I2C2_GATE>;
717 #address-cells = <1>;
719 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
720 reg = <0x63fc8000 0x4000>;
722 clocks = <&clks IMX5_CLK_I2C1_GATE>;
727 #sound-dai-cells = <0>;
728 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
730 reg = <0x63fcc000 0x4000>;
732 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
733 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
734 clock-names = "ipg", "baud";
735 dmas = <&sdma 28 0 0>,
737 dma-names = "rx", "tx";
738 fsl,fifo-depth = <15>;
742 audmux: audmux@63fd0000 {
743 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
744 reg = <0x63fd0000 0x4000>;
749 compatible = "fsl,imx53-nand";
750 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
752 clocks = <&clks IMX5_CLK_NFC_GATE>;
757 #sound-dai-cells = <0>;
758 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
760 reg = <0x63fe8000 0x4000>;
762 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
763 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
764 clock-names = "ipg", "baud";
765 dmas = <&sdma 46 0 0>,
767 dma-names = "rx", "tx";
768 fsl,fifo-depth = <15>;
772 fec: ethernet@63fec000 {
773 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
774 reg = <0x63fec000 0x4000>;
776 clocks = <&clks IMX5_CLK_FEC_GATE>,
777 <&clks IMX5_CLK_FEC_GATE>,
778 <&clks IMX5_CLK_FEC_GATE>;
779 clock-names = "ipg", "ahb", "ptp";
784 compatible = "fsl,imx53-tve";
785 reg = <0x63ff0000 0x1000>;
787 clocks = <&clks IMX5_CLK_TVE_GATE>,
788 <&clks IMX5_CLK_IPU_DI1_SEL>;
789 clock-names = "tve", "di_sel";
794 remote-endpoint = <&ipu_di1_tve>;
800 compatible = "fsl,imx53-vpu", "cnm,coda7541";
801 reg = <0x63ff4000 0x1000>;
803 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
804 <&clks IMX5_CLK_VPU_GATE>;
805 clock-names = "per", "ahb";
810 sahara: crypto@63ff8000 {
811 compatible = "fsl,imx53-sahara";
812 reg = <0x63ff8000 0x4000>;
813 interrupts = <19 20>;
814 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
815 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
816 clock-names = "ipg", "ahb";
820 ocram: sram@f8000000 {
821 compatible = "mmio-sram";
822 reg = <0xf8000000 0x20000>;
823 clocks = <&clks IMX5_CLK_OCRAM>;
827 compatible = "arm,cortex-a8-pmu";