arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15 #include <dt-bindings/clock/imx5-clock.h>
  16
  17 / {
  18         aliases {
  19                 gpio0 = &gpio1;
  20                 gpio1 = &gpio2;
  21                 gpio2 = &gpio3;
  22                 gpio3 = &gpio4;
  23                 gpio4 = &gpio5;
  24                 gpio5 = &gpio6;
  25                 gpio6 = &gpio7;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 spi0 = &ecspi1;
  35                 spi1 = &ecspi2;
  36                 spi2 = &cspi;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42                 cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a8";
  45                         reg = <0x0>;
  46                 };
  47         };
  48
  49         tzic: tz-interrupt-controller@0fffc000 {
  50                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  51                 interrupt-controller;
  52                 #interrupt-cells = <1>;
  53                 reg = <0x0fffc000 0x4000>;
  54         };
  55
  56         clocks {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 ckil {
  61                         compatible = "fsl,imx-ckil", "fixed-clock";
  62                         clock-frequency = <32768>;
  63                 };
  64
  65                 ckih1 {
  66                         compatible = "fsl,imx-ckih1", "fixed-clock";
  67                         clock-frequency = <22579200>;
  68                 };
  69
  70                 ckih2 {
  71                         compatible = "fsl,imx-ckih2", "fixed-clock";
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 osc {
  76                         compatible = "fsl,imx-osc", "fixed-clock";
  77                         clock-frequency = <24000000>;
  78                 };
  79         };
  80
  81         soc {
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 compatible = "simple-bus";
  85                 interrupt-parent = <&tzic>;
  86                 ranges;
  87
  88                 sata: sata@10000000 {
  89                         compatible = "fsl,imx53-ahci";
  90                         reg = <0x10000000 0x1000>;
  91                         interrupts = <28>;
  92                         clocks = <&clks IMX5_CLK_SATA_GATE>,
  93                                  <&clks IMX5_CLK_SATA_REF>,
  94                                  <&clks IMX5_CLK_AHB>;
  95                         clock-names = "sata_gate", "sata_ref", "ahb";
  96                         status = "disabled";
  97                 };
  98
  99                 ipu: ipu@18000000 {
 100                         #crtc-cells = <1>;
 101                         compatible = "fsl,imx53-ipu";
 102                         reg = <0x18000000 0x080000000>;
 103                         interrupts = <11 10>;
 104                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 105                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 106                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 107                         clock-names = "bus", "di0", "di1";
 108                         resets = <&src 2>;
 109                 };
 110
 111                 aips@50000000 { /* AIPS1 */
 112                         compatible = "fsl,aips-bus", "simple-bus";
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         reg = <0x50000000 0x10000000>;
 116                         ranges;
 117
 118                         spba@50000000 {
 119                                 compatible = "fsl,spba-bus", "simple-bus";
 120                                 #address-cells = <1>;
 121                                 #size-cells = <1>;
 122                                 reg = <0x50000000 0x40000>;
 123                                 ranges;
 124
 125                                 esdhc1: esdhc@50004000 {
 126                                         compatible = "fsl,imx53-esdhc";
 127                                         reg = <0x50004000 0x4000>;
 128                                         interrupts = <1>;
 129                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 130                                                  <&clks IMX5_CLK_DUMMY>,
 131                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 132                                         clock-names = "ipg", "ahb", "per";
 133                                         bus-width = <4>;
 134                                         status = "disabled";
 135                                 };
 136
 137                                 esdhc2: esdhc@50008000 {
 138                                         compatible = "fsl,imx53-esdhc";
 139                                         reg = <0x50008000 0x4000>;
 140                                         interrupts = <2>;
 141                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 142                                                  <&clks IMX5_CLK_DUMMY>,
 143                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 144                                         clock-names = "ipg", "ahb", "per";
 145                                         bus-width = <4>;
 146                                         status = "disabled";
 147                                 };
 148
 149                                 uart3: serial@5000c000 {
 150                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 151                                         reg = <0x5000c000 0x4000>;
 152                                         interrupts = <33>;
 153                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 154                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 155                                         clock-names = "ipg", "per";
 156                                         status = "disabled";
 157                                 };
 158
 159                                 ecspi1: ecspi@50010000 {
 160                                         #address-cells = <1>;
 161                                         #size-cells = <0>;
 162                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 163                                         reg = <0x50010000 0x4000>;
 164                                         interrupts = <36>;
 165                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 166                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 167                                         clock-names = "ipg", "per";
 168                                         status = "disabled";
 169                                 };
 170
 171                                 ssi2: ssi@50014000 {
 172                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 173                                         reg = <0x50014000 0x4000>;
 174                                         interrupts = <30>;
 175                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
 176                                         dmas = <&sdma 24 1 0>,
 177                                                <&sdma 25 1 0>;
 178                                         dma-names = "rx", "tx";
 179                                         fsl,fifo-depth = <15>;
 180                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 181                                         status = "disabled";
 182                                 };
 183
 184                                 esdhc3: esdhc@50020000 {
 185                                         compatible = "fsl,imx53-esdhc";
 186                                         reg = <0x50020000 0x4000>;
 187                                         interrupts = <3>;
 188                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 189                                                  <&clks IMX5_CLK_DUMMY>,
 190                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 191                                         clock-names = "ipg", "ahb", "per";
 192                                         bus-width = <4>;
 193                                         status = "disabled";
 194                                 };
 195
 196                                 esdhc4: esdhc@50024000 {
 197                                         compatible = "fsl,imx53-esdhc";
 198                                         reg = <0x50024000 0x4000>;
 199                                         interrupts = <4>;
 200                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 201                                                  <&clks IMX5_CLK_DUMMY>,
 202                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 203                                         clock-names = "ipg", "ahb", "per";
 204                                         bus-width = <4>;
 205                                         status = "disabled";
 206                                 };
 207                         };
 208
 209                         usbphy0: usbphy@0 {
 210                                 compatible = "usb-nop-xceiv";
 211                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 212                                 clock-names = "main_clk";
 213                                 status = "okay";
 214                         };
 215
 216                         usbphy1: usbphy@1 {
 217                                 compatible = "usb-nop-xceiv";
 218                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 219                                 clock-names = "main_clk";
 220                                 status = "okay";
 221                         };
 222
 223                         usbotg: usb@53f80000 {
 224                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 225                                 reg = <0x53f80000 0x0200>;
 226                                 interrupts = <18>;
 227                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 228                                 fsl,usbmisc = <&usbmisc 0>;
 229                                 fsl,usbphy = <&usbphy0>;
 230                                 status = "disabled";
 231                         };
 232
 233                         usbh1: usb@53f80200 {
 234                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 235                                 reg = <0x53f80200 0x0200>;
 236                                 interrupts = <14>;
 237                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 238                                 fsl,usbmisc = <&usbmisc 1>;
 239                                 fsl,usbphy = <&usbphy1>;
 240                                 status = "disabled";
 241                         };
 242
 243                         usbh2: usb@53f80400 {
 244                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 245                                 reg = <0x53f80400 0x0200>;
 246                                 interrupts = <16>;
 247                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 248                                 fsl,usbmisc = <&usbmisc 2>;
 249                                 status = "disabled";
 250                         };
 251
 252                         usbh3: usb@53f80600 {
 253                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 254                                 reg = <0x53f80600 0x0200>;
 255                                 interrupts = <17>;
 256                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 257                                 fsl,usbmisc = <&usbmisc 3>;
 258                                 status = "disabled";
 259                         };
 260
 261                         usbmisc: usbmisc@53f80800 {
 262                                 #index-cells = <1>;
 263                                 compatible = "fsl,imx53-usbmisc";
 264                                 reg = <0x53f80800 0x200>;
 265                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 266                         };
 267
 268                         gpio1: gpio@53f84000 {
 269                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 270                                 reg = <0x53f84000 0x4000>;
 271                                 interrupts = <50 51>;
 272                                 gpio-controller;
 273                                 #gpio-cells = <2>;
 274                                 interrupt-controller;
 275                                 #interrupt-cells = <2>;
 276                         };
 277
 278                         gpio2: gpio@53f88000 {
 279                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 280                                 reg = <0x53f88000 0x4000>;
 281                                 interrupts = <52 53>;
 282                                 gpio-controller;
 283                                 #gpio-cells = <2>;
 284                                 interrupt-controller;
 285                                 #interrupt-cells = <2>;
 286                         };
 287
 288                         gpio3: gpio@53f8c000 {
 289                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 290                                 reg = <0x53f8c000 0x4000>;
 291                                 interrupts = <54 55>;
 292                                 gpio-controller;
 293                                 #gpio-cells = <2>;
 294                                 interrupt-controller;
 295                                 #interrupt-cells = <2>;
 296                         };
 297
 298                         gpio4: gpio@53f90000 {
 299                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 300                                 reg = <0x53f90000 0x4000>;
 301                                 interrupts = <56 57>;
 302                                 gpio-controller;
 303                                 #gpio-cells = <2>;
 304                                 interrupt-controller;
 305                                 #interrupt-cells = <2>;
 306                         };
 307
 308                         kpp: kpp@53f94000 {
 309                                 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
 310                                 reg = <0x53f94000 0x4000>;
 311                                 interrupts = <60>;
 312                                 clocks = <&clks IMX5_CLK_DUMMY>;
 313                                 status = "disabled";
 314                         };
 315
 316                         wdog1: wdog@53f98000 {
 317                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 318                                 reg = <0x53f98000 0x4000>;
 319                                 interrupts = <58>;
 320                                 clocks = <&clks IMX5_CLK_DUMMY>;
 321                         };
 322
 323                         wdog2: wdog@53f9c000 {
 324                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 325                                 reg = <0x53f9c000 0x4000>;
 326                                 interrupts = <59>;
 327                                 clocks = <&clks IMX5_CLK_DUMMY>;
 328                                 status = "disabled";
 329                         };
 330
 331                         gpt: timer@53fa0000 {
 332                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 333                                 reg = <0x53fa0000 0x4000>;
 334                                 interrupts = <39>;
 335                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 336                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 337                                 clock-names = "ipg", "per";
 338                         };
 339
 340                         iomuxc: iomuxc@53fa8000 {
 341                                 compatible = "fsl,imx53-iomuxc";
 342                                 reg = <0x53fa8000 0x4000>;
 343                         };
 344
 345                         gpr: iomuxc-gpr@53fa8000 {
 346                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 347                                 reg = <0x53fa8000 0xc>;
 348                         };
 349
 350                         ldb: ldb@53fa8008 {
 351                                 #address-cells = <1>;
 352                                 #size-cells = <0>;
 353                                 compatible = "fsl,imx53-ldb";
 354                                 reg = <0x53fa8008 0x4>;
 355                                 gpr = <&gpr>;
 356                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 357                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 358                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 359                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 360                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 361                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 362                                 clock-names = "di0_pll", "di1_pll",
 363                                               "di0_sel", "di1_sel",
 364                                               "di0", "di1";
 365                                 status = "disabled";
 366
 367                                 lvds-channel@0 {
 368                                         reg = <0>;
 369                                         crtcs = <&ipu 0>;
 370                                         status = "disabled";
 371                                 };
 372
 373                                 lvds-channel@1 {
 374                                         reg = <1>;
 375                                         crtcs = <&ipu 1>;
 376                                         status = "disabled";
 377                                 };
 378                         };
 379
 380                         pwm1: pwm@53fb4000 {
 381                                 #pwm-cells = <2>;
 382                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 383                                 reg = <0x53fb4000 0x4000>;
 384                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 385                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 386                                 clock-names = "ipg", "per";
 387                                 interrupts = <61>;
 388                         };
 389
 390                         pwm2: pwm@53fb8000 {
 391                                 #pwm-cells = <2>;
 392                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 393                                 reg = <0x53fb8000 0x4000>;
 394                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 395                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 396                                 clock-names = "ipg", "per";
 397                                 interrupts = <94>;
 398                         };
 399
 400                         uart1: serial@53fbc000 {
 401                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 402                                 reg = <0x53fbc000 0x4000>;
 403                                 interrupts = <31>;
 404                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 405                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 406                                 clock-names = "ipg", "per";
 407                                 status = "disabled";
 408                         };
 409
 410                         uart2: serial@53fc0000 {
 411                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 412                                 reg = <0x53fc0000 0x4000>;
 413                                 interrupts = <32>;
 414                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 415                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 416                                 clock-names = "ipg", "per";
 417                                 status = "disabled";
 418                         };
 419
 420                         can1: can@53fc8000 {
 421                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 422                                 reg = <0x53fc8000 0x4000>;
 423                                 interrupts = <82>;
 424                                 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
 425                                          <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
 426                                 clock-names = "ipg", "per";
 427                                 status = "disabled";
 428                         };
 429
 430                         can2: can@53fcc000 {
 431                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 432                                 reg = <0x53fcc000 0x4000>;
 433                                 interrupts = <83>;
 434                                 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
 435                                          <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
 436                                 clock-names = "ipg", "per";
 437                                 status = "disabled";
 438                         };
 439
 440                         src: src@53fd0000 {
 441                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 442                                 reg = <0x53fd0000 0x4000>;
 443                                 #reset-cells = <1>;
 444                         };
 445
 446                         clks: ccm@53fd4000{
 447                                 compatible = "fsl,imx53-ccm";
 448                                 reg = <0x53fd4000 0x4000>;
 449                                 interrupts = <0 71 0x04 0 72 0x04>;
 450                                 #clock-cells = <1>;
 451                         };
 452
 453                         gpio5: gpio@53fdc000 {
 454                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 455                                 reg = <0x53fdc000 0x4000>;
 456                                 interrupts = <103 104>;
 457                                 gpio-controller;
 458                                 #gpio-cells = <2>;
 459                                 interrupt-controller;
 460                                 #interrupt-cells = <2>;
 461                         };
 462
 463                         gpio6: gpio@53fe0000 {
 464                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x53fe0000 0x4000>;
 466                                 interrupts = <105 106>;
 467                                 gpio-controller;
 468                                 #gpio-cells = <2>;
 469                                 interrupt-controller;
 470                                 #interrupt-cells = <2>;
 471                         };
 472
 473                         gpio7: gpio@53fe4000 {
 474                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 475                                 reg = <0x53fe4000 0x4000>;
 476                                 interrupts = <107 108>;
 477                                 gpio-controller;
 478                                 #gpio-cells = <2>;
 479                                 interrupt-controller;
 480                                 #interrupt-cells = <2>;
 481                         };
 482
 483                         i2c3: i2c@53fec000 {
 484                                 #address-cells = <1>;
 485                                 #size-cells = <0>;
 486                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 487                                 reg = <0x53fec000 0x4000>;
 488                                 interrupts = <64>;
 489                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 490                                 status = "disabled";
 491                         };
 492
 493                         uart4: serial@53ff0000 {
 494                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 495                                 reg = <0x53ff0000 0x4000>;
 496                                 interrupts = <13>;
 497                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 498                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 499                                 clock-names = "ipg", "per";
 500                                 status = "disabled";
 501                         };
 502                 };
 503
 504                 aips@60000000 { /* AIPS2 */
 505                         compatible = "fsl,aips-bus", "simple-bus";
 506                         #address-cells = <1>;
 507                         #size-cells = <1>;
 508                         reg = <0x60000000 0x10000000>;
 509                         ranges;
 510
 511                         iim: iim@63f98000 {
 512                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 513                                 reg = <0x63f98000 0x4000>;
 514                                 interrupts = <69>;
 515                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 516                         };
 517
 518                         uart5: serial@63f90000 {
 519                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 520                                 reg = <0x63f90000 0x4000>;
 521                                 interrupts = <86>;
 522                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 523                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 524                                 clock-names = "ipg", "per";
 525                                 status = "disabled";
 526                         };
 527
 528                         owire: owire@63fa4000 {
 529                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 530                                 reg = <0x63fa4000 0x4000>;
 531                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 532                                 status = "disabled";
 533                         };
 534
 535                         ecspi2: ecspi@63fac000 {
 536                                 #address-cells = <1>;
 537                                 #size-cells = <0>;
 538                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 539                                 reg = <0x63fac000 0x4000>;
 540                                 interrupts = <37>;
 541                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 542                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 543                                 clock-names = "ipg", "per";
 544                                 status = "disabled";
 545                         };
 546
 547                         sdma: sdma@63fb0000 {
 548                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 549                                 reg = <0x63fb0000 0x4000>;
 550                                 interrupts = <6>;
 551                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 552                                          <&clks IMX5_CLK_SDMA_GATE>;
 553                                 clock-names = "ipg", "ahb";
 554                                 #dma-cells = <3>;
 555                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 556                         };
 557
 558                         cspi: cspi@63fc0000 {
 559                                 #address-cells = <1>;
 560                                 #size-cells = <0>;
 561                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 562                                 reg = <0x63fc0000 0x4000>;
 563                                 interrupts = <38>;
 564                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 565                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 566                                 clock-names = "ipg", "per";
 567                                 status = "disabled";
 568                         };
 569
 570                         i2c2: i2c@63fc4000 {
 571                                 #address-cells = <1>;
 572                                 #size-cells = <0>;
 573                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 574                                 reg = <0x63fc4000 0x4000>;
 575                                 interrupts = <63>;
 576                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 577                                 status = "disabled";
 578                         };
 579
 580                         i2c1: i2c@63fc8000 {
 581                                 #address-cells = <1>;
 582                                 #size-cells = <0>;
 583                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 584                                 reg = <0x63fc8000 0x4000>;
 585                                 interrupts = <62>;
 586                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 587                                 status = "disabled";
 588                         };
 589
 590                         ssi1: ssi@63fcc000 {
 591                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 592                                 reg = <0x63fcc000 0x4000>;
 593                                 interrupts = <29>;
 594                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
 595                                 dmas = <&sdma 28 0 0>,
 596                                        <&sdma 29 0 0>;
 597                                 dma-names = "rx", "tx";
 598                                 fsl,fifo-depth = <15>;
 599                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 600                                 status = "disabled";
 601                         };
 602
 603                         audmux: audmux@63fd0000 {
 604                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 605                                 reg = <0x63fd0000 0x4000>;
 606                                 status = "disabled";
 607                         };
 608
 609                         nfc: nand@63fdb000 {
 610                                 compatible = "fsl,imx53-nand";
 611                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 612                                 interrupts = <8>;
 613                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 614                                 status = "disabled";
 615                         };
 616
 617                         ssi3: ssi@63fe8000 {
 618                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 619                                 reg = <0x63fe8000 0x4000>;
 620                                 interrupts = <96>;
 621                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
 622                                 dmas = <&sdma 46 0 0>,
 623                                        <&sdma 47 0 0>;
 624                                 dma-names = "rx", "tx";
 625                                 fsl,fifo-depth = <15>;
 626                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 627                                 status = "disabled";
 628                         };
 629
 630                         fec: ethernet@63fec000 {
 631                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 632                                 reg = <0x63fec000 0x4000>;
 633                                 interrupts = <87>;
 634                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 635                                          <&clks IMX5_CLK_FEC_GATE>,
 636                                          <&clks IMX5_CLK_FEC_GATE>;
 637                                 clock-names = "ipg", "ahb", "ptp";
 638                                 status = "disabled";
 639                         };
 640
 641                         tve: tve@63ff0000 {
 642                                 compatible = "fsl,imx53-tve";
 643                                 reg = <0x63ff0000 0x1000>;
 644                                 interrupts = <92>;
 645                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 646                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 647                                 clock-names = "tve", "di_sel";
 648                                 crtcs = <&ipu 1>;
 649                                 status = "disabled";
 650                         };
 651
 652                         vpu: vpu@63ff4000 {
 653                                 compatible = "fsl,imx53-vpu";
 654                                 reg = <0x63ff4000 0x1000>;
 655                                 interrupts = <9>;
 656                                 clocks = <&clks IMX5_CLK_VPU_GATE>,
 657                                          <&clks IMX5_CLK_VPU_GATE>;
 658                                 clock-names = "per", "ahb";
 659                                 iram = <&ocram>;
 660                                 status = "disabled";
 661                         };
 662                 };
 663
 664                 ocram: sram@f8000000 {
 665                         compatible = "mmio-sram";
 666                         reg = <0xf8000000 0x20000>;
 667                         clocks = <&clks IMX5_CLK_OCRAM>;
 668                 };
 669         };
 670 };