2 * Copyright 2012 Sascha Hauer, Pengutronix
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "skeleton.dtsi"
13 #include "imx27-pinfunc.h"
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/gpio/gpio.h>
38 aitc: aitc-interrupt-controller@e0000000 {
39 compatible = "fsl,imx27-aitc", "fsl,avic";
41 #interrupt-cells = <1>;
42 reg = <0x10040000 0x1000>;
50 compatible = "fsl,imx-osc26m", "fixed-clock";
52 clock-frequency = <26000000>;
62 compatible = "arm,arm926ej-s";
68 clock-latency = <62500>;
70 voltage-tolerance = <5>;
75 compatible = "simple-bus";
80 compatible = "usb-nop-xceiv";
83 clock-names = "main_clk";
87 compatible = "usb-nop-xceiv";
90 clock-names = "main_clk";
97 compatible = "simple-bus";
98 interrupt-parent = <&aitc>;
101 aipi@10000000 { /* AIPI1 */
102 compatible = "fsl,aipi-bus", "simple-bus";
103 #address-cells = <1>;
105 reg = <0x10000000 0x20000>;
109 compatible = "fsl,imx27-dma";
110 reg = <0x10001000 0x1000>;
112 clocks = <&clks 50>, <&clks 70>;
113 clock-names = "ipg", "ahb";
115 #dma-channels = <16>;
118 wdog: wdog@10002000 {
119 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
120 reg = <0x10002000 0x1000>;
125 gpt1: timer@10003000 {
126 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
127 reg = <0x10003000 0x1000>;
129 clocks = <&clks 46>, <&clks 61>;
130 clock-names = "ipg", "per";
133 gpt2: timer@10004000 {
134 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
135 reg = <0x10004000 0x1000>;
137 clocks = <&clks 45>, <&clks 61>;
138 clock-names = "ipg", "per";
141 gpt3: timer@10005000 {
142 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
143 reg = <0x10005000 0x1000>;
145 clocks = <&clks 44>, <&clks 61>;
146 clock-names = "ipg", "per";
151 compatible = "fsl,imx27-pwm";
152 reg = <0x10006000 0x1000>;
154 clocks = <&clks 34>, <&clks 61>;
155 clock-names = "ipg", "per";
159 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
160 reg = <0x10008000 0x1000>;
166 owire: owire@10009000 {
167 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
168 reg = <0x10009000 0x1000>;
173 uart1: serial@1000a000 {
174 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
175 reg = <0x1000a000 0x1000>;
177 clocks = <&clks 81>, <&clks 61>;
178 clock-names = "ipg", "per";
182 uart2: serial@1000b000 {
183 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
184 reg = <0x1000b000 0x1000>;
186 clocks = <&clks 80>, <&clks 61>;
187 clock-names = "ipg", "per";
191 uart3: serial@1000c000 {
192 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
193 reg = <0x1000c000 0x1000>;
195 clocks = <&clks 79>, <&clks 61>;
196 clock-names = "ipg", "per";
200 uart4: serial@1000d000 {
201 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
202 reg = <0x1000d000 0x1000>;
204 clocks = <&clks 78>, <&clks 61>;
205 clock-names = "ipg", "per";
209 cspi1: cspi@1000e000 {
210 #address-cells = <1>;
212 compatible = "fsl,imx27-cspi";
213 reg = <0x1000e000 0x1000>;
215 clocks = <&clks 53>, <&clks 60>;
216 clock-names = "ipg", "per";
220 cspi2: cspi@1000f000 {
221 #address-cells = <1>;
223 compatible = "fsl,imx27-cspi";
224 reg = <0x1000f000 0x1000>;
226 clocks = <&clks 52>, <&clks 60>;
227 clock-names = "ipg", "per";
232 #sound-dai-cells = <0>;
233 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
234 reg = <0x10010000 0x1000>;
237 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
238 dma-names = "rx0", "tx0", "rx1", "tx1";
239 fsl,fifo-depth = <8>;
244 #sound-dai-cells = <0>;
245 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
246 reg = <0x10011000 0x1000>;
249 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
250 dma-names = "rx0", "tx0", "rx1", "tx1";
251 fsl,fifo-depth = <8>;
256 #address-cells = <1>;
258 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
259 reg = <0x10012000 0x1000>;
265 sdhci1: sdhci@10013000 {
266 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
267 reg = <0x10013000 0x1000>;
269 clocks = <&clks 30>, <&clks 60>;
270 clock-names = "ipg", "per";
276 sdhci2: sdhci@10014000 {
277 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
278 reg = <0x10014000 0x1000>;
280 clocks = <&clks 29>, <&clks 60>;
281 clock-names = "ipg", "per";
287 iomuxc: iomuxc@10015000 {
288 compatible = "fsl,imx27-iomuxc";
289 reg = <0x10015000 0x600>;
290 #address-cells = <1>;
294 gpio1: gpio@10015000 {
295 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
296 reg = <0x10015000 0x100>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
304 gpio2: gpio@10015100 {
305 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
306 reg = <0x10015100 0x100>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
314 gpio3: gpio@10015200 {
315 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
316 reg = <0x10015200 0x100>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
324 gpio4: gpio@10015300 {
325 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
326 reg = <0x10015300 0x100>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
334 gpio5: gpio@10015400 {
335 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
336 reg = <0x10015400 0x100>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
344 gpio6: gpio@10015500 {
345 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
346 reg = <0x10015500 0x100>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
355 audmux: audmux@10016000 {
356 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
357 reg = <0x10016000 0x1000>;
359 clock-names = "audmux";
363 cspi3: cspi@10017000 {
364 #address-cells = <1>;
366 compatible = "fsl,imx27-cspi";
367 reg = <0x10017000 0x1000>;
369 clocks = <&clks 51>, <&clks 60>;
370 clock-names = "ipg", "per";
374 gpt4: timer@10019000 {
375 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
376 reg = <0x10019000 0x1000>;
378 clocks = <&clks 43>, <&clks 61>;
379 clock-names = "ipg", "per";
382 gpt5: timer@1001a000 {
383 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
384 reg = <0x1001a000 0x1000>;
386 clocks = <&clks 42>, <&clks 61>;
387 clock-names = "ipg", "per";
390 uart5: serial@1001b000 {
391 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
392 reg = <0x1001b000 0x1000>;
394 clocks = <&clks 77>, <&clks 61>;
395 clock-names = "ipg", "per";
399 uart6: serial@1001c000 {
400 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
401 reg = <0x1001c000 0x1000>;
403 clocks = <&clks 78>, <&clks 61>;
404 clock-names = "ipg", "per";
409 #address-cells = <1>;
411 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
412 reg = <0x1001d000 0x1000>;
418 sdhci3: sdhci@1001e000 {
419 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
420 reg = <0x1001e000 0x1000>;
422 clocks = <&clks 28>, <&clks 60>;
423 clock-names = "ipg", "per";
429 gpt6: timer@1001f000 {
430 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
431 reg = <0x1001f000 0x1000>;
433 clocks = <&clks 41>, <&clks 61>;
434 clock-names = "ipg", "per";
438 aipi@10020000 { /* AIPI2 */
439 compatible = "fsl,aipi-bus", "simple-bus";
440 #address-cells = <1>;
442 reg = <0x10020000 0x20000>;
446 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
448 reg = <0x10021000 0x1000>;
449 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
450 clock-names = "ipg", "ahb", "per";
454 coda: coda@10023000 {
455 compatible = "fsl,imx27-vpu";
456 reg = <0x10023000 0x0200>;
458 clocks = <&clks 57>, <&clks 66>;
459 clock-names = "per", "ahb";
463 usbotg: usb@10024000 {
464 compatible = "fsl,imx27-usb";
465 reg = <0x10024000 0x200>;
468 fsl,usbmisc = <&usbmisc 0>;
469 fsl,usbphy = <&usbphy0>;
473 usbh1: usb@10024200 {
474 compatible = "fsl,imx27-usb";
475 reg = <0x10024200 0x200>;
478 fsl,usbmisc = <&usbmisc 1>;
482 usbh2: usb@10024400 {
483 compatible = "fsl,imx27-usb";
484 reg = <0x10024400 0x200>;
487 fsl,usbmisc = <&usbmisc 2>;
488 fsl,usbphy = <&usbphy2>;
492 usbmisc: usbmisc@10024600 {
494 compatible = "fsl,imx27-usbmisc";
495 reg = <0x10024600 0x200>;
499 sahara2: sahara@10025000 {
500 compatible = "fsl,imx27-sahara";
501 reg = <0x10025000 0x1000>;
503 clocks = <&clks 32>, <&clks 64>;
504 clock-names = "ipg", "ahb";
508 compatible = "fsl,imx27-ccm";
509 reg = <0x10027000 0x1000>;
514 compatible = "fsl,imx27-iim";
515 reg = <0x10028000 0x1000>;
520 fec: ethernet@1002b000 {
521 compatible = "fsl,imx27-fec";
522 reg = <0x1002b000 0x4000>;
524 clocks = <&clks 48>, <&clks 67>;
525 clock-names = "ipg", "ahb";
531 #address-cells = <1>;
533 compatible = "fsl,imx27-nand";
534 reg = <0xd8000000 0x1000>;
540 weim: weim@d8002000 {
541 #address-cells = <2>;
543 compatible = "fsl,imx27-weim";
544 reg = <0xd8002000 0x1000>;
547 0 0 0xc0000000 0x08000000
548 1 0 0xc8000000 0x08000000
549 2 0 0xd0000000 0x02000000
550 3 0 0xd2000000 0x02000000
551 4 0 0xd4000000 0x02000000
552 5 0 0xd6000000 0x02000000
557 iram: iram@ffff4c00 {
558 compatible = "mmio-sram";
559 reg = <0xffff4c00 0xb400>;