arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts

   1 /*
   2  * The code contained herein is licensed under the GNU General Public
   3  * License. You may obtain a copy of the GNU General Public License
   4  * Version 2 or later at the following locations:
   5  *
   6  * http://www.opensource.org/licenses/gpl-license.html
   7  * http://www.gnu.org/copyleft/gpl.html
   8  */
   9
  10 #include "imx27-phytec-phycore-som.dts"
  11
  12 / {
  13         model = "Phytec pcm970";
  14         compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
  15 };
  16
  17 &cspi1 {
  18         fsl,spi-num-chipselects = <2>;
  19         cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
  20 };
  21
  22 &i2c1 {
  23         clock-frequency = <400000>;
  24         pinctrl-names = "default";
  25         pinctrl-0 = <&pinctrl_i2c1>;
  26         status = "okay";
  27
  28         camgpio: pca9536@41 {
  29                 compatible = "nxp,pca9536";
  30                 reg = <0x41>;
  31                 gpio-controller;
  32                 #gpio-cells = <2>;
  33         };
  34 };
  35
  36 &iomuxc {
  37         imx27_phycore_rdk {
  38                 pinctrl_i2c1: i2c1grp {
  39                         /* Add pullup to DATA line */
  40                         fsl,pins = <
  41                                 MX27_PAD_I2C_DATA__I2C_DATA     0x1
  42                                 MX27_PAD_I2C_CLK__I2C_CLK       0x0
  43                         >;
  44                 };
  45
  46                 pinctrl_uart1: uart1grp {
  47                         fsl,pins = <
  48                                 MX27_PAD_UART1_TXD__UART1_TXD 0x0
  49                                 MX27_PAD_UART1_RXD__UART1_RXD 0x0
  50                                 MX27_PAD_UART1_CTS__UART1_CTS 0x0
  51                                 MX27_PAD_UART1_RTS__UART1_RTS 0x0
  52                         >;
  53                 };
  54
  55                 pinctrl_uart2: uart2grp {
  56                         fsl,pins = <
  57                                 MX27_PAD_UART2_TXD__UART2_TXD 0x0
  58                                 MX27_PAD_UART2_RXD__UART2_RXD 0x0
  59                                 MX27_PAD_UART2_CTS__UART2_CTS 0x0
  60                                 MX27_PAD_UART2_RTS__UART2_RTS 0x0
  61                         >;
  62                 };
  63         };
  64 };
  65
  66 &sdhci2 {
  67         bus-width = <4>;
  68         cd-gpios = <&gpio3 29 0>;
  69         wp-gpios = <&gpio3 28 0>;
  70         vmmc-supply = <&vmmc1_reg>;
  71         status = "okay";
  72 };
  73
  74 &uart1 {
  75         fsl,uart-has-rtscts;
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_uart1>;
  78         status = "okay";
  79 };
  80
  81 &uart2 {
  82         fsl,uart-has-rtscts;
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_uart2>;
  85         status = "okay";
  86 };
  87
  88 &weim {
  89         can@d4000000 {
  90                 compatible = "nxp,sja1000";
  91                 reg = <4 0x00000000 0x00000100>;
  92                 interrupt-parent = <&gpio5>;
  93                 interrupts = <19 0x2>;
  94                 nxp,external-clock-frequency = <16000000>;
  95                 nxp,tx-output-config = <0x16>;
  96                 nxp,no-comparator-bypass;
  97                 fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
  98         };
  99 };