2 * Copyright 2012 Markus Pargmann, Pengutronix
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "imx27-phytec-phycard-s-som.dts"
15 model = "Phytec pca100 rapid development kit";
16 compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
19 model = "Primeview-PD050VL1";
20 native-mode = <&timing0>;
21 bits-per-pixel = <16>; /* non-standard but required */
22 fsl,pcr = <0xf0c88080>; /* non-standard but required */
33 clock-frequency = <25000000>;
39 compatible = "simple-bus";
43 reg_3v3: regulator@0 {
44 compatible = "regulator-fixed";
46 regulator-name = "3V3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_i2c1>;
65 compatible = "nxp,pcf8563";
70 compatible = "maxim,max1037";
71 vcc-supply = <®_3v3>;
78 pinctrl_i2c1: i2c1grp {
80 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
81 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
85 pinctrl_owire1: owire1grp {
87 MX27_PAD_RTCK__OWIRE 0x0
91 pinctrl_uart1: uart1grp {
93 MX27_PAD_UART1_TXD__UART1_TXD 0x0
94 MX27_PAD_UART1_RXD__UART1_RXD 0x0
95 MX27_PAD_UART1_CTS__UART1_CTS 0x0
96 MX27_PAD_UART1_RTS__UART1_RTS 0x0
100 pinctrl_uart2: uart2grp {
102 MX27_PAD_UART2_TXD__UART2_TXD 0x0
103 MX27_PAD_UART2_RXD__UART2_RXD 0x0
104 MX27_PAD_UART2_CTS__UART2_CTS 0x0
105 MX27_PAD_UART2_RTS__UART2_RTS 0x0
109 pinctrl_uart3: uart3grp {
111 MX27_PAD_UART3_TXD__UART3_TXD 0x0
112 MX27_PAD_UART3_RXD__UART3_RXD 0x0
113 MX27_PAD_UART3_CTS__UART3_CTS 0x0
114 MX27_PAD_UART3_RTS__UART3_RTS 0x0
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_owire1>;
127 cd-gpios = <&gpio3 29 0>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_uart1>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_uart2>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart3>;