2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
16 model = "Freescale MX1 ADS";
17 compatible = "fsl,imx1ads", "fsl,imx1";
24 reg = <0x08000000 0x04000000>;
29 pinctrl-0 = <&pinctrl_cspi1>;
30 cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_i2c>;
39 extgpio0: pcf8575@22 {
40 compatible = "nxp,pcf8575";
46 extgpio1: pcf8575@24 {
47 compatible = "nxp,pcf8575";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_uart1>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_uart2>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_weim>;
74 compatible = "cfi-flash";
75 reg = <0 0x00000000 0x02000000>;
77 fsl,weim-cs-timing = <0x00003e00 0x00000801>;
85 pinctrl_cspi1: cspi1grp {
87 MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
88 MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
89 MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
90 MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
91 MX1_PAD_SPI1_SS__GPIO3_15 0x0
97 MX1_PAD_I2C_SCL__I2C_SCL 0x0
98 MX1_PAD_I2C_SDA__I2C_SDA 0x0
102 pinctrl_uart1: uart1grp {
104 MX1_PAD_UART1_TXD__UART1_TXD 0x0
105 MX1_PAD_UART1_RXD__UART1_RXD 0x0
106 MX1_PAD_UART1_CTS__UART1_CTS 0x0
107 MX1_PAD_UART1_RTS__UART1_RTS 0x0
111 pinctrl_uart2: uart2grp {
113 MX1_PAD_UART2_TXD__UART2_TXD 0x0
114 MX1_PAD_UART2_RXD__UART2_RXD 0x0
115 MX1_PAD_UART2_CTS__UART2_CTS 0x0
116 MX1_PAD_UART2_RTS__UART2_RTS 0x0
120 pinctrl_weim: weimgrp {
132 MX1_PAD_BCLK__BCLK 0x0
134 MX1_PAD_DTACK__DTACK 0x0