arch/arm/boot/dts/exynos5250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos5250 SoC device tree source
   4  *
   5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung Exynos5250 SoC device nodes are listed in this file.
   9  * Exynos5250 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
  14  * additional nodes can be added to this file.
  15  */
  16
  17 #include <dt-bindings/clock/exynos5250.h>
  18 #include "exynos5.dtsi"
  19 #include "exynos4-cpu-thermal.dtsi"
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5250", "samsung,exynos5";
  24
  25         aliases {
  26                 spi0 = &spi_0;
  27                 spi1 = &spi_1;
  28                 spi2 = &spi_2;
  29                 gsc0 = &gsc_0;
  30                 gsc1 = &gsc_1;
  31                 gsc2 = &gsc_2;
  32                 gsc3 = &gsc_3;
  33                 mshc0 = &mmc_0;
  34                 mshc1 = &mmc_1;
  35                 mshc2 = &mmc_2;
  36                 mshc3 = &mmc_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 i2c9 = &i2c_9;
  43                 pinctrl0 = &pinctrl_0;
  44                 pinctrl1 = &pinctrl_1;
  45                 pinctrl2 = &pinctrl_2;
  46                 pinctrl3 = &pinctrl_3;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu-map {
  54                         cluster0 {
  55                                 core0 {
  56                                         cpu = <&cpu0>;
  57                                 };
  58                                 core1 {
  59                                         cpu = <&cpu1>;
  60                                 };
  61                         };
  62                 };
  63
  64                 cpu0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <0>;
  68                         clocks = <&clock CLK_ARM_CLK>;
  69                         clock-names = "cpu";
  70                         operating-points-v2 = <&cpu0_opp_table>;
  71                         #cooling-cells = <2>; /* min followed by max */
  72                 };
  73                 cpu1: cpu@1 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a15";
  76                         reg = <1>;
  77                         clocks = <&clock CLK_ARM_CLK>;
  78                         clock-names = "cpu";
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         #cooling-cells = <2>; /* min followed by max */
  81                 };
  82         };
  83
  84         cpu0_opp_table: opp-table-0 {
  85                 compatible = "operating-points-v2";
  86                 opp-shared;
  87
  88                 opp-200000000 {
  89                         opp-hz = /bits/ 64 <200000000>;
  90                         opp-microvolt = <925000>;
  91                         clock-latency-ns = <140000>;
  92                 };
  93                 opp-300000000 {
  94                         opp-hz = /bits/ 64 <300000000>;
  95                         opp-microvolt = <937500>;
  96                         clock-latency-ns = <140000>;
  97                 };
  98                 opp-400000000 {
  99                         opp-hz = /bits/ 64 <400000000>;
 100                         opp-microvolt = <950000>;
 101                         clock-latency-ns = <140000>;
 102                 };
 103                 opp-500000000 {
 104                         opp-hz = /bits/ 64 <500000000>;
 105                         opp-microvolt = <975000>;
 106                         clock-latency-ns = <140000>;
 107                 };
 108                 opp-600000000 {
 109                         opp-hz = /bits/ 64 <600000000>;
 110                         opp-microvolt = <1000000>;
 111                         clock-latency-ns = <140000>;
 112                 };
 113                 opp-700000000 {
 114                         opp-hz = /bits/ 64 <700000000>;
 115                         opp-microvolt = <1012500>;
 116                         clock-latency-ns = <140000>;
 117                 };
 118                 opp-800000000 {
 119                         opp-hz = /bits/ 64 <800000000>;
 120                         opp-microvolt = <1025000>;
 121                         clock-latency-ns = <140000>;
 122                 };
 123                 opp-900000000 {
 124                         opp-hz = /bits/ 64 <900000000>;
 125                         opp-microvolt = <1050000>;
 126                         clock-latency-ns = <140000>;
 127                 };
 128                 opp-1000000000 {
 129                         opp-hz = /bits/ 64 <1000000000>;
 130                         opp-microvolt = <1075000>;
 131                         clock-latency-ns = <140000>;
 132                         opp-suspend;
 133                 };
 134                 opp-1100000000 {
 135                         opp-hz = /bits/ 64 <1100000000>;
 136                         opp-microvolt = <1100000>;
 137                         clock-latency-ns = <140000>;
 138                 };
 139                 opp-1200000000 {
 140                         opp-hz = /bits/ 64 <1200000000>;
 141                         opp-microvolt = <1125000>;
 142                         clock-latency-ns = <140000>;
 143                 };
 144                 opp-1300000000 {
 145                         opp-hz = /bits/ 64 <1300000000>;
 146                         opp-microvolt = <1150000>;
 147                         clock-latency-ns = <140000>;
 148                 };
 149                 opp-1400000000 {
 150                         opp-hz = /bits/ 64 <1400000000>;
 151                         opp-microvolt = <1200000>;
 152                         clock-latency-ns = <140000>;
 153                 };
 154                 opp-1500000000 {
 155                         opp-hz = /bits/ 64 <1500000000>;
 156                         opp-microvolt = <1225000>;
 157                         clock-latency-ns = <140000>;
 158                 };
 159                 opp-1600000000 {
 160                         opp-hz = /bits/ 64 <1600000000>;
 161                         opp-microvolt = <1250000>;
 162                         clock-latency-ns = <140000>;
 163                 };
 164                 opp-1700000000 {
 165                         opp-hz = /bits/ 64 <1700000000>;
 166                         opp-microvolt = <1300000>;
 167                         clock-latency-ns = <140000>;
 168                 };
 169         };
 170
 171         pmu {
 172                 compatible = "arm,cortex-a15-pmu";
 173                 interrupt-parent = <&combiner>;
 174                 interrupts = <1 2>, <22 4>;
 175         };
 176
 177         soc: soc {
 178                 sram@2020000 {
 179                         compatible = "mmio-sram";
 180                         reg = <0x02020000 0x30000>;
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183                         ranges = <0 0x02020000 0x30000>;
 184
 185                         smp-sram@0 {
 186                                 compatible = "samsung,exynos4210-sysram";
 187                                 reg = <0x0 0x1000>;
 188                         };
 189
 190                         smp-sram@2f000 {
 191                                 compatible = "samsung,exynos4210-sysram-ns";
 192                                 reg = <0x2f000 0x1000>;
 193                         };
 194                 };
 195
 196                 pd_gsc: power-domain@10044000 {
 197                         compatible = "samsung,exynos4210-pd";
 198                         reg = <0x10044000 0x20>;
 199                         #power-domain-cells = <0>;
 200                         label = "GSC";
 201                 };
 202
 203                 pd_mfc: power-domain@10044040 {
 204                         compatible = "samsung,exynos4210-pd";
 205                         reg = <0x10044040 0x20>;
 206                         #power-domain-cells = <0>;
 207                         label = "MFC";
 208                 };
 209
 210                 pd_g3d: power-domain@10044060 {
 211                         compatible = "samsung,exynos4210-pd";
 212                         reg = <0x10044060 0x20>;
 213                         #power-domain-cells = <0>;
 214                         label = "G3D";
 215                 };
 216
 217                 pd_disp1: power-domain@100440a0 {
 218                         compatible = "samsung,exynos4210-pd";
 219                         reg = <0x100440a0 0x20>;
 220                         #power-domain-cells = <0>;
 221                         label = "DISP1";
 222                 };
 223
 224                 pd_mau: power-domain@100440c0 {
 225                         compatible = "samsung,exynos4210-pd";
 226                         reg = <0x100440c0 0x20>;
 227                         #power-domain-cells = <0>;
 228                         label = "MAU";
 229                 };
 230
 231                 clock: clock-controller@10010000 {
 232                         compatible = "samsung,exynos5250-clock";
 233                         reg = <0x10010000 0x30000>;
 234                         #clock-cells = <1>;
 235                 };
 236
 237                 clock_audss: audss-clock-controller@3810000 {
 238                         compatible = "samsung,exynos5250-audss-clock";
 239                         reg = <0x03810000 0x0c>;
 240                         #clock-cells = <1>;
 241                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 242                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 243                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 244                         power-domains = <&pd_mau>;
 245                 };
 246
 247                 timer@101c0000 {
 248                         compatible = "samsung,exynos5250-mct",
 249                                      "samsung,exynos4210-mct";
 250                         reg = <0x101c0000 0x800>;
 251                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 252                         clock-names = "fin_pll", "mct";
 253                         interrupts-extended = <&combiner 23 3>,
 254                                               <&combiner 23 4>,
 255                                               <&combiner 25 2>,
 256                                               <&combiner 25 3>,
 257                                               <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 258                                               <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 259                 };
 260
 261                 pinctrl_0: pinctrl@11400000 {
 262                         compatible = "samsung,exynos5250-pinctrl";
 263                         reg = <0x11400000 0x1000>;
 264                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 265
 266                         wakup_eint: wakeup-interrupt-controller {
 267                                 compatible = "samsung,exynos4210-wakeup-eint";
 268                                 interrupt-parent = <&gic>;
 269                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 270                         };
 271                 };
 272
 273                 pinctrl_1: pinctrl@13400000 {
 274                         compatible = "samsung,exynos5250-pinctrl";
 275                         reg = <0x13400000 0x1000>;
 276                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 277                 };
 278
 279                 pinctrl_2: pinctrl@10d10000 {
 280                         compatible = "samsung,exynos5250-pinctrl";
 281                         reg = <0x10d10000 0x1000>;
 282                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 283                 };
 284
 285                 pinctrl_3: pinctrl@3860000 {
 286                         compatible = "samsung,exynos5250-pinctrl";
 287                         reg = <0x03860000 0x1000>;
 288                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 289                         power-domains = <&pd_mau>;
 290                 };
 291
 292                 pmu_system_controller: system-controller@10040000 {
 293                         compatible = "samsung,exynos5250-pmu", "syscon";
 294                         reg = <0x10040000 0x5000>;
 295                         clock-names = "clkout16";
 296                         clocks = <&clock CLK_FIN_PLL>;
 297                         #clock-cells = <1>;
 298                         interrupt-controller;
 299                         #interrupt-cells = <3>;
 300                         interrupt-parent = <&gic>;
 301                 };
 302
 303                 watchdog@101d0000 {
 304                         compatible = "samsung,exynos5250-wdt";
 305                         reg = <0x101d0000 0x100>;
 306                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&clock CLK_WDT>;
 308                         clock-names = "watchdog";
 309                         samsung,syscon-phandle = <&pmu_system_controller>;
 310                 };
 311
 312                 mfc: codec@11000000 {
 313                         compatible = "samsung,mfc-v6";
 314                         reg = <0x11000000 0x10000>;
 315                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 316                         power-domains = <&pd_mfc>;
 317                         clocks = <&clock CLK_MFC>;
 318                         clock-names = "mfc";
 319                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 320                         iommu-names = "left", "right";
 321                 };
 322
 323                 rotator: rotator@11c00000 {
 324                         compatible = "samsung,exynos5250-rotator";
 325                         reg = <0x11c00000 0x64>;
 326                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&clock CLK_ROTATOR>;
 328                         clock-names = "rotator";
 329                         iommus = <&sysmmu_rotator>;
 330                 };
 331
 332                 mali: gpu@11800000 {
 333                         compatible = "samsung,exynos5250-mali", "arm,mali-t604";
 334                         reg = <0x11800000 0x5000>;
 335                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 337                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 338                         interrupt-names = "job", "mmu", "gpu";
 339                         clocks = <&clock CLK_G3D>;
 340                         clock-names = "core";
 341                         operating-points-v2 = <&gpu_opp_table>;
 342                         power-domains = <&pd_g3d>;
 343                         status = "disabled";
 344
 345                         gpu_opp_table: opp-table {
 346                                 compatible = "operating-points-v2";
 347
 348                                 opp-100000000 {
 349                                         opp-hz = /bits/ 64 <100000000>;
 350                                         opp-microvolt = <925000>;
 351                                 };
 352                                 opp-160000000 {
 353                                         opp-hz = /bits/ 64 <160000000>;
 354                                         opp-microvolt = <925000>;
 355                                 };
 356                                 opp-266000000 {
 357                                         opp-hz = /bits/ 64 <266000000>;
 358                                         opp-microvolt = <1025000>;
 359                                 };
 360                                 opp-350000000 {
 361                                         opp-hz = /bits/ 64 <350000000>;
 362                                         opp-microvolt = <1075000>;
 363                                 };
 364                                 opp-400000000 {
 365                                         opp-hz = /bits/ 64 <400000000>;
 366                                         opp-microvolt = <1125000>;
 367                                 };
 368                                 opp-450000000 {
 369                                         opp-hz = /bits/ 64 <450000000>;
 370                                         opp-microvolt = <1150000>;
 371                                 };
 372                                 opp-533000000 {
 373                                         opp-hz = /bits/ 64 <533000000>;
 374                                         opp-microvolt = <1250000>;
 375                                 };
 376                         };
 377                 };
 378
 379                 tmu: tmu@10060000 {
 380                         compatible = "samsung,exynos5250-tmu";
 381                         reg = <0x10060000 0x100>;
 382                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&clock CLK_TMU>;
 384                         clock-names = "tmu_apbif";
 385                         #thermal-sensor-cells = <0>;
 386                 };
 387
 388                 sata: sata@122f0000 {
 389                         compatible = "snps,dwc-ahci";
 390                         reg = <0x122f0000 0x1ff>;
 391                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 392                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 393                         clock-names = "sata", "pclk";
 394                         phys = <&sata_phy>;
 395                         phy-names = "sata-phy";
 396                         ports-implemented = <0x1>;
 397                         status = "disabled";
 398                 };
 399
 400                 sata_phy: sata-phy@12170000 {
 401                         compatible = "samsung,exynos5250-sata-phy";
 402                         reg = <0x12170000 0x1ff>;
 403                         clocks = <&clock CLK_SATA_PHYCTRL>;
 404                         clock-names = "sata_phyctrl";
 405                         #phy-cells = <0>;
 406                         samsung,syscon-phandle = <&pmu_system_controller>;
 407                         status = "disabled";
 408                 };
 409
 410                 /* i2c_0-3 are defined in exynos5.dtsi */
 411                 i2c_4: i2c@12ca0000 {
 412                         compatible = "samsung,s3c2440-i2c";
 413                         reg = <0x12ca0000 0x100>;
 414                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         clocks = <&clock CLK_I2C4>;
 418                         clock-names = "i2c";
 419                         pinctrl-names = "default";
 420                         pinctrl-0 = <&i2c4_bus>;
 421                         status = "disabled";
 422                 };
 423
 424                 i2c_5: i2c@12cb0000 {
 425                         compatible = "samsung,s3c2440-i2c";
 426                         reg = <0x12cb0000 0x100>;
 427                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         clocks = <&clock CLK_I2C5>;
 431                         clock-names = "i2c";
 432                         pinctrl-names = "default";
 433                         pinctrl-0 = <&i2c5_bus>;
 434                         status = "disabled";
 435                 };
 436
 437                 i2c_6: i2c@12cc0000 {
 438                         compatible = "samsung,s3c2440-i2c";
 439                         reg = <0x12cc0000 0x100>;
 440                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         clocks = <&clock CLK_I2C6>;
 444                         clock-names = "i2c";
 445                         pinctrl-names = "default";
 446                         pinctrl-0 = <&i2c6_bus>;
 447                         status = "disabled";
 448                 };
 449
 450                 i2c_7: i2c@12cd0000 {
 451                         compatible = "samsung,s3c2440-i2c";
 452                         reg = <0x12cd0000 0x100>;
 453                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         clocks = <&clock CLK_I2C7>;
 457                         clock-names = "i2c";
 458                         pinctrl-names = "default";
 459                         pinctrl-0 = <&i2c7_bus>;
 460                         status = "disabled";
 461                 };
 462
 463                 i2c_8: i2c@12ce0000 {
 464                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 465                         reg = <0x12ce0000 0x1000>;
 466                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         clocks = <&clock CLK_I2C_HDMI>;
 470                         clock-names = "i2c";
 471                         status = "disabled";
 472
 473                         hdmiphy: hdmi-phy@38 {
 474                                 compatible = "samsung,exynos4212-hdmiphy";
 475                                 reg = <0x38>;
 476                         };
 477                 };
 478
 479                 i2c_9: i2c@121d0000 {
 480                         compatible = "samsung,exynos5-sata-phy-i2c";
 481                         reg = <0x121d0000 0x100>;
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         clocks = <&clock CLK_SATA_PHYI2C>;
 485                         clock-names = "i2c";
 486                         status = "disabled";
 487
 488                         sata_phy_i2c: sata-phy-i2c@38 {
 489                                 compatible = "samsung,exynos-sataphy-i2c";
 490                                 reg = <0x38>;
 491                                 status = "disabled";
 492                         };
 493                 };
 494
 495                 spi_0: spi@12d20000 {
 496                         compatible = "samsung,exynos4210-spi";
 497                         status = "disabled";
 498                         reg = <0x12d20000 0x100>;
 499                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 500                         dmas = <&pdma0 5>, <&pdma0 4>;
 501                         dma-names = "tx", "rx";
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 505                         clock-names = "spi", "spi_busclk0";
 506                         pinctrl-names = "default";
 507                         pinctrl-0 = <&spi0_bus>;
 508                 };
 509
 510                 spi_1: spi@12d30000 {
 511                         compatible = "samsung,exynos4210-spi";
 512                         status = "disabled";
 513                         reg = <0x12d30000 0x100>;
 514                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 515                         dmas = <&pdma1 5>, <&pdma1 4>;
 516                         dma-names = "tx", "rx";
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 520                         clock-names = "spi", "spi_busclk0";
 521                         pinctrl-names = "default";
 522                         pinctrl-0 = <&spi1_bus>;
 523                 };
 524
 525                 spi_2: spi@12d40000 {
 526                         compatible = "samsung,exynos4210-spi";
 527                         status = "disabled";
 528                         reg = <0x12d40000 0x100>;
 529                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 530                         dmas = <&pdma0 7>, <&pdma0 6>;
 531                         dma-names = "tx", "rx";
 532                         #address-cells = <1>;
 533                         #size-cells = <0>;
 534                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 535                         clock-names = "spi", "spi_busclk0";
 536                         pinctrl-names = "default";
 537                         pinctrl-0 = <&spi2_bus>;
 538                 };
 539
 540                 mmc_0: mmc@12200000 {
 541                         compatible = "samsung,exynos5250-dw-mshc";
 542                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         reg = <0x12200000 0x1000>;
 546                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 547                         clock-names = "biu", "ciu";
 548                         fifo-depth = <0x80>;
 549                         status = "disabled";
 550                 };
 551
 552                 mmc_1: mmc@12210000 {
 553                         compatible = "samsung,exynos5250-dw-mshc";
 554                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         reg = <0x12210000 0x1000>;
 558                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 559                         clock-names = "biu", "ciu";
 560                         fifo-depth = <0x80>;
 561                         status = "disabled";
 562                 };
 563
 564                 mmc_2: mmc@12220000 {
 565                         compatible = "samsung,exynos5250-dw-mshc";
 566                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         reg = <0x12220000 0x1000>;
 570                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 571                         clock-names = "biu", "ciu";
 572                         fifo-depth = <0x80>;
 573                         status = "disabled";
 574                 };
 575
 576                 mmc_3: mmc@12230000 {
 577                         compatible = "samsung,exynos5250-dw-mshc";
 578                         reg = <0x12230000 0x1000>;
 579                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 583                         clock-names = "biu", "ciu";
 584                         fifo-depth = <0x80>;
 585                         status = "disabled";
 586                 };
 587
 588                 i2s0: i2s@3830000 {
 589                         compatible = "samsung,s5pv210-i2s";
 590                         status = "disabled";
 591                         reg = <0x03830000 0x100>;
 592                         dmas = <&pdma0 10>,
 593                                 <&pdma0 9>,
 594                                 <&pdma0 8>;
 595                         dma-names = "tx", "rx", "tx-sec";
 596                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 597                                 <&clock_audss EXYNOS_I2S_BUS>,
 598                                 <&clock_audss EXYNOS_SCLK_I2S>;
 599                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 600                         samsung,idma-addr = <0x03000000>;
 601                         pinctrl-names = "default";
 602                         pinctrl-0 = <&i2s0_bus>;
 603                         power-domains = <&pd_mau>;
 604                         #clock-cells = <1>;
 605                         #sound-dai-cells = <1>;
 606                 };
 607
 608                 i2s1: i2s@12d60000 {
 609                         compatible = "samsung,s3c6410-i2s";
 610                         status = "disabled";
 611                         reg = <0x12d60000 0x100>;
 612                         dmas = <&pdma1 12>,
 613                                 <&pdma1 11>;
 614                         dma-names = "tx", "rx";
 615                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 616                         clock-names = "iis", "i2s_opclk0";
 617                         pinctrl-names = "default";
 618                         pinctrl-0 = <&i2s1_bus>;
 619                         power-domains = <&pd_mau>;
 620                         #sound-dai-cells = <1>;
 621                 };
 622
 623                 i2s2: i2s@12d70000 {
 624                         compatible = "samsung,s3c6410-i2s";
 625                         status = "disabled";
 626                         reg = <0x12d70000 0x100>;
 627                         dmas = <&pdma0 12>,
 628                                 <&pdma0 11>;
 629                         dma-names = "tx", "rx";
 630                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 631                         clock-names = "iis", "i2s_opclk0";
 632                         pinctrl-names = "default";
 633                         pinctrl-0 = <&i2s2_bus>;
 634                         power-domains = <&pd_mau>;
 635                         #sound-dai-cells = <1>;
 636                 };
 637
 638                 usbdrd: usb@12000000 {
 639                         compatible = "samsung,exynos5250-dwusb3";
 640                         clocks = <&clock CLK_USB3>;
 641                         clock-names = "usbdrd30";
 642                         #address-cells = <1>;
 643                         #size-cells = <1>;
 644                         ranges = <0x0 0x12000000 0x10000>;
 645
 646                         usbdrd_dwc3: usb@0 {
 647                                 compatible = "snps,dwc3";
 648                                 reg = <0x0 0x10000>;
 649                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 650                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 651                                 phy-names = "usb2-phy", "usb3-phy";
 652                         };
 653                 };
 654
 655                 usbdrd_phy: phy@12100000 {
 656                         compatible = "samsung,exynos5250-usbdrd-phy";
 657                         reg = <0x12100000 0x100>;
 658                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 659                         clock-names = "phy", "ref";
 660                         samsung,pmu-syscon = <&pmu_system_controller>;
 661                         #phy-cells = <1>;
 662                 };
 663
 664                 ehci: usb@12110000 {
 665                         compatible = "samsung,exynos4210-ehci";
 666                         reg = <0x12110000 0x100>;
 667                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 668
 669                         clocks = <&clock CLK_USB2>;
 670                         clock-names = "usbhost";
 671                         phys = <&usb2_phy_gen 1>;
 672                         phy-names = "host";
 673                 };
 674
 675                 ohci: usb@12120000 {
 676                         compatible = "samsung,exynos4210-ohci";
 677                         reg = <0x12120000 0x100>;
 678                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 679
 680                         clocks = <&clock CLK_USB2>;
 681                         clock-names = "usbhost";
 682                         phys = <&usb2_phy_gen 1>;
 683                         phy-names = "host";
 684                 };
 685
 686                 usb2_phy_gen: phy@12130000 {
 687                         compatible = "samsung,exynos5250-usb2-phy";
 688                         reg = <0x12130000 0x100>;
 689                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 690                         clock-names = "phy", "ref";
 691                         #phy-cells = <1>;
 692                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 693                         samsung,pmureg-phandle = <&pmu_system_controller>;
 694                 };
 695
 696                 pdma0: dma-controller@121a0000 {
 697                         compatible = "arm,pl330", "arm,primecell";
 698                         reg = <0x121a0000 0x1000>;
 699                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 700                         clocks = <&clock CLK_PDMA0>;
 701                         clock-names = "apb_pclk";
 702                         #dma-cells = <1>;
 703                 };
 704
 705                 pdma1: dma-controller@121b0000 {
 706                         compatible = "arm,pl330", "arm,primecell";
 707                         reg = <0x121b0000 0x1000>;
 708                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&clock CLK_PDMA1>;
 710                         clock-names = "apb_pclk";
 711                         #dma-cells = <1>;
 712                 };
 713
 714                 mdma0: dma-controller@10800000 {
 715                         compatible = "arm,pl330", "arm,primecell";
 716                         reg = <0x10800000 0x1000>;
 717                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 718                         clocks = <&clock CLK_MDMA0>;
 719                         clock-names = "apb_pclk";
 720                         #dma-cells = <1>;
 721                 };
 722
 723                 mdma1: dma-controller@11c10000 {
 724                         compatible = "arm,pl330", "arm,primecell";
 725                         reg = <0x11c10000 0x1000>;
 726                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 727                         clocks = <&clock CLK_MDMA1>;
 728                         clock-names = "apb_pclk";
 729                         #dma-cells = <1>;
 730                 };
 731
 732                 gsc_0: gsc@13e00000 {
 733                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 734                         reg = <0x13e00000 0x1000>;
 735                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 736                         power-domains = <&pd_gsc>;
 737                         clocks = <&clock CLK_GSCL0>;
 738                         clock-names = "gscl";
 739                         iommus = <&sysmmu_gsc0>;
 740                 };
 741
 742                 gsc_1: gsc@13e10000 {
 743                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 744                         reg = <0x13e10000 0x1000>;
 745                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 746                         power-domains = <&pd_gsc>;
 747                         clocks = <&clock CLK_GSCL1>;
 748                         clock-names = "gscl";
 749                         iommus = <&sysmmu_gsc1>;
 750                 };
 751
 752                 gsc_2: gsc@13e20000 {
 753                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 754                         reg = <0x13e20000 0x1000>;
 755                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 756                         power-domains = <&pd_gsc>;
 757                         clocks = <&clock CLK_GSCL2>;
 758                         clock-names = "gscl";
 759                         iommus = <&sysmmu_gsc2>;
 760                 };
 761
 762                 gsc_3: gsc@13e30000 {
 763                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 764                         reg = <0x13e30000 0x1000>;
 765                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 766                         power-domains = <&pd_gsc>;
 767                         clocks = <&clock CLK_GSCL3>;
 768                         clock-names = "gscl";
 769                         iommus = <&sysmmu_gsc3>;
 770                 };
 771
 772                 hdmi: hdmi@14530000 {
 773                         compatible = "samsung,exynos4212-hdmi";
 774                         reg = <0x14530000 0x70000>;
 775                         power-domains = <&pd_disp1>;
 776                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 777                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 778                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 779                                  <&clock CLK_MOUT_HDMI>;
 780                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 781                                         "sclk_hdmiphy", "mout_hdmi";
 782                         samsung,syscon-phandle = <&pmu_system_controller>;
 783                         phy = <&hdmiphy>;
 784                         #sound-dai-cells = <0>;
 785                         status = "disabled";
 786                 };
 787
 788                 hdmicec: cec@101b0000 {
 789                         compatible = "samsung,s5p-cec";
 790                         reg = <0x101b0000 0x200>;
 791                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 792                         clocks = <&clock CLK_HDMI_CEC>;
 793                         clock-names = "hdmicec";
 794                         samsung,syscon-phandle = <&pmu_system_controller>;
 795                         hdmi-phandle = <&hdmi>;
 796                         pinctrl-names = "default";
 797                         pinctrl-0 = <&hdmi_cec>;
 798                         status = "disabled";
 799                 };
 800
 801                 mixer: mixer@14450000 {
 802                         compatible = "samsung,exynos5250-mixer";
 803                         reg = <0x14450000 0x10000>;
 804                         power-domains = <&pd_disp1>;
 805                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 806                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 807                                  <&clock CLK_SCLK_HDMI>;
 808                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 809                         iommus = <&sysmmu_tv>;
 810                         status = "disabled";
 811                 };
 812
 813                 dp_phy: video-phy-0 {
 814                         compatible = "samsung,exynos5250-dp-video-phy";
 815                         samsung,pmu-syscon = <&pmu_system_controller>;
 816                         #phy-cells = <0>;
 817                 };
 818
 819                 mipi_phy: video-phy-1 {
 820                         compatible = "samsung,s5pv210-mipi-video-phy";
 821                         #phy-cells = <1>;
 822                         syscon = <&pmu_system_controller>;
 823                 };
 824
 825                 dsi_0: dsi@14500000 {
 826                         compatible = "samsung,exynos4210-mipi-dsi";
 827                         reg = <0x14500000 0x10000>;
 828                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 829                         samsung,power-domain = <&pd_disp1>;
 830                         phys = <&mipi_phy 3>;
 831                         phy-names = "dsim";
 832                         clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
 833                         clock-names = "bus_clk", "sclk_mipi";
 834                         status = "disabled";
 835                         #address-cells = <1>;
 836                         #size-cells = <0>;
 837                 };
 838
 839                 adc: adc@12d10000 {
 840                         compatible = "samsung,exynos-adc-v1";
 841                         reg = <0x12d10000 0x100>;
 842                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 843                         clocks = <&clock CLK_ADC>;
 844                         clock-names = "adc";
 845                         #io-channel-cells = <1>;
 846                         samsung,syscon-phandle = <&pmu_system_controller>;
 847                         status = "disabled";
 848                 };
 849
 850                 sysmmu_g2d: sysmmu@10a60000 {
 851                         compatible = "samsung,exynos-sysmmu";
 852                         reg = <0x10a60000 0x1000>;
 853                         interrupt-parent = <&combiner>;
 854                         interrupts = <24 5>;
 855                         clock-names = "sysmmu", "master";
 856                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 857                         #iommu-cells = <0>;
 858                 };
 859
 860                 sysmmu_mfc_r: sysmmu@11200000 {
 861                         compatible = "samsung,exynos-sysmmu";
 862                         reg = <0x11200000 0x1000>;
 863                         interrupt-parent = <&combiner>;
 864                         interrupts = <6 2>;
 865                         power-domains = <&pd_mfc>;
 866                         clock-names = "sysmmu", "master";
 867                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 868                         #iommu-cells = <0>;
 869                 };
 870
 871                 sysmmu_mfc_l: sysmmu@11210000 {
 872                         compatible = "samsung,exynos-sysmmu";
 873                         reg = <0x11210000 0x1000>;
 874                         interrupt-parent = <&combiner>;
 875                         interrupts = <8 5>;
 876                         power-domains = <&pd_mfc>;
 877                         clock-names = "sysmmu", "master";
 878                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 879                         #iommu-cells = <0>;
 880                 };
 881
 882                 sysmmu_rotator: sysmmu@11d40000 {
 883                         compatible = "samsung,exynos-sysmmu";
 884                         reg = <0x11d40000 0x1000>;
 885                         interrupt-parent = <&combiner>;
 886                         interrupts = <4 0>;
 887                         clock-names = "sysmmu", "master";
 888                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 889                         #iommu-cells = <0>;
 890                 };
 891
 892                 sysmmu_jpeg: sysmmu@11f20000 {
 893                         compatible = "samsung,exynos-sysmmu";
 894                         reg = <0x11f20000 0x1000>;
 895                         interrupt-parent = <&combiner>;
 896                         interrupts = <4 2>;
 897                         power-domains = <&pd_gsc>;
 898                         clock-names = "sysmmu", "master";
 899                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 900                         #iommu-cells = <0>;
 901                 };
 902
 903                 sysmmu_fimc_isp: sysmmu@13260000 {
 904                         compatible = "samsung,exynos-sysmmu";
 905                         reg = <0x13260000 0x1000>;
 906                         interrupt-parent = <&combiner>;
 907                         interrupts = <10 6>;
 908                         clock-names = "sysmmu";
 909                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
 910                         #iommu-cells = <0>;
 911                 };
 912
 913                 sysmmu_fimc_drc: sysmmu@13270000 {
 914                         compatible = "samsung,exynos-sysmmu";
 915                         reg = <0x13270000 0x1000>;
 916                         interrupt-parent = <&combiner>;
 917                         interrupts = <11 6>;
 918                         clock-names = "sysmmu";
 919                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
 920                         #iommu-cells = <0>;
 921                 };
 922
 923                 sysmmu_fimc_fd: sysmmu@132a0000 {
 924                         compatible = "samsung,exynos-sysmmu";
 925                         reg = <0x132a0000 0x1000>;
 926                         interrupt-parent = <&combiner>;
 927                         interrupts = <5 0>;
 928                         clock-names = "sysmmu";
 929                         clocks = <&clock CLK_SMMU_FIMC_FD>;
 930                         #iommu-cells = <0>;
 931                 };
 932
 933                 sysmmu_fimc_scc: sysmmu@13280000 {
 934                         compatible = "samsung,exynos-sysmmu";
 935                         reg = <0x13280000 0x1000>;
 936                         interrupt-parent = <&combiner>;
 937                         interrupts = <5 2>;
 938                         clock-names = "sysmmu";
 939                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
 940                         #iommu-cells = <0>;
 941                 };
 942
 943                 sysmmu_fimc_scp: sysmmu@13290000 {
 944                         compatible = "samsung,exynos-sysmmu";
 945                         reg = <0x13290000 0x1000>;
 946                         interrupt-parent = <&combiner>;
 947                         interrupts = <3 6>;
 948                         clock-names = "sysmmu";
 949                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
 950                         #iommu-cells = <0>;
 951                 };
 952
 953                 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
 954                         compatible = "samsung,exynos-sysmmu";
 955                         reg = <0x132b0000 0x1000>;
 956                         interrupt-parent = <&combiner>;
 957                         interrupts = <5 4>;
 958                         clock-names = "sysmmu";
 959                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
 960                         #iommu-cells = <0>;
 961                 };
 962
 963                 sysmmu_fimc_odc: sysmmu@132c0000 {
 964                         compatible = "samsung,exynos-sysmmu";
 965                         reg = <0x132c0000 0x1000>;
 966                         interrupt-parent = <&combiner>;
 967                         interrupts = <11 0>;
 968                         clock-names = "sysmmu";
 969                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
 970                         #iommu-cells = <0>;
 971                 };
 972
 973                 sysmmu_fimc_dis0: sysmmu@132d0000 {
 974                         compatible = "samsung,exynos-sysmmu";
 975                         reg = <0x132d0000 0x1000>;
 976                         interrupt-parent = <&combiner>;
 977                         interrupts = <10 4>;
 978                         clock-names = "sysmmu";
 979                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 980                         #iommu-cells = <0>;
 981                 };
 982
 983                 sysmmu_fimc_dis1: sysmmu@132e0000 {
 984                         compatible = "samsung,exynos-sysmmu";
 985                         reg = <0x132e0000 0x1000>;
 986                         interrupt-parent = <&combiner>;
 987                         interrupts = <9 4>;
 988                         clock-names = "sysmmu";
 989                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 990                         #iommu-cells = <0>;
 991                 };
 992
 993                 sysmmu_fimc_3dnr: sysmmu@132f0000 {
 994                         compatible = "samsung,exynos-sysmmu";
 995                         reg = <0x132f0000 0x1000>;
 996                         interrupt-parent = <&combiner>;
 997                         interrupts = <5 6>;
 998                         clock-names = "sysmmu";
 999                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
1000                         #iommu-cells = <0>;
1001                 };
1002
1003                 sysmmu_fimc_lite0: sysmmu@13c40000 {
1004                         compatible = "samsung,exynos-sysmmu";
1005                         reg = <0x13c40000 0x1000>;
1006                         interrupt-parent = <&combiner>;
1007                         interrupts = <3 4>;
1008                         power-domains = <&pd_gsc>;
1009                         clock-names = "sysmmu", "master";
1010                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1011                         #iommu-cells = <0>;
1012                 };
1013
1014                 sysmmu_fimc_lite1: sysmmu@13c50000 {
1015                         compatible = "samsung,exynos-sysmmu";
1016                         reg = <0x13c50000 0x1000>;
1017                         interrupt-parent = <&combiner>;
1018                         interrupts = <24 1>;
1019                         power-domains = <&pd_gsc>;
1020                         clock-names = "sysmmu", "master";
1021                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1022                         #iommu-cells = <0>;
1023                 };
1024
1025                 sysmmu_gsc0: sysmmu@13e80000 {
1026                         compatible = "samsung,exynos-sysmmu";
1027                         reg = <0x13e80000 0x1000>;
1028                         interrupt-parent = <&combiner>;
1029                         interrupts = <2 0>;
1030                         power-domains = <&pd_gsc>;
1031                         clock-names = "sysmmu", "master";
1032                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1033                         #iommu-cells = <0>;
1034                 };
1035
1036                 sysmmu_gsc1: sysmmu@13e90000 {
1037                         compatible = "samsung,exynos-sysmmu";
1038                         reg = <0x13e90000 0x1000>;
1039                         interrupt-parent = <&combiner>;
1040                         interrupts = <2 2>;
1041                         power-domains = <&pd_gsc>;
1042                         clock-names = "sysmmu", "master";
1043                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1044                         #iommu-cells = <0>;
1045                 };
1046
1047                 sysmmu_gsc2: sysmmu@13ea0000 {
1048                         compatible = "samsung,exynos-sysmmu";
1049                         reg = <0x13ea0000 0x1000>;
1050                         interrupt-parent = <&combiner>;
1051                         interrupts = <2 4>;
1052                         power-domains = <&pd_gsc>;
1053                         clock-names = "sysmmu", "master";
1054                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1055                         #iommu-cells = <0>;
1056                 };
1057
1058                 sysmmu_gsc3: sysmmu@13eb0000 {
1059                         compatible = "samsung,exynos-sysmmu";
1060                         reg = <0x13eb0000 0x1000>;
1061                         interrupt-parent = <&combiner>;
1062                         interrupts = <2 6>;
1063                         power-domains = <&pd_gsc>;
1064                         clock-names = "sysmmu", "master";
1065                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1066                         #iommu-cells = <0>;
1067                 };
1068
1069                 sysmmu_fimd1: sysmmu@14640000 {
1070                         compatible = "samsung,exynos-sysmmu";
1071                         reg = <0x14640000 0x1000>;
1072                         interrupt-parent = <&combiner>;
1073                         interrupts = <3 2>;
1074                         power-domains = <&pd_disp1>;
1075                         clock-names = "sysmmu", "master";
1076                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1077                         #iommu-cells = <0>;
1078                 };
1079
1080                 sysmmu_tv: sysmmu@14650000 {
1081                         compatible = "samsung,exynos-sysmmu";
1082                         reg = <0x14650000 0x1000>;
1083                         interrupt-parent = <&combiner>;
1084                         interrupts = <7 4>;
1085                         power-domains = <&pd_disp1>;
1086                         clock-names = "sysmmu", "master";
1087                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1088                         #iommu-cells = <0>;
1089                 };
1090         };
1091
1092         timer {
1093                 compatible = "arm,armv7-timer";
1094                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1095                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1096                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1097                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1098                 /*
1099                  * Unfortunately we need this since some versions
1100                  * of U-Boot on Exynos don't set the CNTFRQ register,
1101                  * so we need the value from DT.
1102                  */
1103                 clock-frequency = <24000000>;
1104         };
1105 };
1106
1107 &cpu_thermal {
1108         polling-delay-passive = <0>;
1109         polling-delay = <0>;
1110         thermal-sensors = <&tmu>;
1111
1112         cooling-maps {
1113                 map0 {
1114                         /* Corresponds to 800MHz at freq_table */
1115                         cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1116                 };
1117                 map1 {
1118                         /* Corresponds to 200MHz at freq_table */
1119                         cooling-device = <&cpu0 15 15>,
1120                                          <&cpu1 15 15>;
1121                 };
1122         };
1123 };
1124
1125 &dp {
1126         power-domains = <&pd_disp1>;
1127         clocks = <&clock CLK_DP>;
1128         clock-names = "dp";
1129         phys = <&dp_phy>;
1130         phy-names = "dp";
1131 };
1132
1133 &fimd {
1134         power-domains = <&pd_disp1>;
1135         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1136         clock-names = "sclk_fimd", "fimd";
1137         iommus = <&sysmmu_fimd1>;
1138 };
1139
1140 &g2d {
1141         iommus = <&sysmmu_g2d>;
1142         clocks = <&clock CLK_G2D>;
1143         clock-names = "fimg2d";
1144         status = "okay";
1145 };
1146
1147 &i2c_0 {
1148         clocks = <&clock CLK_I2C0>;
1149         clock-names = "i2c";
1150         pinctrl-names = "default";
1151         pinctrl-0 = <&i2c0_bus>;
1152 };
1153
1154 &i2c_1 {
1155         clocks = <&clock CLK_I2C1>;
1156         clock-names = "i2c";
1157         pinctrl-names = "default";
1158         pinctrl-0 = <&i2c1_bus>;
1159 };
1160
1161 &i2c_2 {
1162         clocks = <&clock CLK_I2C2>;
1163         clock-names = "i2c";
1164         pinctrl-names = "default";
1165         pinctrl-0 = <&i2c2_bus>;
1166 };
1167
1168 &i2c_3 {
1169         clocks = <&clock CLK_I2C3>;
1170         clock-names = "i2c";
1171         pinctrl-names = "default";
1172         pinctrl-0 = <&i2c3_bus>;
1173 };
1174
1175 &prng {
1176         clocks = <&clock CLK_SSS>;
1177         clock-names = "secss";
1178 };
1179
1180 &pwm {
1181         clocks = <&clock CLK_PWM>;
1182         clock-names = "timers";
1183 };
1184
1185 &rtc {
1186         clocks = <&clock CLK_RTC>;
1187         clock-names = "rtc";
1188         interrupt-parent = <&pmu_system_controller>;
1189         status = "disabled";
1190 };
1191
1192 &serial_0 {
1193         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1194         clock-names = "uart", "clk_uart_baud0";
1195         dmas = <&pdma0 13>, <&pdma0 14>;
1196         dma-names = "rx", "tx";
1197 };
1198
1199 &serial_1 {
1200         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1201         clock-names = "uart", "clk_uart_baud0";
1202         dmas = <&pdma1 15>, <&pdma1 16>;
1203         dma-names = "rx", "tx";
1204 };
1205
1206 &serial_2 {
1207         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1208         clock-names = "uart", "clk_uart_baud0";
1209         dmas = <&pdma0 15>, <&pdma0 16>;
1210         dma-names = "rx", "tx";
1211 };
1212
1213 &serial_3 {
1214         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1215         clock-names = "uart", "clk_uart_baud0";
1216         dmas = <&pdma1 17>, <&pdma1 18>;
1217         dma-names = "rx", "tx";
1218 };
1219
1220 &sss {
1221         clocks = <&clock CLK_SSS>;
1222         clock-names = "secss";
1223 };
1224
1225 &trng {
1226         clocks = <&clock CLK_SSS>;
1227         clock-names = "secss";
1228 };
1229
1230 #include "exynos5250-pinctrl.dtsi"
1231 #include "exynos-syscon-restart.dtsi"