arch/arm/boot/dts/dra72-evm-revc.dts

   1 /*
   2  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include "dra72-evm-common.dtsi"
   9 #include <dt-bindings/net/ti-dp83867.h>
  10
  11 / {
  12         model = "TI DRA722 Rev C EVM";
  13
  14         memory@0 {
  15                 device_type = "memory";
  16                 reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
  17         };
  18
  19         evm_1v8_sw: fixedregulator-evm_1v8 {
  20                 compatible = "regulator-fixed";
  21                 regulator-name = "evm_1v8";
  22                 regulator-min-microvolt = <1800000>;
  23                 regulator-max-microvolt = <1800000>;
  24                 vin-supply = <&smps4_reg>;
  25                 regulator-always-on;
  26                 regulator-boot-on;
  27         };
  28 };
  29
  30 &i2c1 {
  31         tps65917: tps65917@58 {
  32                 reg = <0x58>;
  33
  34                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
  35         };
  36 };
  37
  38 #include "dra72-evm-tps65917.dtsi"
  39
  40 &ldo2_reg {
  41         /* LDO2_OUT --> VDDA_1V8_PHY2 */
  42         regulator-always-on;
  43         regulator-boot-on;
  44 };
  45
  46 &hdmi {
  47         vdda-supply = <&ldo2_reg>;
  48 };
  49
  50 &pcf_gpio_21 {
  51         interrupt-parent = <&gpio3>;
  52         interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
  53 };
  54
  55 &mac {
  56         mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
  57                      <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,     /* P11 */
  58                      <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;    /* P12 */
  59         dual_emac;
  60 };
  61
  62 &cpsw_emac0 {
  63         phy_id = <&davinci_mdio>, <2>;
  64         phy-mode = "rgmii-id";
  65         dual_emac_res_vlan = <1>;
  66 };
  67
  68 &cpsw_emac1 {
  69         phy_id = <&davinci_mdio>, <3>;
  70         phy-mode = "rgmii-id";
  71         dual_emac_res_vlan = <2>;
  72 };
  73
  74 &davinci_mdio {
  75         dp83867_0: ethernet-phy@2 {
  76                 reg = <2>;
  77                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  78                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
  79                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
  80                 ti,min-output-impedance;
  81                 interrupt-parent = <&gpio6>;
  82                 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
  83         };
  84
  85         dp83867_1: ethernet-phy@3 {
  86                 reg = <3>;
  87                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  88                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
  89                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
  90                 ti,min-output-impedance;
  91                 interrupt-parent = <&gpio6>;
  92                 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
  93         };
  94 };
  95
  96 &mmc1 {
  97         vqmmc-supply = <&ldo1_reg>;
  98 };
  99
 100 &mmc2 {
 101         vmmc-supply = <&evm_1v8_sw>;
 102 };