1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on "omap4.dtsi"
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
14 #define MAX_SOURCES 400
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
59 #interrupt-cells = <3>;
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 #interrupt-cells = <3>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
73 interrupt-parent = <&gic>;
82 compatible = "arm,cortex-a15";
85 operating-points-v2 = <&cpu0_opp_table>;
87 clocks = <&dpll_mpu_ck>;
90 clock-latency = <300000>; /* From omap-cpufreq driver */
93 #cooling-cells = <2>; /* min followed by max */
95 vbb-supply = <&abb_mpu>;
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
101 syscon = <&scm_wkup>;
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>,
106 <1060000 850000 1150000>;
107 opp-supported-hw = <0xFF 0x01>;
112 opp-hz = /bits/ 64 <1176000000>;
113 opp-microvolt = <1160000 885000 1160000>,
114 <1160000 885000 1160000>;
116 opp-supported-hw = <0xFF 0x02>;
119 opp_high@1500000000 {
120 opp-hz = /bits/ 64 <1500000000>;
121 opp-microvolt = <1210000 950000 1250000>,
122 <1210000 950000 1250000>;
123 opp-supported-hw = <0xFF 0x04>;
128 * The soc node represents the soc top level view. It is used for IPs
129 * that are not memory mapped in the MPU view or for the MPU itself.
132 compatible = "ti,omap-infra";
134 compatible = "ti,omap5-mpu";
140 * XXX: Use a flat representation of the SOC interconnect.
141 * The real OMAP interconnect network is quite complex.
142 * Since it will not bring real advantage to represent that in DT for
143 * the moment, just use a fake OCP bus entry to represent the whole bus
147 compatible = "ti,dra7-l3-noc", "simple-bus";
148 #address-cells = <1>;
150 ranges = <0x0 0x0 0x0 0xc0000000>;
151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
152 ti,hwmods = "l3_main_1", "l3_main_2";
153 reg = <0x0 0x44000000 0x0 0x1000000>,
154 <0x0 0x45000000 0x0 0x1000>;
155 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
156 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
158 l4_cfg: interconnect@4a000000 {
160 l4_wkup: interconnect@4ae00000 {
162 l4_per1: interconnect@48000000 {
164 l4_per2: interconnect@48400000 {
166 l4_per3: interconnect@48800000 {
170 compatible = "simple-bus";
172 #address-cells = <1>;
173 ranges = <0x51000000 0x51000000 0x3000
174 0x0 0x20000000 0x10000000>;
176 * To enable PCI endpoint mode, disable the pcie1_rc
177 * node and enable pcie1_ep mode.
179 pcie1_rc: pcie@51000000 {
180 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
181 reg-names = "rc_dbics", "ti_conf", "config";
182 interrupts = <0 232 0x4>, <0 233 0x4>;
183 #address-cells = <3>;
186 ranges = <0x81000000 0 0 0x03000 0 0x00010000
187 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
188 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
189 bus-range = <0x00 0xff>;
190 #interrupt-cells = <1>;
192 linux,pci-domain = <0>;
195 phy-names = "pcie-phy0";
196 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
197 interrupt-map-mask = <0 0 0 7>;
198 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
199 <0 0 0 2 &pcie1_intc 2>,
200 <0 0 0 3 &pcie1_intc 3>,
201 <0 0 0 4 &pcie1_intc 4>;
202 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
204 pcie1_intc: interrupt-controller {
205 interrupt-controller;
206 #address-cells = <0>;
207 #interrupt-cells = <1>;
211 pcie1_ep: pcie_ep@51000000 {
212 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
213 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
214 interrupts = <0 232 0x4>;
216 num-ib-windows = <4>;
217 num-ob-windows = <16>;
220 phy-names = "pcie-phy0";
221 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
228 compatible = "simple-bus";
230 #address-cells = <1>;
231 ranges = <0x51800000 0x51800000 0x3000
232 0x0 0x30000000 0x10000000>;
234 pcie2_rc: pcie@51800000 {
235 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
236 reg-names = "rc_dbics", "ti_conf", "config";
237 interrupts = <0 355 0x4>, <0 356 0x4>;
238 #address-cells = <3>;
241 ranges = <0x81000000 0 0 0x03000 0 0x00010000
242 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
243 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
244 bus-range = <0x00 0xff>;
245 #interrupt-cells = <1>;
247 linux,pci-domain = <1>;
250 phy-names = "pcie-phy0";
251 interrupt-map-mask = <0 0 0 7>;
252 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
253 <0 0 0 2 &pcie2_intc 2>,
254 <0 0 0 3 &pcie2_intc 3>,
255 <0 0 0 4 &pcie2_intc 4>;
256 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
257 pcie2_intc: interrupt-controller {
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <1>;
265 ocmcram1: ocmcram@40300000 {
266 compatible = "mmio-sram";
267 reg = <0x40300000 0x80000>;
268 ranges = <0x0 0x40300000 0x80000>;
269 #address-cells = <1>;
272 * This is a placeholder for an optional reserved
273 * region for use by secure software. The size
274 * of this region is not known until runtime so it
275 * is set as zero to either be updated to reserve
276 * space or left unchanged to leave all SRAM for use.
277 * On HS parts that that require the reserved region
278 * either the bootloader can update the size to
279 * the required amount or the node can be overridden
280 * from the board dts file for the secure platform.
283 compatible = "ti,secure-ram";
289 * NOTE: ocmcram2 and ocmcram3 are not available on all
290 * DRA7xx and AM57xx variants. Confirm availability in
291 * the data manual for the exact part number in use
292 * before enabling these nodes in the board dts file.
294 ocmcram2: ocmcram@40400000 {
296 compatible = "mmio-sram";
297 reg = <0x40400000 0x100000>;
298 ranges = <0x0 0x40400000 0x100000>;
299 #address-cells = <1>;
303 ocmcram3: ocmcram@40500000 {
305 compatible = "mmio-sram";
306 reg = <0x40500000 0x100000>;
307 ranges = <0x0 0x40500000 0x100000>;
308 #address-cells = <1>;
312 bandgap: bandgap@4a0021e0 {
313 reg = <0x4a0021e0 0xc
319 compatible = "ti,dra752-bandgap";
320 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
321 #thermal-sensor-cells = <1>;
324 dsp1_system: dsp_system@40d00000 {
325 compatible = "syscon";
326 reg = <0x40d00000 0x100>;
329 dra7_iodelay_core: padconf@4844a000 {
330 compatible = "ti,dra7-iodelay";
331 reg = <0x4844a000 0x0d1c>;
332 #address-cells = <1>;
334 #pinctrl-cells = <2>;
337 edma: edma@43300000 {
338 compatible = "ti,edma3-tpcc";
340 reg = <0x43300000 0x100000>;
341 reg-names = "edma3_cc";
342 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-names = "edma3_ccint", "edma3_mperr",
350 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
353 * memcpy is disabled, can be enabled with:
354 * ti,edma-memcpy-channels = <20 21>;
355 * for example. Note that these channels need to be
356 * masked in the xbar as well.
360 edma_tptc0: tptc@43400000 {
361 compatible = "ti,edma3-tptc";
363 reg = <0x43400000 0x100000>;
364 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "edma3_tcerrint";
368 edma_tptc1: tptc@43500000 {
369 compatible = "ti,edma3-tptc";
371 reg = <0x43500000 0x100000>;
372 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
373 interrupt-names = "edma3_tcerrint";
377 compatible = "ti,omap5-dmm";
378 reg = <0x4e000000 0x800>;
379 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
383 target-module@40d01000 {
384 compatible = "ti,sysc-omap2", "ti,sysc";
385 reg = <0x40d01000 0x4>,
388 reg-names = "rev", "sysc", "syss";
389 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
392 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
393 SYSC_OMAP2_SOFTRESET |
394 SYSC_OMAP2_AUTOIDLE)>;
395 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
397 resets = <&prm_dsp1 1>;
398 reset-names = "rstctrl";
399 ranges = <0x0 0x40d01000 0x1000>;
401 #address-cells = <1>;
404 compatible = "ti,dra7-dsp-iommu";
406 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
408 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
412 target-module@40d02000 {
413 compatible = "ti,sysc-omap2", "ti,sysc";
414 reg = <0x40d02000 0x4>,
417 reg-names = "rev", "sysc", "syss";
418 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
421 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
422 SYSC_OMAP2_SOFTRESET |
423 SYSC_OMAP2_AUTOIDLE)>;
424 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
426 resets = <&prm_dsp1 1>;
427 reset-names = "rstctrl";
428 ranges = <0x0 0x40d02000 0x1000>;
430 #address-cells = <1>;
433 compatible = "ti,dra7-dsp-iommu";
435 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
437 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
441 target-module@58882000 {
442 compatible = "ti,sysc-omap2", "ti,sysc";
443 reg = <0x58882000 0x4>,
446 reg-names = "rev", "sysc", "syss";
447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
450 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
451 SYSC_OMAP2_SOFTRESET |
452 SYSC_OMAP2_AUTOIDLE)>;
453 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
455 resets = <&prm_ipu 2>;
456 reset-names = "rstctrl";
457 #address-cells = <1>;
459 ranges = <0x0 0x58882000 0x100>;
462 compatible = "ti,dra7-iommu";
464 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
466 ti,iommu-bus-err-back;
470 target-module@55082000 {
471 compatible = "ti,sysc-omap2", "ti,sysc";
472 reg = <0x55082000 0x4>,
475 reg-names = "rev", "sysc", "syss";
476 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
479 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
480 SYSC_OMAP2_SOFTRESET |
481 SYSC_OMAP2_AUTOIDLE)>;
482 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
484 resets = <&prm_core 2>;
485 reset-names = "rstctrl";
486 #address-cells = <1>;
488 ranges = <0x0 0x55082000 0x100>;
491 compatible = "ti,dra7-iommu";
493 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
495 ti,iommu-bus-err-back;
499 abb_mpu: regulator-abb-mpu {
500 compatible = "ti,abb-v3";
501 regulator-name = "abb_mpu";
502 #address-cells = <0>;
504 clocks = <&sys_clkin1>;
505 ti,settling-time = <50>;
506 ti,clock-cycles = <16>;
508 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
509 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
511 reg-names = "setup-address", "control-address",
512 "int-address", "efuse-address",
514 ti,tranxdone-status-mask = <0x80>;
515 /* LDOVBBMPU_FBB_MUX_CTRL */
516 ti,ldovbb-override-mask = <0x400>;
517 /* LDOVBBMPU_FBB_VSET_OUT */
518 ti,ldovbb-vset-mask = <0x1F>;
521 * NOTE: only FBB mode used but actual vset will
522 * determine final biasing
525 /*uV ABB efuse rbb_m fbb_m vset_m*/
526 1060000 0 0x0 0 0x02000000 0x01F00000
527 1160000 0 0x4 0 0x02000000 0x01F00000
528 1210000 0 0x8 0 0x02000000 0x01F00000
532 abb_ivahd: regulator-abb-ivahd {
533 compatible = "ti,abb-v3";
534 regulator-name = "abb_ivahd";
535 #address-cells = <0>;
537 clocks = <&sys_clkin1>;
538 ti,settling-time = <50>;
539 ti,clock-cycles = <16>;
541 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
542 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
544 reg-names = "setup-address", "control-address",
545 "int-address", "efuse-address",
547 ti,tranxdone-status-mask = <0x40000000>;
548 /* LDOVBBIVA_FBB_MUX_CTRL */
549 ti,ldovbb-override-mask = <0x400>;
550 /* LDOVBBIVA_FBB_VSET_OUT */
551 ti,ldovbb-vset-mask = <0x1F>;
554 * NOTE: only FBB mode used but actual vset will
555 * determine final biasing
558 /*uV ABB efuse rbb_m fbb_m vset_m*/
559 1055000 0 0x0 0 0x02000000 0x01F00000
560 1150000 0 0x4 0 0x02000000 0x01F00000
561 1250000 0 0x8 0 0x02000000 0x01F00000
565 abb_dspeve: regulator-abb-dspeve {
566 compatible = "ti,abb-v3";
567 regulator-name = "abb_dspeve";
568 #address-cells = <0>;
570 clocks = <&sys_clkin1>;
571 ti,settling-time = <50>;
572 ti,clock-cycles = <16>;
574 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
575 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
577 reg-names = "setup-address", "control-address",
578 "int-address", "efuse-address",
580 ti,tranxdone-status-mask = <0x20000000>;
581 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
582 ti,ldovbb-override-mask = <0x400>;
583 /* LDOVBBDSPEVE_FBB_VSET_OUT */
584 ti,ldovbb-vset-mask = <0x1F>;
587 * NOTE: only FBB mode used but actual vset will
588 * determine final biasing
591 /*uV ABB efuse rbb_m fbb_m vset_m*/
592 1055000 0 0x0 0 0x02000000 0x01F00000
593 1150000 0 0x4 0 0x02000000 0x01F00000
594 1250000 0 0x8 0 0x02000000 0x01F00000
598 abb_gpu: regulator-abb-gpu {
599 compatible = "ti,abb-v3";
600 regulator-name = "abb_gpu";
601 #address-cells = <0>;
603 clocks = <&sys_clkin1>;
604 ti,settling-time = <50>;
605 ti,clock-cycles = <16>;
607 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
608 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
610 reg-names = "setup-address", "control-address",
611 "int-address", "efuse-address",
613 ti,tranxdone-status-mask = <0x10000000>;
614 /* LDOVBBGPU_FBB_MUX_CTRL */
615 ti,ldovbb-override-mask = <0x400>;
616 /* LDOVBBGPU_FBB_VSET_OUT */
617 ti,ldovbb-vset-mask = <0x1F>;
620 * NOTE: only FBB mode used but actual vset will
621 * determine final biasing
624 /*uV ABB efuse rbb_m fbb_m vset_m*/
625 1090000 0 0x0 0 0x02000000 0x01F00000
626 1210000 0 0x4 0 0x02000000 0x01F00000
627 1280000 0 0x8 0 0x02000000 0x01F00000
632 compatible = "ti,dra7xxx-qspi";
633 reg = <0x4b300000 0x100>,
634 <0x5c000000 0x4000000>;
635 reg-names = "qspi_base", "qspi_mmap";
636 syscon-chipselects = <&scm_conf 0x558>;
637 #address-cells = <1>;
640 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
643 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
648 sata: sata@4a141100 {
649 compatible = "snps,dwc-ahci";
650 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
651 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
653 phy-names = "sata-phy";
654 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
656 ports-implemented = <0x1>;
660 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
661 gpmc: gpmc@50000000 {
662 compatible = "ti,am3352-gpmc";
664 reg = <0x50000000 0x37c>; /* device IO registers */
665 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
666 dmas = <&edma_xbar 4 0>;
669 gpmc,num-waitpins = <2>;
670 #address-cells = <2>;
672 interrupt-controller;
673 #interrupt-cells = <2>;
679 target-module@56000000 {
680 compatible = "ti,sysc-omap4", "ti,sysc";
681 reg = <0x5600fe00 0x4>,
683 reg-names = "rev", "sysc";
684 ti,sysc-midle = <SYSC_IDLE_FORCE>,
687 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
690 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
692 #address-cells = <1>;
694 ranges = <0 0x56000000 0x2000000>;
697 crossbar_mpu: crossbar@4a002a48 {
698 compatible = "ti,irq-crossbar";
699 reg = <0x4a002a48 0x130>;
700 interrupt-controller;
701 interrupt-parent = <&wakeupgen>;
702 #interrupt-cells = <3>;
704 ti,max-crossbar-sources = <MAX_SOURCES>;
706 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
707 ti,irqs-skip = <10 133 139 140>;
708 ti,irqs-safe-map = <0>;
712 compatible = "ti,dra7-dss";
713 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
714 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
716 ti,hwmods = "dss_core";
717 /* CTRL_CORE_DSS_PLL_CONTROL */
718 syscon-pll-ctrl = <&scm_conf 0x538>;
719 #address-cells = <1>;
724 compatible = "ti,dra7-dispc";
725 reg = <0x58001000 0x1000>;
726 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
727 ti,hwmods = "dss_dispc";
728 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
730 /* CTRL_CORE_SMA_SW_1 */
731 syscon-pol = <&scm_conf 0x534>;
734 hdmi: encoder@58060000 {
735 compatible = "ti,dra7-hdmi";
736 reg = <0x58040000 0x200>,
739 <0x58060000 0x19000>;
740 reg-names = "wp", "pll", "phy", "core";
741 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
743 ti,hwmods = "dss_hdmi";
744 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
745 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
746 clock-names = "fck", "sys_clk";
747 dmas = <&sdma_xbar 76>;
748 dma-names = "audio_tx";
752 aes1_target: target-module@4b500000 {
753 compatible = "ti,sysc-omap2", "ti,sysc";
754 reg = <0x4b500080 0x4>,
757 reg-names = "rev", "sysc", "syss";
758 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
759 SYSC_OMAP2_AUTOIDLE)>;
760 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
763 <SYSC_IDLE_SMART_WKUP>;
765 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
766 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
768 #address-cells = <1>;
770 ranges = <0x0 0x4b500000 0x1000>;
773 compatible = "ti,omap4-aes";
775 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
776 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
777 dma-names = "tx", "rx";
778 clocks = <&l3_iclk_div>;
783 aes2_target: target-module@4b700000 {
784 compatible = "ti,sysc-omap2", "ti,sysc";
785 reg = <0x4b700080 0x4>,
788 reg-names = "rev", "sysc", "syss";
789 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
790 SYSC_OMAP2_AUTOIDLE)>;
791 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
794 <SYSC_IDLE_SMART_WKUP>;
796 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
797 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
799 #address-cells = <1>;
801 ranges = <0x0 0x4b700000 0x1000>;
804 compatible = "ti,omap4-aes";
806 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
807 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
808 dma-names = "tx", "rx";
809 clocks = <&l3_iclk_div>;
814 sham_target: target-module@4b101000 {
815 compatible = "ti,sysc-omap3-sham", "ti,sysc";
816 reg = <0x4b101100 0x4>,
819 reg-names = "rev", "sysc", "syss";
820 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
821 SYSC_OMAP2_AUTOIDLE)>;
822 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
826 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
827 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
829 #address-cells = <1>;
831 ranges = <0x0 0x4b101000 0x1000>;
834 compatible = "ti,omap5-sham";
836 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
837 dmas = <&edma_xbar 119 0>;
839 clocks = <&l3_iclk_div>;
844 opp_supply_mpu: opp-supply@4a003b20 {
845 compatible = "ti,omap5-opp-supply";
846 reg = <0x4a003b20 0xc>;
847 ti,efuse-settings = <
853 ti,absolute-max-voltage-uv = <1500000>;
858 thermal_zones: thermal-zones {
859 #include "omap4-cpu-thermal.dtsi"
860 #include "omap5-gpu-thermal.dtsi"
861 #include "omap5-core-thermal.dtsi"
862 #include "dra7-dspeve-thermal.dtsi"
863 #include "dra7-iva-thermal.dtsi"
869 polling-delay = <500>; /* milliseconds */
870 coefficients = <0 2000>;
874 coefficients = <0 2000>;
878 coefficients = <0 2000>;
882 coefficients = <0 2000>;
886 coefficients = <0 2000>;
890 temperature = <120000>; /* milli Celsius */
894 temperature = <120000>; /* milli Celsius */
898 temperature = <120000>; /* milli Celsius */
902 temperature = <120000>; /* milli Celsius */
906 temperature = <120000>; /* milli Celsius */
909 #include "dra7-l4.dtsi"
910 #include "dra7xx-clocks.dtsi"
914 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
920 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
926 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
932 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
937 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
943 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
948 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
953 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
958 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";