1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
11 compatible = "marvell,berlin2q", "marvell,berlin";
23 enable-method = "marvell,berlin-smp";
26 compatible = "arm,cortex-a9";
28 next-level-cache = <&l2>;
31 clocks = <&chip_clk CLKID_CPU>;
32 clock-latency = <100000>;
33 /* Can be modified by the bootloader */
44 compatible = "arm,cortex-a9";
46 next-level-cache = <&l2>;
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&l2>;
58 compatible = "arm,cortex-a9";
60 next-level-cache = <&l2>;
66 compatible = "arm,cortex-a9-pmu";
67 interrupt-parent = <&gic>;
68 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
72 interrupt-affinity = <&cpu0>,
79 compatible = "fixed-clock";
81 clock-frequency = <25000000>;
85 compatible = "simple-bus";
89 ranges = <0 0xf7000000 0x1000000>;
90 interrupt-parent = <&gic>;
92 sdhci0: sdhci@ab0000 {
93 compatible = "mrvl,pxav3-mmc";
94 reg = <0xab0000 0x200>;
95 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
96 clock-names = "io", "core";
97 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
101 sdhci1: sdhci@ab0800 {
102 compatible = "mrvl,pxav3-mmc";
103 reg = <0xab0800 0x200>;
104 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
105 clock-names = "io", "core";
106 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
110 sdhci2: sdhci@ab1000 {
111 compatible = "mrvl,pxav3-mmc";
112 reg = <0xab1000 0x200>;
113 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
115 clock-names = "io", "core";
119 l2: l2-cache-controller@ac0000 {
120 compatible = "arm,pl310-cache";
121 reg = <0xac0000 0x1000>;
124 arm,data-latency = <2 2 2>;
125 arm,tag-latency = <2 2 2>;
128 scu: snoop-control-unit@ad0000 {
129 compatible = "arm,cortex-a9-scu";
130 reg = <0xad0000 0x58>;
134 compatible = "arm,cortex-a9-twd-timer";
135 reg = <0xad0600 0x20>;
136 clocks = <&chip_clk CLKID_TWD>;
137 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
140 gic: interrupt-controller@ad1000 {
141 compatible = "arm,cortex-a9-gic";
142 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
143 interrupt-controller;
144 #interrupt-cells = <3>;
147 usb_phy2: phy@a2f400 {
148 compatible = "marvell,berlin2cd-usb-phy";
149 reg = <0xa2f400 0x128>;
151 resets = <&chip_rst 0x104 14>;
156 compatible = "chipidea,usb2";
157 reg = <0xa30000 0x10000>;
158 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&chip_clk CLKID_USB2>;
161 phy-names = "usb-phy";
165 usb_phy0: phy@b74000 {
166 compatible = "marvell,berlin2cd-usb-phy";
167 reg = <0xb74000 0x128>;
169 resets = <&chip_rst 0x104 12>;
173 usb_phy1: phy@b78000 {
174 compatible = "marvell,berlin2cd-usb-phy";
175 reg = <0xb78000 0x128>;
177 resets = <&chip_rst 0x104 13>;
181 eth0: ethernet@b90000 {
182 compatible = "marvell,pxa168-eth";
183 reg = <0xb90000 0x10000>;
184 clocks = <&chip_clk CLKID_GETH0>;
185 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
186 /* set by bootloader */
187 local-mac-address = [00 00 00 00 00 00];
188 #address-cells = <1>;
190 phy-connection-type = "mii";
191 phy-handle = <ðphy0>;
194 ethphy0: ethernet-phy@0 {
200 compatible = "marvell,berlin-cpu-ctrl";
201 reg = <0xdd0000 0x10000>;
205 compatible = "simple-bus";
206 #address-cells = <1>;
209 ranges = <0 0xe80000 0x10000>;
210 interrupt-parent = <&aic>;
213 compatible = "snps,dw-apb-gpio";
214 reg = <0x0400 0x400>;
215 #address-cells = <1>;
219 compatible = "snps,dw-apb-gpio-port";
222 snps,nr-gpios = <32>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
231 compatible = "snps,dw-apb-gpio";
232 reg = <0x0800 0x400>;
233 #address-cells = <1>;
237 compatible = "snps,dw-apb-gpio-port";
240 snps,nr-gpios = <32>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
249 compatible = "snps,dw-apb-gpio";
250 reg = <0x0c00 0x400>;
251 #address-cells = <1>;
255 compatible = "snps,dw-apb-gpio-port";
258 snps,nr-gpios = <32>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
267 compatible = "snps,dw-apb-gpio";
268 reg = <0x1000 0x400>;
269 #address-cells = <1>;
273 compatible = "snps,dw-apb-gpio-port";
276 snps,nr-gpios = <32>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
285 compatible = "snps,designware-i2c";
286 #address-cells = <1>;
288 reg = <0x1400 0x100>;
290 clocks = <&chip_clk CLKID_CFG>;
291 pinctrl-0 = <&twsi0_pmux>;
292 pinctrl-names = "default";
297 compatible = "snps,designware-i2c";
298 #address-cells = <1>;
300 reg = <0x1800 0x100>;
302 clocks = <&chip_clk CLKID_CFG>;
303 pinctrl-0 = <&twsi1_pmux>;
304 pinctrl-names = "default";
309 compatible = "snps,dw-apb-timer";
311 clocks = <&chip_clk CLKID_CFG>;
312 clock-names = "timer";
317 compatible = "snps,dw-apb-timer";
319 clocks = <&chip_clk CLKID_CFG>;
320 clock-names = "timer";
324 compatible = "snps,dw-apb-timer";
326 clocks = <&chip_clk CLKID_CFG>;
327 clock-names = "timer";
332 compatible = "snps,dw-apb-timer";
334 clocks = <&chip_clk CLKID_CFG>;
335 clock-names = "timer";
340 compatible = "snps,dw-apb-timer";
342 clocks = <&chip_clk CLKID_CFG>;
343 clock-names = "timer";
348 compatible = "snps,dw-apb-timer";
350 clocks = <&chip_clk CLKID_CFG>;
351 clock-names = "timer";
356 compatible = "snps,dw-apb-timer";
358 clocks = <&chip_clk CLKID_CFG>;
359 clock-names = "timer";
364 compatible = "snps,dw-apb-timer";
366 clocks = <&chip_clk CLKID_CFG>;
367 clock-names = "timer";
371 aic: interrupt-controller@3800 {
372 compatible = "snps,dw-apb-ictl";
374 interrupt-controller;
375 #interrupt-cells = <1>;
376 interrupt-parent = <&gic>;
377 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
381 chip: chip-control@ea0000 {
382 compatible = "simple-mfd", "syscon";
383 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
386 compatible = "marvell,berlin2q-clk";
389 clock-names = "refclk";
392 soc_pinctrl: pin-controller {
393 compatible = "marvell,berlin2q-soc-pinctrl";
400 twsi0_pmux: twsi0-pmux {
405 twsi1_pmux: twsi1-pmux {
412 compatible = "marvell,berlin2-reset";
418 compatible = "marvell,berlin2q-ahci", "generic-ahci";
419 reg = <0xe90000 0x1000>;
420 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&chip_clk CLKID_SATA>;
422 #address-cells = <1>;
427 phys = <&sata_phy 0>;
433 phys = <&sata_phy 1>;
438 sata_phy: phy@e900a0 {
439 compatible = "marvell,berlin2q-sata-phy";
440 reg = <0xe900a0 0x200>;
441 clocks = <&chip_clk CLKID_SATA>;
442 #address-cells = <1>;
457 compatible = "chipidea,usb2";
458 reg = <0xed0000 0x10000>;
459 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&chip_clk CLKID_USB0>;
462 phy-names = "usb-phy";
467 compatible = "chipidea,usb2";
468 reg = <0xee0000 0x10000>;
469 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&chip_clk CLKID_USB1>;
472 phy-names = "usb-phy";
477 compatible = "marvell,berlin-pwm";
478 reg = <0xf20000 0x40>;
479 clocks = <&chip_clk CLKID_CFG>;
484 compatible = "simple-bus";
485 #address-cells = <1>;
488 ranges = <0 0xfc0000 0x10000>;
489 interrupt-parent = <&sic>;
491 wdt0: watchdog@1000 {
492 compatible = "snps,dw-wdt";
493 reg = <0x1000 0x100>;
498 wdt1: watchdog@2000 {
499 compatible = "snps,dw-wdt";
500 reg = <0x2000 0x100>;
505 wdt2: watchdog@3000 {
506 compatible = "snps,dw-wdt";
507 reg = <0x3000 0x100>;
512 sm_gpio1: gpio@5000 {
513 compatible = "snps,dw-apb-gpio";
514 reg = <0x5000 0x400>;
515 #address-cells = <1>;
519 compatible = "snps,dw-apb-gpio-port";
522 snps,nr-gpios = <32>;
528 compatible = "snps,designware-i2c";
529 #address-cells = <1>;
531 reg = <0x7000 0x100>;
534 pinctrl-0 = <&twsi2_pmux>;
535 pinctrl-names = "default";
540 compatible = "snps,designware-i2c";
541 #address-cells = <1>;
543 reg = <0x8000 0x100>;
546 pinctrl-0 = <&twsi3_pmux>;
547 pinctrl-names = "default";
552 compatible = "snps,dw-apb-uart";
553 reg = <0x9000 0x100>;
557 pinctrl-0 = <&uart0_pmux>;
558 pinctrl-names = "default";
563 compatible = "snps,dw-apb-uart";
564 reg = <0xa000 0x100>;
568 pinctrl-0 = <&uart1_pmux>;
569 pinctrl-names = "default";
573 sm_gpio0: gpio@c000 {
574 compatible = "snps,dw-apb-gpio";
575 reg = <0xc000 0x400>;
576 #address-cells = <1>;
580 compatible = "snps,dw-apb-gpio-port";
583 snps,nr-gpios = <32>;
588 sysctrl: pin-controller@d000 {
589 compatible = "simple-mfd", "syscon";
590 reg = <0xd000 0x100>;
592 sys_pinctrl: pin-controller {
593 compatible = "marvell,berlin2q-system-pinctrl";
595 uart0_pmux: uart0-pmux {
600 uart1_pmux: uart1-pmux {
605 twsi2_pmux: twsi2-pmux {
610 twsi3_pmux: twsi3-pmux {
617 compatible = "marvell,berlin2-adc";
618 interrupts = <12>, <14>;
619 interrupt-names = "adc", "tsen";
623 sic: interrupt-controller@e000 {
624 compatible = "snps,dw-apb-ictl";
626 interrupt-controller;
627 #interrupt-cells = <1>;
628 interrupt-parent = <&gic>;
629 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;