1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
7 /* firmware-provided startup stubs live here, where the secondary CPUs are
10 /memreserve/ 0x00000000 0x00001000;
12 /* This include file covers the common peripherals and configuration between
13 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
14 * bcm2835.dtsi and bcm2836.dtsi.
18 compatible = "brcm,bcm2835";
20 interrupt-parent = <&intc>;
30 stdout-path = "serial0:115200n8";
34 cpu_thermal: cpu-thermal {
35 polling-delay-passive = <0>;
36 polling-delay = <1000>;
38 thermal-sensors = <&thermal>;
42 temperature = <80000>;
54 compatible = "simple-bus";
59 compatible = "brcm,bcm2835-system-timer";
60 reg = <0x7e003000 0x1000>;
61 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
62 /* This could be a reference to BCM2835_CLOCK_TIMER,
63 * but we don't have the driver using the common clock
66 clock-frequency = <1000000>;
70 compatible = "brcm,bcm2835-dma";
71 reg = <0x7e007000 0xf00>;
83 /* dma channel 11-14 share one irq */
88 /* unused shared irq for all channels */
90 interrupt-names = "dma0",
107 brcm,dma-channel-mask = <0x7f35>;
110 intc: interrupt-controller@7e00b200 {
111 compatible = "brcm,bcm2835-armctrl-ic";
112 reg = <0x7e00b200 0x200>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
118 compatible = "brcm,bcm2835-pm-wdt";
119 reg = <0x7e100000 0x28>;
122 clocks: cprman@7e101000 {
123 compatible = "brcm,bcm2835-cprman";
125 reg = <0x7e101000 0x2000>;
127 /* CPRMAN derives almost everything from the
128 * platform's oscillator. However, the DSI
129 * pixel clocks come from the DSI analog PHY.
132 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
133 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
137 compatible = "brcm,bcm2835-rng";
138 reg = <0x7e104000 0x10>;
142 mailbox: mailbox@7e00b880 {
143 compatible = "brcm,bcm2835-mbox";
144 reg = <0x7e00b880 0x40>;
149 gpio: gpio@7e200000 {
150 compatible = "brcm,bcm2835-gpio";
151 reg = <0x7e200000 0xb4>;
153 * The GPIO IP block is designed for 3 banks of GPIOs.
154 * Each bank has a GPIO interrupt for itself.
155 * There is an overall "any bank" interrupt.
156 * In order, these are GIC interrupts 17, 18, 19, 20.
157 * Since the BCM2835 only has 2 banks, the 2nd bank
158 * interrupt output appears to be mirrored onto the
159 * 3rd bank's interrupt signal.
160 * So, a bank0 interrupt shows up on 17, 20, and
161 * a bank1 interrupt shows up on 18, 19, 20!
163 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
171 /* Defines pin muxing groups according to
172 * BCM2835-ARM-Peripherals.pdf page 102.
174 * While each pin can have its mux selected
175 * for various functions individually, some
176 * groups only make sense to switch to a
177 * particular function together.
179 dpi_gpio0: dpi_gpio0 {
180 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
181 12 13 14 15 16 17 18 19
182 20 21 22 23 24 25 26 27>;
183 brcm,function = <BCM2835_FSEL_ALT2>;
185 emmc_gpio22: emmc_gpio22 {
186 brcm,pins = <22 23 24 25 26 27>;
187 brcm,function = <BCM2835_FSEL_ALT3>;
189 emmc_gpio34: emmc_gpio34 {
190 brcm,pins = <34 35 36 37 38 39>;
191 brcm,function = <BCM2835_FSEL_ALT3>;
192 brcm,pull = <BCM2835_PUD_OFF
199 emmc_gpio48: emmc_gpio48 {
200 brcm,pins = <48 49 50 51 52 53>;
201 brcm,function = <BCM2835_FSEL_ALT3>;
204 gpclk0_gpio4: gpclk0_gpio4 {
206 brcm,function = <BCM2835_FSEL_ALT0>;
208 gpclk1_gpio5: gpclk1_gpio5 {
210 brcm,function = <BCM2835_FSEL_ALT0>;
212 gpclk1_gpio42: gpclk1_gpio42 {
214 brcm,function = <BCM2835_FSEL_ALT0>;
216 gpclk1_gpio44: gpclk1_gpio44 {
218 brcm,function = <BCM2835_FSEL_ALT0>;
220 gpclk2_gpio6: gpclk2_gpio6 {
222 brcm,function = <BCM2835_FSEL_ALT0>;
224 gpclk2_gpio43: gpclk2_gpio43 {
226 brcm,function = <BCM2835_FSEL_ALT0>;
227 brcm,pull = <BCM2835_PUD_OFF>;
230 i2c0_gpio0: i2c0_gpio0 {
232 brcm,function = <BCM2835_FSEL_ALT0>;
234 i2c0_gpio28: i2c0_gpio28 {
236 brcm,function = <BCM2835_FSEL_ALT0>;
238 i2c0_gpio44: i2c0_gpio44 {
240 brcm,function = <BCM2835_FSEL_ALT1>;
242 i2c1_gpio2: i2c1_gpio2 {
244 brcm,function = <BCM2835_FSEL_ALT0>;
246 i2c1_gpio44: i2c1_gpio44 {
248 brcm,function = <BCM2835_FSEL_ALT2>;
250 i2c_slave_gpio18: i2c_slave_gpio18 {
251 brcm,pins = <18 19 20 21>;
252 brcm,function = <BCM2835_FSEL_ALT3>;
255 jtag_gpio4: jtag_gpio4 {
256 brcm,pins = <4 5 6 12 13>;
257 brcm,function = <BCM2835_FSEL_ALT5>;
259 jtag_gpio22: jtag_gpio22 {
260 brcm,pins = <22 23 24 25 26 27>;
261 brcm,function = <BCM2835_FSEL_ALT4>;
264 pcm_gpio18: pcm_gpio18 {
265 brcm,pins = <18 19 20 21>;
266 brcm,function = <BCM2835_FSEL_ALT0>;
268 pcm_gpio28: pcm_gpio28 {
269 brcm,pins = <28 29 30 31>;
270 brcm,function = <BCM2835_FSEL_ALT2>;
273 pwm0_gpio12: pwm0_gpio12 {
275 brcm,function = <BCM2835_FSEL_ALT0>;
277 pwm0_gpio18: pwm0_gpio18 {
279 brcm,function = <BCM2835_FSEL_ALT5>;
281 pwm0_gpio40: pwm0_gpio40 {
283 brcm,function = <BCM2835_FSEL_ALT0>;
285 pwm1_gpio13: pwm1_gpio13 {
287 brcm,function = <BCM2835_FSEL_ALT0>;
289 pwm1_gpio19: pwm1_gpio19 {
291 brcm,function = <BCM2835_FSEL_ALT5>;
293 pwm1_gpio41: pwm1_gpio41 {
295 brcm,function = <BCM2835_FSEL_ALT0>;
297 pwm1_gpio45: pwm1_gpio45 {
299 brcm,function = <BCM2835_FSEL_ALT0>;
302 sdhost_gpio48: sdhost_gpio48 {
303 brcm,pins = <48 49 50 51 52 53>;
304 brcm,function = <BCM2835_FSEL_ALT0>;
307 spi0_gpio7: spi0_gpio7 {
308 brcm,pins = <7 8 9 10 11>;
309 brcm,function = <BCM2835_FSEL_ALT0>;
311 spi0_gpio35: spi0_gpio35 {
312 brcm,pins = <35 36 37 38 39>;
313 brcm,function = <BCM2835_FSEL_ALT0>;
315 spi1_gpio16: spi1_gpio16 {
316 brcm,pins = <16 17 18 19 20 21>;
317 brcm,function = <BCM2835_FSEL_ALT4>;
319 spi2_gpio40: spi2_gpio40 {
320 brcm,pins = <40 41 42 43 44 45>;
321 brcm,function = <BCM2835_FSEL_ALT4>;
324 uart0_gpio14: uart0_gpio14 {
326 brcm,function = <BCM2835_FSEL_ALT0>;
328 /* Separate from the uart0_gpio14 group
329 * because it conflicts with spi1_gpio16, and
330 * people often run uart0 on the two pins
331 * without flow control.
333 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
335 brcm,function = <BCM2835_FSEL_ALT3>;
337 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
339 brcm,function = <BCM2835_FSEL_ALT3>;
340 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
342 uart0_gpio32: uart0_gpio32 {
344 brcm,function = <BCM2835_FSEL_ALT3>;
345 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
347 uart0_gpio36: uart0_gpio36 {
349 brcm,function = <BCM2835_FSEL_ALT2>;
351 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
353 brcm,function = <BCM2835_FSEL_ALT2>;
356 uart1_gpio14: uart1_gpio14 {
358 brcm,function = <BCM2835_FSEL_ALT5>;
360 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
362 brcm,function = <BCM2835_FSEL_ALT5>;
364 uart1_gpio32: uart1_gpio32 {
366 brcm,function = <BCM2835_FSEL_ALT5>;
368 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
370 brcm,function = <BCM2835_FSEL_ALT5>;
372 uart1_gpio40: uart1_gpio40 {
374 brcm,function = <BCM2835_FSEL_ALT5>;
376 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
378 brcm,function = <BCM2835_FSEL_ALT5>;
382 uart0: serial@7e201000 {
383 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
384 reg = <0x7e201000 0x1000>;
386 clocks = <&clocks BCM2835_CLOCK_UART>,
387 <&clocks BCM2835_CLOCK_VPU>;
388 clock-names = "uartclk", "apb_pclk";
389 arm,primecell-periphid = <0x00241011>;
392 sdhost: mmc@7e202000 {
393 compatible = "brcm,bcm2835-sdhost";
394 reg = <0x7e202000 0x100>;
396 clocks = <&clocks BCM2835_CLOCK_VPU>;
403 compatible = "brcm,bcm2835-i2s";
404 reg = <0x7e203000 0x24>;
405 clocks = <&clocks BCM2835_CLOCK_PCM>;
409 dma-names = "tx", "rx";
414 compatible = "brcm,bcm2835-spi";
415 reg = <0x7e204000 0x1000>;
417 clocks = <&clocks BCM2835_CLOCK_VPU>;
418 #address-cells = <1>;
424 compatible = "brcm,bcm2835-i2c";
425 reg = <0x7e205000 0x1000>;
427 clocks = <&clocks BCM2835_CLOCK_VPU>;
428 #address-cells = <1>;
433 pixelvalve@7e206000 {
434 compatible = "brcm,bcm2835-pixelvalve0";
435 reg = <0x7e206000 0x100>;
436 interrupts = <2 13>; /* pwa0 */
439 pixelvalve@7e207000 {
440 compatible = "brcm,bcm2835-pixelvalve1";
441 reg = <0x7e207000 0x100>;
442 interrupts = <2 14>; /* pwa1 */
446 compatible = "brcm,bcm2835-dpi";
447 reg = <0x7e208000 0x8c>;
448 clocks = <&clocks BCM2835_CLOCK_VPU>,
449 <&clocks BCM2835_CLOCK_DPI>;
450 clock-names = "core", "pixel";
451 #address-cells = <1>;
457 compatible = "brcm,bcm2835-dsi0";
458 reg = <0x7e209000 0x78>;
460 #address-cells = <1>;
464 clocks = <&clocks BCM2835_PLLA_DSI0>,
465 <&clocks BCM2835_CLOCK_DSI0E>,
466 <&clocks BCM2835_CLOCK_DSI0P>;
467 clock-names = "phy", "escape", "pixel";
469 clock-output-names = "dsi0_byte",
475 thermal: thermal@7e212000 {
476 compatible = "brcm,bcm2835-thermal";
477 reg = <0x7e212000 0x8>;
478 clocks = <&clocks BCM2835_CLOCK_TSENS>;
479 #thermal-sensor-cells = <0>;
484 compatible = "brcm,bcm2835-aux";
486 reg = <0x7e215000 0x8>;
487 clocks = <&clocks BCM2835_CLOCK_VPU>;
490 uart1: serial@7e215040 {
491 compatible = "brcm,bcm2835-aux-uart";
492 reg = <0x7e215040 0x40>;
494 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
499 compatible = "brcm,bcm2835-aux-spi";
500 reg = <0x7e215080 0x40>;
502 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
503 #address-cells = <1>;
509 compatible = "brcm,bcm2835-aux-spi";
510 reg = <0x7e2150c0 0x40>;
512 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
513 #address-cells = <1>;
519 compatible = "brcm,bcm2835-pwm";
520 reg = <0x7e20c000 0x28>;
521 clocks = <&clocks BCM2835_CLOCK_PWM>;
522 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
523 assigned-clock-rates = <10000000>;
528 sdhci: sdhci@7e300000 {
529 compatible = "brcm,bcm2835-sdhci";
530 reg = <0x7e300000 0x100>;
532 clocks = <&clocks BCM2835_CLOCK_EMMC>;
537 compatible = "brcm,bcm2835-hvs";
538 reg = <0x7e400000 0x6000>;
543 compatible = "brcm,bcm2835-dsi1";
544 reg = <0x7e700000 0x8c>;
546 #address-cells = <1>;
550 clocks = <&clocks BCM2835_PLLD_DSI1>,
551 <&clocks BCM2835_CLOCK_DSI1E>,
552 <&clocks BCM2835_CLOCK_DSI1P>;
553 clock-names = "phy", "escape", "pixel";
555 clock-output-names = "dsi1_byte",
563 compatible = "brcm,bcm2835-i2c";
564 reg = <0x7e804000 0x1000>;
566 clocks = <&clocks BCM2835_CLOCK_VPU>;
567 #address-cells = <1>;
573 compatible = "brcm,bcm2835-i2c";
574 reg = <0x7e805000 0x1000>;
576 clocks = <&clocks BCM2835_CLOCK_VPU>;
577 #address-cells = <1>;
583 compatible = "brcm,bcm2835-vec";
584 reg = <0x7e806000 0x1000>;
585 clocks = <&clocks BCM2835_CLOCK_VEC>;
590 pixelvalve@7e807000 {
591 compatible = "brcm,bcm2835-pixelvalve2";
592 reg = <0x7e807000 0x100>;
593 interrupts = <2 10>; /* pixelvalve */
596 hdmi: hdmi@7e902000 {
597 compatible = "brcm,bcm2835-hdmi";
598 reg = <0x7e902000 0x600>,
600 interrupts = <2 8>, <2 9>;
602 clocks = <&clocks BCM2835_PLLH_PIX>,
603 <&clocks BCM2835_CLOCK_HSM>;
604 clock-names = "pixel", "hdmi";
606 dma-names = "audio-rx";
611 compatible = "brcm,bcm2835-usb";
612 reg = <0x7e980000 0x10000>;
614 #address-cells = <1>;
619 phy-names = "usb2-phy";
623 compatible = "brcm,bcm2835-v3d";
624 reg = <0x7ec00000 0x1000>;
629 compatible = "brcm,bcm2835-vc4";
634 compatible = "simple-bus";
635 #address-cells = <1>;
638 /* The oscillator is the root of the clock tree. */
640 compatible = "fixed-clock";
643 clock-output-names = "osc";
644 clock-frequency = <19200000>;
648 compatible = "fixed-clock";
651 clock-output-names = "otg";
652 clock-frequency = <480000000>;
657 compatible = "usb-nop-xceiv";