1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
7 compatible = "aspeed,ast2500";
10 interrupt-parent = <&vic>;
40 compatible = "arm,arm1176jzf-s";
47 device_type = "memory";
52 compatible = "simple-bus";
58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
61 compatible = "aspeed,ast2500-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
68 spi-max-frequency = <50000000>;
69 spi-rx-bus-width = <2>;
74 compatible = "jedec,spi-nor";
75 spi-max-frequency = <50000000>;
76 spi-rx-bus-width = <2>;
81 compatible = "jedec,spi-nor";
82 spi-max-frequency = <50000000>;
83 spi-rx-bus-width = <2>;
89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
92 compatible = "aspeed,ast2500-spi";
93 clocks = <&syscon ASPEED_CLK_AHB>;
97 compatible = "jedec,spi-nor";
98 spi-max-frequency = <50000000>;
99 spi-rx-bus-width = <2>;
104 compatible = "jedec,spi-nor";
105 spi-max-frequency = <50000000>;
106 spi-rx-bus-width = <2>;
112 reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
113 #address-cells = <1>;
115 compatible = "aspeed,ast2500-spi";
116 clocks = <&syscon ASPEED_CLK_AHB>;
120 compatible = "jedec,spi-nor";
121 spi-max-frequency = <50000000>;
122 spi-rx-bus-width = <2>;
127 compatible = "jedec,spi-nor";
128 spi-max-frequency = <50000000>;
129 spi-rx-bus-width = <2>;
134 vic: interrupt-controller@1e6c0080 {
135 compatible = "aspeed,ast2400-vic";
136 interrupt-controller;
137 #interrupt-cells = <1>;
138 valid-sources = <0xfefff7ff 0x0807ffff>;
139 reg = <0x1e6c0080 0x80>;
142 cvic: copro-interrupt-controller@1e6c2000 {
143 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
144 valid-sources = <0xffffffff>;
145 copro-sw-interrupts = <1>;
146 reg = <0x1e6c2000 0x80>;
149 mac0: ethernet@1e660000 {
150 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
151 reg = <0x1e660000 0x180>;
153 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
157 mac1: ethernet@1e680000 {
158 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
159 reg = <0x1e680000 0x180>;
161 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
165 ehci0: usb@1e6a1000 {
166 compatible = "aspeed,ast2500-ehci", "generic-ehci";
167 reg = <0x1e6a1000 0x100>;
169 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_usb2ah_default>;
175 ehci1: usb@1e6a3000 {
176 compatible = "aspeed,ast2500-ehci", "generic-ehci";
177 reg = <0x1e6a3000 0x100>;
179 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usb2bh_default>;
186 compatible = "aspeed,ast2500-uhci", "generic-uhci";
187 reg = <0x1e6b0000 0x100>;
190 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
193 * No default pinmux, it will follow EHCI, use an explicit pinmux
194 * override if you don't enable EHCI
198 vhub: usb-vhub@1e6a0000 {
199 compatible = "aspeed,ast2500-usb-vhub";
200 reg = <0x1e6a0000 0x300>;
202 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
203 aspeed,vhub-downstream-ports = <5>;
204 aspeed,vhub-generic-endpoints = <15>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_usb2ad_default>;
211 compatible = "simple-bus";
212 #address-cells = <1>;
216 edac: memory-controller@1e6e0000 {
217 compatible = "aspeed,ast2500-sdram-edac";
218 reg = <0x1e6e0000 0x174>;
223 syscon: syscon@1e6e2000 {
224 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
225 reg = <0x1e6e2000 0x1a8>;
226 #address-cells = <1>;
228 ranges = <0 0x1e6e2000 0x1000>;
232 scu_ic: interrupt-controller@18 {
233 #interrupt-cells = <1>;
234 compatible = "aspeed,ast2500-scu-ic";
237 interrupt-controller;
240 p2a: p2a-control@2c {
241 compatible = "aspeed,ast2500-p2a-ctrl";
247 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
248 reg = <0x7c 0x4 0x150 0x8>;
251 pinctrl: pinctrl@80 {
252 compatible = "aspeed,ast2500-pinctrl";
253 reg = <0x80 0x18>, <0xa0 0x10>;
254 aspeed,external-nodes = <&gfx>, <&lhc>;
258 rng: hwrng@1e6e2078 {
259 compatible = "timeriomem_rng";
260 reg = <0x1e6e2078 0x4>;
265 hace: crypto@1e6e3000 {
266 compatible = "aspeed,ast2500-hace";
267 reg = <0x1e6e3000 0x100>;
269 clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
270 resets = <&syscon ASPEED_RESET_HACE>;
273 gfx: display@1e6e6000 {
274 compatible = "aspeed,ast2500-gfx", "syscon";
275 reg = <0x1e6e6000 0x1000>;
277 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
278 resets = <&syscon ASPEED_RESET_CRT1>;
284 xdma: xdma@1e6e7000 {
285 compatible = "aspeed,ast2500-xdma";
286 reg = <0x1e6e7000 0x100>;
287 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
288 resets = <&syscon ASPEED_RESET_XDMA>;
289 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
290 aspeed,pcie-device = "bmc";
291 aspeed,scu = <&syscon>;
296 compatible = "aspeed,ast2500-adc";
297 reg = <0x1e6e9000 0xb0>;
298 clocks = <&syscon ASPEED_CLK_APB>;
299 resets = <&syscon ASPEED_RESET_ADC>;
300 #io-channel-cells = <1>;
304 video: video@1e700000 {
305 compatible = "aspeed,ast2500-video-engine";
306 reg = <0x1e700000 0x1000>;
307 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
308 <&syscon ASPEED_CLK_GATE_ECLK>;
309 clock-names = "vclk", "eclk";
314 sram: sram@1e720000 {
315 compatible = "mmio-sram";
316 reg = <0x1e720000 0x9000>; // 36K
319 sdmmc: sd-controller@1e740000 {
320 compatible = "aspeed,ast2500-sd-controller";
321 reg = <0x1e740000 0x100>;
322 #address-cells = <1>;
324 ranges = <0 0x1e740000 0x10000>;
325 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
329 compatible = "aspeed,ast2500-sdhci";
333 clocks = <&syscon ASPEED_CLK_SDIO>;
338 compatible = "aspeed,ast2500-sdhci";
342 clocks = <&syscon ASPEED_CLK_SDIO>;
347 gpio: gpio@1e780000 {
350 compatible = "aspeed,ast2500-gpio";
351 reg = <0x1e780000 0x200>;
353 gpio-ranges = <&pinctrl 0 0 232>;
354 clocks = <&syscon ASPEED_CLK_APB>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
359 sgpio: sgpio@1e780200 {
361 compatible = "aspeed,ast2500-sgpio";
364 reg = <0x1e780200 0x0100>;
365 clocks = <&syscon ASPEED_CLK_APB>;
366 #interrupt-cells = <2>;
367 interrupt-controller;
368 bus-frequency = <12000000>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_sgpm_default>;
375 compatible = "aspeed,ast2500-rtc";
376 reg = <0x1e781000 0x18>;
380 timer: timer@1e782000 {
381 /* This timer is a Faraday FTTMR010 derivative */
382 compatible = "aspeed,ast2400-timer";
383 reg = <0x1e782000 0x90>;
384 interrupts = <16 17 18 35 36 37 38 39>;
385 clocks = <&syscon ASPEED_CLK_APB>;
386 clock-names = "PCLK";
389 uart1: serial@1e783000 {
390 compatible = "ns16550a";
391 reg = <0x1e783000 0x20>;
394 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
395 resets = <&lpc_reset 4>;
400 uart5: serial@1e784000 {
401 compatible = "ns16550a";
402 reg = <0x1e784000 0x20>;
405 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
410 wdt1: watchdog@1e785000 {
411 compatible = "aspeed,ast2500-wdt";
412 reg = <0x1e785000 0x20>;
413 clocks = <&syscon ASPEED_CLK_APB>;
416 wdt2: watchdog@1e785020 {
417 compatible = "aspeed,ast2500-wdt";
418 reg = <0x1e785020 0x20>;
419 clocks = <&syscon ASPEED_CLK_APB>;
422 wdt3: watchdog@1e785040 {
423 compatible = "aspeed,ast2500-wdt";
424 reg = <0x1e785040 0x20>;
425 clocks = <&syscon ASPEED_CLK_APB>;
429 pwm_tacho: pwm-tacho-controller@1e786000 {
430 compatible = "aspeed,ast2500-pwm-tacho";
431 #address-cells = <1>;
433 reg = <0x1e786000 0x1000>;
434 clocks = <&syscon ASPEED_CLK_24M>;
435 resets = <&syscon ASPEED_RESET_PWM>;
439 vuart: serial@1e787000 {
440 compatible = "aspeed,ast2500-vuart";
441 reg = <0x1e787000 0x40>;
444 clocks = <&syscon ASPEED_CLK_APB>;
450 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
451 reg = <0x1e789000 0x1000>;
454 #address-cells = <1>;
456 ranges = <0x0 0x1e789000 0x1000>;
459 compatible = "aspeed,ast2500-kcs-bmc-v2";
460 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
462 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
467 compatible = "aspeed,ast2500-kcs-bmc-v2";
468 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
470 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
475 compatible = "aspeed,ast2500-kcs-bmc-v2";
476 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
478 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
483 compatible = "aspeed,ast2500-kcs-bmc-v2";
484 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
486 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
490 lpc_ctrl: lpc-ctrl@80 {
491 compatible = "aspeed,ast2500-lpc-ctrl";
493 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
497 lpc_snoop: lpc-snoop@90 {
498 compatible = "aspeed,ast2500-lpc-snoop";
501 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
505 lpc_reset: reset-controller@98 {
506 compatible = "aspeed,ast2500-lpc-reset";
511 uart_routing: uart-routing@9c {
512 compatible = "aspeed,ast2500-uart-routing";
518 compatible = "aspeed,ast2500-lhc";
519 reg = <0xa0 0x24 0xc8 0x8>;
524 compatible = "aspeed,ast2500-ibt-bmc";
527 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
532 peci0: peci-controller@1e78b000 {
533 compatible = "aspeed,ast2500-peci";
534 reg = <0x1e78b000 0x60>;
536 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
537 resets = <&syscon ASPEED_RESET_PECI>;
538 cmd-timeout-ms = <1000>;
539 clock-frequency = <1000000>;
543 uart2: serial@1e78d000 {
544 compatible = "ns16550a";
545 reg = <0x1e78d000 0x20>;
548 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
549 resets = <&lpc_reset 5>;
554 uart3: serial@1e78e000 {
555 compatible = "ns16550a";
556 reg = <0x1e78e000 0x20>;
559 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
560 resets = <&lpc_reset 6>;
565 uart4: serial@1e78f000 {
566 compatible = "ns16550a";
567 reg = <0x1e78f000 0x20>;
570 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
571 resets = <&lpc_reset 7>;
577 compatible = "simple-bus";
578 #address-cells = <1>;
580 ranges = <0 0x1e78a000 0x1000>;
587 i2c_ic: interrupt-controller@0 {
588 #interrupt-cells = <1>;
589 compatible = "aspeed,ast2500-i2c-ic";
592 interrupt-controller;
596 #address-cells = <1>;
600 compatible = "aspeed,ast2500-i2c-bus";
601 clocks = <&syscon ASPEED_CLK_APB>;
602 resets = <&syscon ASPEED_RESET_I2C>;
603 bus-frequency = <100000>;
605 interrupt-parent = <&i2c_ic>;
607 /* Does not need pinctrl properties */
611 #address-cells = <1>;
615 compatible = "aspeed,ast2500-i2c-bus";
616 clocks = <&syscon ASPEED_CLK_APB>;
617 resets = <&syscon ASPEED_RESET_I2C>;
618 bus-frequency = <100000>;
620 interrupt-parent = <&i2c_ic>;
622 /* Does not need pinctrl properties */
626 #address-cells = <1>;
630 compatible = "aspeed,ast2500-i2c-bus";
631 clocks = <&syscon ASPEED_CLK_APB>;
632 resets = <&syscon ASPEED_RESET_I2C>;
633 bus-frequency = <100000>;
635 interrupt-parent = <&i2c_ic>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_i2c3_default>;
642 #address-cells = <1>;
646 compatible = "aspeed,ast2500-i2c-bus";
647 clocks = <&syscon ASPEED_CLK_APB>;
648 resets = <&syscon ASPEED_RESET_I2C>;
649 bus-frequency = <100000>;
651 interrupt-parent = <&i2c_ic>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_i2c4_default>;
658 #address-cells = <1>;
662 compatible = "aspeed,ast2500-i2c-bus";
663 clocks = <&syscon ASPEED_CLK_APB>;
664 resets = <&syscon ASPEED_RESET_I2C>;
665 bus-frequency = <100000>;
667 interrupt-parent = <&i2c_ic>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_i2c5_default>;
674 #address-cells = <1>;
678 compatible = "aspeed,ast2500-i2c-bus";
679 clocks = <&syscon ASPEED_CLK_APB>;
680 resets = <&syscon ASPEED_RESET_I2C>;
681 bus-frequency = <100000>;
683 interrupt-parent = <&i2c_ic>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&pinctrl_i2c6_default>;
690 #address-cells = <1>;
694 compatible = "aspeed,ast2500-i2c-bus";
695 clocks = <&syscon ASPEED_CLK_APB>;
696 resets = <&syscon ASPEED_RESET_I2C>;
697 bus-frequency = <100000>;
699 interrupt-parent = <&i2c_ic>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_i2c7_default>;
706 #address-cells = <1>;
710 compatible = "aspeed,ast2500-i2c-bus";
711 clocks = <&syscon ASPEED_CLK_APB>;
712 resets = <&syscon ASPEED_RESET_I2C>;
713 bus-frequency = <100000>;
715 interrupt-parent = <&i2c_ic>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_i2c8_default>;
722 #address-cells = <1>;
726 compatible = "aspeed,ast2500-i2c-bus";
727 clocks = <&syscon ASPEED_CLK_APB>;
728 resets = <&syscon ASPEED_RESET_I2C>;
729 bus-frequency = <100000>;
731 interrupt-parent = <&i2c_ic>;
732 pinctrl-names = "default";
733 pinctrl-0 = <&pinctrl_i2c9_default>;
738 #address-cells = <1>;
742 compatible = "aspeed,ast2500-i2c-bus";
743 clocks = <&syscon ASPEED_CLK_APB>;
744 resets = <&syscon ASPEED_RESET_I2C>;
745 bus-frequency = <100000>;
747 interrupt-parent = <&i2c_ic>;
748 pinctrl-names = "default";
749 pinctrl-0 = <&pinctrl_i2c10_default>;
754 #address-cells = <1>;
758 compatible = "aspeed,ast2500-i2c-bus";
759 clocks = <&syscon ASPEED_CLK_APB>;
760 resets = <&syscon ASPEED_RESET_I2C>;
761 bus-frequency = <100000>;
763 interrupt-parent = <&i2c_ic>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_i2c11_default>;
770 #address-cells = <1>;
774 compatible = "aspeed,ast2500-i2c-bus";
775 clocks = <&syscon ASPEED_CLK_APB>;
776 resets = <&syscon ASPEED_RESET_I2C>;
777 bus-frequency = <100000>;
779 interrupt-parent = <&i2c_ic>;
780 pinctrl-names = "default";
781 pinctrl-0 = <&pinctrl_i2c12_default>;
786 #address-cells = <1>;
790 compatible = "aspeed,ast2500-i2c-bus";
791 clocks = <&syscon ASPEED_CLK_APB>;
792 resets = <&syscon ASPEED_RESET_I2C>;
793 bus-frequency = <100000>;
795 interrupt-parent = <&i2c_ic>;
796 pinctrl-names = "default";
797 pinctrl-0 = <&pinctrl_i2c13_default>;
802 #address-cells = <1>;
806 compatible = "aspeed,ast2500-i2c-bus";
807 clocks = <&syscon ASPEED_CLK_APB>;
808 resets = <&syscon ASPEED_RESET_I2C>;
809 bus-frequency = <100000>;
811 interrupt-parent = <&i2c_ic>;
812 pinctrl-names = "default";
813 pinctrl-0 = <&pinctrl_i2c14_default>;
819 pinctrl_acpi_default: acpi_default {
824 pinctrl_adc0_default: adc0_default {
829 pinctrl_adc1_default: adc1_default {
834 pinctrl_adc10_default: adc10_default {
839 pinctrl_adc11_default: adc11_default {
844 pinctrl_adc12_default: adc12_default {
849 pinctrl_adc13_default: adc13_default {
854 pinctrl_adc14_default: adc14_default {
859 pinctrl_adc15_default: adc15_default {
864 pinctrl_adc2_default: adc2_default {
869 pinctrl_adc3_default: adc3_default {
874 pinctrl_adc4_default: adc4_default {
879 pinctrl_adc5_default: adc5_default {
884 pinctrl_adc6_default: adc6_default {
889 pinctrl_adc7_default: adc7_default {
894 pinctrl_adc8_default: adc8_default {
899 pinctrl_adc9_default: adc9_default {
904 pinctrl_bmcint_default: bmcint_default {
909 pinctrl_ddcclk_default: ddcclk_default {
914 pinctrl_ddcdat_default: ddcdat_default {
919 pinctrl_espi_default: espi_default {
924 pinctrl_fwspics1_default: fwspics1_default {
925 function = "FWSPICS1";
929 pinctrl_fwspics2_default: fwspics2_default {
930 function = "FWSPICS2";
934 pinctrl_gpid0_default: gpid0_default {
939 pinctrl_gpid2_default: gpid2_default {
944 pinctrl_gpid4_default: gpid4_default {
949 pinctrl_gpid6_default: gpid6_default {
954 pinctrl_gpie0_default: gpie0_default {
959 pinctrl_gpie2_default: gpie2_default {
964 pinctrl_gpie4_default: gpie4_default {
969 pinctrl_gpie6_default: gpie6_default {
974 pinctrl_i2c10_default: i2c10_default {
979 pinctrl_i2c11_default: i2c11_default {
984 pinctrl_i2c12_default: i2c12_default {
989 pinctrl_i2c13_default: i2c13_default {
994 pinctrl_i2c14_default: i2c14_default {
999 pinctrl_i2c3_default: i2c3_default {
1004 pinctrl_i2c4_default: i2c4_default {
1009 pinctrl_i2c5_default: i2c5_default {
1014 pinctrl_i2c6_default: i2c6_default {
1019 pinctrl_i2c7_default: i2c7_default {
1024 pinctrl_i2c8_default: i2c8_default {
1029 pinctrl_i2c9_default: i2c9_default {
1034 pinctrl_lad0_default: lad0_default {
1039 pinctrl_lad1_default: lad1_default {
1044 pinctrl_lad2_default: lad2_default {
1049 pinctrl_lad3_default: lad3_default {
1054 pinctrl_lclk_default: lclk_default {
1059 pinctrl_lframe_default: lframe_default {
1060 function = "LFRAME";
1064 pinctrl_lpchc_default: lpchc_default {
1069 pinctrl_lpcpd_default: lpcpd_default {
1074 pinctrl_lpcplus_default: lpcplus_default {
1075 function = "LPCPLUS";
1079 pinctrl_lpcpme_default: lpcpme_default {
1080 function = "LPCPME";
1084 pinctrl_lpcrst_default: lpcrst_default {
1085 function = "LPCRST";
1089 pinctrl_lpcsmi_default: lpcsmi_default {
1090 function = "LPCSMI";
1094 pinctrl_lsirq_default: lsirq_default {
1099 pinctrl_mac1link_default: mac1link_default {
1100 function = "MAC1LINK";
1101 groups = "MAC1LINK";
1104 pinctrl_mac2link_default: mac2link_default {
1105 function = "MAC2LINK";
1106 groups = "MAC2LINK";
1109 pinctrl_mdio1_default: mdio1_default {
1114 pinctrl_mdio2_default: mdio2_default {
1119 pinctrl_ncts1_default: ncts1_default {
1124 pinctrl_ncts2_default: ncts2_default {
1129 pinctrl_ncts3_default: ncts3_default {
1134 pinctrl_ncts4_default: ncts4_default {
1139 pinctrl_ndcd1_default: ndcd1_default {
1144 pinctrl_ndcd2_default: ndcd2_default {
1149 pinctrl_ndcd3_default: ndcd3_default {
1154 pinctrl_ndcd4_default: ndcd4_default {
1159 pinctrl_ndsr1_default: ndsr1_default {
1164 pinctrl_ndsr2_default: ndsr2_default {
1169 pinctrl_ndsr3_default: ndsr3_default {
1174 pinctrl_ndsr4_default: ndsr4_default {
1179 pinctrl_ndtr1_default: ndtr1_default {
1184 pinctrl_ndtr2_default: ndtr2_default {
1189 pinctrl_ndtr3_default: ndtr3_default {
1194 pinctrl_ndtr4_default: ndtr4_default {
1199 pinctrl_nri1_default: nri1_default {
1204 pinctrl_nri2_default: nri2_default {
1209 pinctrl_nri3_default: nri3_default {
1214 pinctrl_nri4_default: nri4_default {
1219 pinctrl_nrts1_default: nrts1_default {
1224 pinctrl_nrts2_default: nrts2_default {
1229 pinctrl_nrts3_default: nrts3_default {
1234 pinctrl_nrts4_default: nrts4_default {
1239 pinctrl_oscclk_default: oscclk_default {
1240 function = "OSCCLK";
1244 pinctrl_pewake_default: pewake_default {
1245 function = "PEWAKE";
1249 pinctrl_pnor_default: pnor_default {
1254 pinctrl_pwm0_default: pwm0_default {
1259 pinctrl_pwm1_default: pwm1_default {
1264 pinctrl_pwm2_default: pwm2_default {
1269 pinctrl_pwm3_default: pwm3_default {
1274 pinctrl_pwm4_default: pwm4_default {
1279 pinctrl_pwm5_default: pwm5_default {
1284 pinctrl_pwm6_default: pwm6_default {
1289 pinctrl_pwm7_default: pwm7_default {
1294 pinctrl_rgmii1_default: rgmii1_default {
1295 function = "RGMII1";
1299 pinctrl_rgmii2_default: rgmii2_default {
1300 function = "RGMII2";
1304 pinctrl_rmii1_default: rmii1_default {
1309 pinctrl_rmii2_default: rmii2_default {
1314 pinctrl_rxd1_default: rxd1_default {
1319 pinctrl_rxd2_default: rxd2_default {
1324 pinctrl_rxd3_default: rxd3_default {
1329 pinctrl_rxd4_default: rxd4_default {
1334 pinctrl_salt1_default: salt1_default {
1339 pinctrl_salt10_default: salt10_default {
1340 function = "SALT10";
1344 pinctrl_salt11_default: salt11_default {
1345 function = "SALT11";
1349 pinctrl_salt12_default: salt12_default {
1350 function = "SALT12";
1354 pinctrl_salt13_default: salt13_default {
1355 function = "SALT13";
1359 pinctrl_salt14_default: salt14_default {
1360 function = "SALT14";
1364 pinctrl_salt2_default: salt2_default {
1369 pinctrl_salt3_default: salt3_default {
1374 pinctrl_salt4_default: salt4_default {
1379 pinctrl_salt5_default: salt5_default {
1384 pinctrl_salt6_default: salt6_default {
1389 pinctrl_salt7_default: salt7_default {
1394 pinctrl_salt8_default: salt8_default {
1399 pinctrl_salt9_default: salt9_default {
1404 pinctrl_scl1_default: scl1_default {
1409 pinctrl_scl2_default: scl2_default {
1414 pinctrl_sd1_default: sd1_default {
1419 pinctrl_sd2_default: sd2_default {
1424 pinctrl_sda1_default: sda1_default {
1429 pinctrl_sda2_default: sda2_default {
1434 pinctrl_sgpm_default: sgpm_default {
1439 pinctrl_sgps1_default: sgps1_default {
1444 pinctrl_sgps2_default: sgps2_default {
1449 pinctrl_sioonctrl_default: sioonctrl_default {
1450 function = "SIOONCTRL";
1451 groups = "SIOONCTRL";
1454 pinctrl_siopbi_default: siopbi_default {
1455 function = "SIOPBI";
1459 pinctrl_siopbo_default: siopbo_default {
1460 function = "SIOPBO";
1464 pinctrl_siopwreq_default: siopwreq_default {
1465 function = "SIOPWREQ";
1466 groups = "SIOPWREQ";
1469 pinctrl_siopwrgd_default: siopwrgd_default {
1470 function = "SIOPWRGD";
1471 groups = "SIOPWRGD";
1474 pinctrl_sios3_default: sios3_default {
1479 pinctrl_sios5_default: sios5_default {
1484 pinctrl_siosci_default: siosci_default {
1485 function = "SIOSCI";
1489 pinctrl_spi1_default: spi1_default {
1494 pinctrl_spi1cs1_default: spi1cs1_default {
1495 function = "SPI1CS1";
1499 pinctrl_spi1debug_default: spi1debug_default {
1500 function = "SPI1DEBUG";
1501 groups = "SPI1DEBUG";
1504 pinctrl_spi1passthru_default: spi1passthru_default {
1505 function = "SPI1PASSTHRU";
1506 groups = "SPI1PASSTHRU";
1509 pinctrl_spi2ck_default: spi2ck_default {
1510 function = "SPI2CK";
1514 pinctrl_spi2cs0_default: spi2cs0_default {
1515 function = "SPI2CS0";
1519 pinctrl_spi2cs1_default: spi2cs1_default {
1520 function = "SPI2CS1";
1524 pinctrl_spi2miso_default: spi2miso_default {
1525 function = "SPI2MISO";
1526 groups = "SPI2MISO";
1529 pinctrl_spi2mosi_default: spi2mosi_default {
1530 function = "SPI2MOSI";
1531 groups = "SPI2MOSI";
1534 pinctrl_timer3_default: timer3_default {
1535 function = "TIMER3";
1539 pinctrl_timer4_default: timer4_default {
1540 function = "TIMER4";
1544 pinctrl_timer5_default: timer5_default {
1545 function = "TIMER5";
1549 pinctrl_timer6_default: timer6_default {
1550 function = "TIMER6";
1554 pinctrl_timer7_default: timer7_default {
1555 function = "TIMER7";
1559 pinctrl_timer8_default: timer8_default {
1560 function = "TIMER8";
1564 pinctrl_txd1_default: txd1_default {
1569 pinctrl_txd2_default: txd2_default {
1574 pinctrl_txd3_default: txd3_default {
1579 pinctrl_txd4_default: txd4_default {
1584 pinctrl_uart6_default: uart6_default {
1589 pinctrl_usbcki_default: usbcki_default {
1590 function = "USBCKI";
1594 pinctrl_usb2ah_default: usb2ah_default {
1595 function = "USB2AH";
1599 pinctrl_usb2ad_default: usb2ad_default {
1600 function = "USB2AD";
1604 pinctrl_usb11bhid_default: usb11bhid_default {
1605 function = "USB11BHID";
1606 groups = "USB11BHID";
1609 pinctrl_usb2bh_default: usb2bh_default {
1610 function = "USB2BH";
1614 pinctrl_vgabiosrom_default: vgabiosrom_default {
1615 function = "VGABIOSROM";
1616 groups = "VGABIOSROM";
1619 pinctrl_vgahs_default: vgahs_default {
1624 pinctrl_vgavs_default: vgavs_default {
1629 pinctrl_vpi24_default: vpi24_default {
1634 pinctrl_vpo_default: vpo_default {
1639 pinctrl_wdtrst1_default: wdtrst1_default {
1640 function = "WDTRST1";
1644 pinctrl_wdtrst2_default: wdtrst2_default {
1645 function = "WDTRST2";