2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs.
16 #include "armada-xp.dtsi"
19 model = "Marvell Armada XP MV78260 SoC";
20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
32 enable-method = "marvell,armada-xp-smp";
36 compatible = "marvell,sheeva-v7";
43 compatible = "marvell,sheeva-v7";
51 * MV78260 has 3 PCIe units Gen2.0: Two units can be
52 * configured as x4 or quad x1 lanes. One unit is
56 compatible = "marvell,armada-xp-pcie";
64 bus-range = <0x00 0xff>;
67 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
68 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
69 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
70 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
71 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
72 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
73 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
74 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
75 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
76 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
77 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
78 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
79 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
80 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
81 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
82 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
83 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
85 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
86 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
87 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
88 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
89 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
90 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
91 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
92 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
94 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
95 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
99 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
100 reg = <0x0800 0 0 0 0>;
101 #address-cells = <3>;
103 #interrupt-cells = <1>;
104 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
105 0x81000000 0 0 0x81000000 0x1 0 1 0>;
106 interrupt-map-mask = <0 0 0 0>;
107 interrupt-map = <0 0 0 0 &mpic 58>;
108 marvell,pcie-port = <0>;
109 marvell,pcie-lane = <0>;
110 clocks = <&gateclk 5>;
116 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
117 reg = <0x1000 0 0 0 0>;
118 #address-cells = <3>;
120 #interrupt-cells = <1>;
121 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
122 0x81000000 0 0 0x81000000 0x2 0 1 0>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 59>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <1>;
127 clocks = <&gateclk 6>;
133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
134 reg = <0x1800 0 0 0 0>;
135 #address-cells = <3>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
139 0x81000000 0 0 0x81000000 0x3 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 60>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <2>;
144 clocks = <&gateclk 7>;
150 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
151 reg = <0x2000 0 0 0 0>;
152 #address-cells = <3>;
154 #interrupt-cells = <1>;
155 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
156 0x81000000 0 0 0x81000000 0x4 0 1 0>;
157 interrupt-map-mask = <0 0 0 0>;
158 interrupt-map = <0 0 0 0 &mpic 61>;
159 marvell,pcie-port = <0>;
160 marvell,pcie-lane = <3>;
161 clocks = <&gateclk 8>;
167 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
168 reg = <0x2800 0 0 0 0>;
169 #address-cells = <3>;
171 #interrupt-cells = <1>;
172 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
173 0x81000000 0 0 0x81000000 0x5 0 1 0>;
174 interrupt-map-mask = <0 0 0 0>;
175 interrupt-map = <0 0 0 0 &mpic 62>;
176 marvell,pcie-port = <1>;
177 marvell,pcie-lane = <0>;
178 clocks = <&gateclk 9>;
184 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
185 reg = <0x3000 0 0 0 0>;
186 #address-cells = <3>;
188 #interrupt-cells = <1>;
189 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
190 0x81000000 0 0 0x81000000 0x6 0 1 0>;
191 interrupt-map-mask = <0 0 0 0>;
192 interrupt-map = <0 0 0 0 &mpic 63>;
193 marvell,pcie-port = <1>;
194 marvell,pcie-lane = <1>;
195 clocks = <&gateclk 10>;
201 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
202 reg = <0x3800 0 0 0 0>;
203 #address-cells = <3>;
205 #interrupt-cells = <1>;
206 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
207 0x81000000 0 0 0x81000000 0x7 0 1 0>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 64>;
210 marvell,pcie-port = <1>;
211 marvell,pcie-lane = <2>;
212 clocks = <&gateclk 11>;
218 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
219 reg = <0x4000 0 0 0 0>;
220 #address-cells = <3>;
222 #interrupt-cells = <1>;
223 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
224 0x81000000 0 0 0x81000000 0x8 0 1 0>;
225 interrupt-map-mask = <0 0 0 0>;
226 interrupt-map = <0 0 0 0 &mpic 65>;
227 marvell,pcie-port = <1>;
228 marvell,pcie-lane = <3>;
229 clocks = <&gateclk 12>;
235 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
236 reg = <0x4800 0 0 0 0>;
237 #address-cells = <3>;
239 #interrupt-cells = <1>;
240 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
241 0x81000000 0 0 0x81000000 0x9 0 1 0>;
242 interrupt-map-mask = <0 0 0 0>;
243 interrupt-map = <0 0 0 0 &mpic 99>;
244 marvell,pcie-port = <2>;
245 marvell,pcie-lane = <0>;
246 clocks = <&gateclk 26>;
253 compatible = "marvell,mv78260-pinctrl";
254 reg = <0x18000 0x38>;
256 sdio_pins: sdio-pins {
257 marvell,pins = "mpp30", "mpp31", "mpp32",
258 "mpp33", "mpp34", "mpp35";
259 marvell,function = "sd0";
264 compatible = "marvell,orion-gpio";
265 reg = <0x18100 0x40>;
269 interrupt-controller;
270 #interrupt-cells = <2>;
271 interrupts = <82>, <83>, <84>, <85>;
275 compatible = "marvell,orion-gpio";
276 reg = <0x18140 0x40>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 interrupts = <87>, <88>, <89>, <90>;
286 compatible = "marvell,orion-gpio";
287 reg = <0x18180 0x40>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
296 eth3: ethernet@34000 {
297 compatible = "marvell,armada-370-neta";
298 reg = <0x34000 0x4000>;
300 clocks = <&gateclk 1>;