2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 * Copyright (C) 2014 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include "skeleton.dtsi"
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
19 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
22 model = "Marvell Armada 38x family SoC";
23 compatible = "marvell,armada380";
34 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
38 controller = <&mbusc>;
39 interrupt-parent = <&gic>;
40 pcie-mem-aperture = <0xe0000000 0x8000000>;
41 pcie-io-aperture = <0xe8000000 0x100000>;
44 compatible = "marvell,bootrom";
45 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
49 compatible = "marvell,mvebu-devbus";
50 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
51 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 clocks = <&coreclk 0>;
59 compatible = "marvell,mvebu-devbus";
60 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
61 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 clocks = <&coreclk 0>;
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 clocks = <&coreclk 0>;
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 clocks = <&coreclk 0>;
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 clocks = <&coreclk 0>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
102 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
104 L2: cache-controller@8000 {
105 compatible = "arm,pl310-cache";
106 reg = <0x8000 0x1000>;
112 compatible = "arm,cortex-a9-scu";
117 compatible = "arm,cortex-a9-twd-timer";
119 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
120 clocks = <&coreclk 2>;
123 gic: interrupt-controller@d000 {
124 compatible = "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
127 interrupt-controller;
128 reg = <0xd000 0x1000>,
133 compatible = "marvell,orion-spi";
134 reg = <0x10600 0x50>;
135 #address-cells = <1>;
138 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&coreclk 0>;
144 compatible = "marvell,orion-spi";
145 reg = <0x10680 0x50>;
146 #address-cells = <1>;
149 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&coreclk 0>;
155 compatible = "marvell,mv64xxx-i2c";
156 reg = <0x11000 0x20>;
157 #address-cells = <1>;
159 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&coreclk 0>;
166 compatible = "marvell,mv64xxx-i2c";
167 reg = <0x11100 0x20>;
168 #address-cells = <1>;
170 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&coreclk 0>;
177 compatible = "snps,dw-apb-uart";
178 reg = <0x12000 0x100>;
180 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&coreclk 0>;
187 compatible = "snps,dw-apb-uart";
188 reg = <0x12100 0x100>;
190 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&coreclk 0>;
197 compatible = "marvell,mv88f6820-pinctrl";
198 reg = <0x18000 0x20>;
202 compatible = "marvell,orion-gpio";
203 reg = <0x18100 0x40>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
216 compatible = "marvell,orion-gpio";
217 reg = <0x18140 0x40>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
229 system-controller@18200 {
230 compatible = "marvell,armada-380-system-controller",
231 "marvell,armada-370-xp-system-controller";
232 reg = <0x18200 0x100>;
235 gateclk: clock-gating-control@18220 {
236 compatible = "marvell,armada-380-gating-clock";
238 clocks = <&coreclk 0>;
242 coreclk: mvebu-sar@18600 {
243 compatible = "marvell,armada-380-core-clock";
244 reg = <0x18600 0x04>;
248 mbusc: mbus-controller@20000 {
249 compatible = "marvell,mbus-controller";
250 reg = <0x20000 0x100>, <0x20180 0x20>;
253 mpic: interrupt-controller@20000 {
254 compatible = "marvell,mpic";
255 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
256 #interrupt-cells = <1>;
258 interrupt-controller;
260 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
264 compatible = "marvell,armada-380-timer",
265 "marvell,armada-xp-timer";
266 reg = <0x20300 0x30>, <0x21040 0x30>;
267 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
268 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
269 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
270 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
273 clocks = <&coreclk 2>, <&refclk>;
274 clock-names = "nbclk", "fixed";
278 compatible = "marvell,armada-380-wdt";
279 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
280 clocks = <&coreclk 2>, <&refclk>;
281 clock-names = "nbclk", "fixed";
285 compatible = "marvell,armada-370-cpu-reset";
286 reg = <0x20800 0x10>;
289 coherency-fabric@21010 {
290 compatible = "marvell,armada-380-coherency-fabric";
291 reg = <0x21010 0x1c>;
295 compatible = "marvell,armada-380-pmsu";
296 reg = <0x22000 0x1000>;
299 eth1: ethernet@30000 {
300 compatible = "marvell,armada-370-neta";
301 reg = <0x30000 0x4000>;
302 interrupts-extended = <&mpic 10>;
303 clocks = <&gateclk 3>;
307 eth2: ethernet@34000 {
308 compatible = "marvell,armada-370-neta";
309 reg = <0x34000 0x4000>;
310 interrupts-extended = <&mpic 12>;
311 clocks = <&gateclk 2>;
316 compatible = "marvell,orion-ehci";
317 reg = <0x58000 0x500>;
318 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&gateclk 18>;
324 compatible = "marvell,orion-xor";
327 clocks = <&gateclk 22>;
331 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
336 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
344 compatible = "marvell,orion-xor";
347 clocks = <&gateclk 28>;
351 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
356 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
363 eth0: ethernet@70000 {
364 compatible = "marvell,armada-370-neta";
365 reg = <0x70000 0x4000>;
366 interrupts-extended = <&mpic 8>;
367 clocks = <&gateclk 4>;
372 #address-cells = <1>;
374 compatible = "marvell,orion-mdio";
376 clocks = <&gateclk 4>;
380 compatible = "marvell,armada-380-ahci";
381 reg = <0xa8000 0x2000>;
382 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&gateclk 15>;
388 compatible = "marvell,armada-380-ahci";
389 reg = <0xe0000 0x2000>;
390 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&gateclk 30>;
395 coredivclk: clock@e4250 {
396 compatible = "marvell,armada-380-corediv-clock";
400 clock-output-names = "nand";
404 compatible = "marvell,armada380-thermal";
405 reg = <0xe4078 0x4>, <0xe4074 0x4>;
410 compatible = "marvell,armada370-nand";
411 reg = <0xd0000 0x54>;
412 #address-cells = <1>;
414 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&coredivclk 0>;
420 compatible = "marvell,armada-380-sdhci";
421 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
422 interrupts = <0 25 0x4>;
423 clocks = <&gateclk 17>;
424 mrvl,clk-delay-cycles = <0x1F>;
429 compatible = "marvell,armada-380-xhci";
430 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
431 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&gateclk 9>;
437 compatible = "marvell,armada-380-xhci";
438 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
439 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&gateclk 10>;
447 /* 2 GHz fixed main PLL */
449 compatible = "fixed-clock";
451 clock-frequency = <2000000000>;
454 /* 25 MHz reference crystal */
456 compatible = "fixed-clock";
458 clock-frequency = <25000000>;