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9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
29 * (HBI0182 + HBI0183) as described in ARM DUI 0440B
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
37 enable-method = "arm,realview-smp";
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
57 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
64 compatible = "arm,pl310-cache";
65 reg = <0x1f002000 0x1000>;
69 * Override default cache size, sets and
70 * associativity as these may be erroneously set
71 * up by boot loader(s).
73 cache-size = <1048576>; // 1MB
75 cache-line-size = <32>;
77 arm,tag-latency = <1>;
78 arm,data-latency = <1 1>;
79 arm,dirty-latency = <1>;
83 compatible = "arm,cortex-a9-scu";
84 reg = <0x1f000000 0x100>;
87 twd_timer: timer@1f000600 {
88 compatible = "arm,cortex-a9-twd-timer";
89 reg = <0x1f000600 0x20>;
90 interrupt-parent = <&intc>;
91 interrupts = <1 13 0xf04>;
94 twd_wdog: watchdog@1f000620 {
95 compatible = "arm,cortex-a9-twd-wdt";
96 reg = <0x1f000620 0x20>;
97 interrupt-parent = <&intc>;
98 interrupts = <1 14 0xf04>;
102 compatible = "arm,cortex-a9-pmu";
103 interrupt-parent = <&intc>;
104 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
105 <0 45 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-affinity = <&CPU0>, <&CPU1>;
109 /* Primary GIC PL390 interrupt controller in the test chip */
110 intc: interrupt-controller@1f000000 {
111 compatible = "arm,cortex-a9-gic";
112 #interrupt-cells = <3>;
113 #address-cells = <1>;
114 interrupt-controller;
115 reg = <0x1f001000 0x1000>,
121 interrupt-parent = <&intc>;
122 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
126 interrupt-parent = <&intc>;
127 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-parent = <&intc>;
132 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
136 interrupt-parent = <&intc>;
137 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
141 interrupt-parent = <&intc>;
142 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-parent = <&intc>;
147 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-parent = <&intc>;
152 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-parent = <&intc>;
157 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-parent = <&intc>;
162 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-parent = <&intc>;
167 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-parent = <&intc>;
172 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-parent = <&intc>;
177 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-parent = <&intc>;
182 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-parent = <&intc>;
187 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-parent = <&intc>;
192 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
196 interrupt-parent = <&intc>;
197 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-parent = <&intc>;
202 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
206 interrupt-parent = <&intc>;
207 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-parent = <&intc>;
212 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
213 <0 18 IRQ_TYPE_LEVEL_HIGH>;
217 interrupt-parent = <&intc>;
218 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
222 interrupt-parent = <&intc>;
223 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
227 interrupt-parent = <&intc>;
228 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;