arch/arm/boot/dts/am33xx.dtsi

   1 /*
   2  * Device Tree Source for AM33XX SoC
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/bus/ti-sysc.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/pinctrl/am33xx.h>
  14 #include <dt-bindings/clock/am3.h>
  15
  16 / {
  17         compatible = "ti,am33xx";
  18         interrupt-parent = <&intc>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 serial4 = &uart4;
  32                 serial5 = &uart5;
  33                 d-can0 = &dcan0;
  34                 d-can1 = &dcan1;
  35                 usb0 = &usb0;
  36                 usb1 = &usb1;
  37                 phy0 = &usb0_phy;
  38                 phy1 = &usb1_phy;
  39                 ethernet0 = &cpsw_emac0;
  40                 ethernet1 = &cpsw_emac1;
  41                 spi0 = &spi0;
  42                 spi1 = &spi1;
  43         };
  44
  45         cpus {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 cpu@0 {
  49                         compatible = "arm,cortex-a8";
  50                         enable-method = "ti,am3352";
  51                         device_type = "cpu";
  52                         reg = <0>;
  53
  54                         operating-points-v2 = <&cpu0_opp_table>;
  55
  56                         clocks = <&dpll_mpu_ck>;
  57                         clock-names = "cpu";
  58
  59                         clock-latency = <300000>; /* From omap-cpufreq driver */
  60                         cpu-idle-states = <&mpu_gate>;
  61                 };
  62
  63                 idle-states {
  64                         mpu_gate: mpu_gate {
  65                                 compatible = "arm,idle-state";
  66                                 entry-latency-us = <40>;
  67                                 exit-latency-us = <90>;
  68                                 min-residency-us = <300>;
  69                                 ti,idle-wkup-m3;
  70                         };
  71                 };
  72         };
  73
  74         cpu0_opp_table: opp-table {
  75                 compatible = "operating-points-v2-ti-cpu";
  76                 syscon = <&scm_conf>;
  77
  78                 /*
  79                  * The three following nodes are marked with opp-suspend
  80                  * because the can not be enabled simultaneously on a
  81                  * single SoC.
  82                  */
  83                 opp50-300000000 {
  84                         opp-hz = /bits/ 64 <300000000>;
  85                         opp-microvolt = <950000 931000 969000>;
  86                         opp-supported-hw = <0x06 0x0010>;
  87                         opp-suspend;
  88                 };
  89
  90                 opp100-275000000 {
  91                         opp-hz = /bits/ 64 <275000000>;
  92                         opp-microvolt = <1100000 1078000 1122000>;
  93                         opp-supported-hw = <0x01 0x00FF>;
  94                         opp-suspend;
  95                 };
  96
  97                 opp100-300000000 {
  98                         opp-hz = /bits/ 64 <300000000>;
  99                         opp-microvolt = <1100000 1078000 1122000>;
 100                         opp-supported-hw = <0x06 0x0020>;
 101                         opp-suspend;
 102                 };
 103
 104                 opp100-500000000 {
 105                         opp-hz = /bits/ 64 <500000000>;
 106                         opp-microvolt = <1100000 1078000 1122000>;
 107                         opp-supported-hw = <0x01 0xFFFF>;
 108                 };
 109
 110                 opp100-600000000 {
 111                         opp-hz = /bits/ 64 <600000000>;
 112                         opp-microvolt = <1100000 1078000 1122000>;
 113                         opp-supported-hw = <0x06 0x0040>;
 114                 };
 115
 116                 opp120-600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <1200000 1176000 1224000>;
 119                         opp-supported-hw = <0x01 0xFFFF>;
 120                 };
 121
 122                 opp120-720000000 {
 123                         opp-hz = /bits/ 64 <720000000>;
 124                         opp-microvolt = <1200000 1176000 1224000>;
 125                         opp-supported-hw = <0x06 0x0080>;
 126                 };
 127
 128                 oppturbo-720000000 {
 129                         opp-hz = /bits/ 64 <720000000>;
 130                         opp-microvolt = <1260000 1234800 1285200>;
 131                         opp-supported-hw = <0x01 0xFFFF>;
 132                 };
 133
 134                 oppturbo-800000000 {
 135                         opp-hz = /bits/ 64 <800000000>;
 136                         opp-microvolt = <1260000 1234800 1285200>;
 137                         opp-supported-hw = <0x06 0x0100>;
 138                 };
 139
 140                 oppnitro-1000000000 {
 141                         opp-hz = /bits/ 64 <1000000000>;
 142                         opp-microvolt = <1325000 1298500 1351500>;
 143                         opp-supported-hw = <0x04 0x0200>;
 144                 };
 145         };
 146
 147         pmu@4b000000 {
 148                 compatible = "arm,cortex-a8-pmu";
 149                 interrupts = <3>;
 150                 reg = <0x4b000000 0x1000000>;
 151                 ti,hwmods = "debugss";
 152         };
 153
 154         /*
 155          * The soc node represents the soc top level view. It is used for IPs
 156          * that are not memory mapped in the MPU view or for the MPU itself.
 157          */
 158         soc {
 159                 compatible = "ti,omap-infra";
 160                 mpu {
 161                         compatible = "ti,omap3-mpu";
 162                         ti,hwmods = "mpu";
 163                         pm-sram = <&pm_sram_code
 164                                    &pm_sram_data>;
 165                 };
 166         };
 167
 168         /*
 169          * XXX: Use a flat representation of the AM33XX interconnect.
 170          * The real AM33XX interconnect network is quite complex. Since
 171          * it will not bring real advantage to represent that in DT
 172          * for the moment, just use a fake OCP bus entry to represent
 173          * the whole bus hierarchy.
 174          */
 175         ocp: ocp {
 176                 compatible = "simple-bus";
 177                 #address-cells = <1>;
 178                 #size-cells = <1>;
 179                 ranges;
 180                 ti,hwmods = "l3_main";
 181
 182                 l4_wkup: interconnect@44c00000 {
 183                 };
 184                 l4_per: interconnect@48000000 {
 185                 };
 186                 l4_fw: interconnect@47c00000 {
 187                 };
 188                 l4_fast: interconnect@4a000000 {
 189                 };
 190                 l4_mpuss: interconnect@4b140000 {
 191                 };
 192
 193                 intc: interrupt-controller@48200000 {
 194                         compatible = "ti,am33xx-intc";
 195                         interrupt-controller;
 196                         #interrupt-cells = <1>;
 197                         reg = <0x48200000 0x1000>;
 198                 };
 199
 200                 target-module@49000000 {
 201                         compatible = "ti,sysc-omap4", "ti,sysc";
 202                         reg = <0x49000000 0x4>;
 203                         reg-names = "rev";
 204                         clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
 205                         clock-names = "fck";
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208                         ranges = <0x0 0x49000000 0x10000>;
 209
 210                         edma: dma@0 {
 211                                 compatible = "ti,edma3-tpcc";
 212                                 reg = <0 0x10000>;
 213                                 reg-names = "edma3_cc";
 214                                 interrupts = <12 13 14>;
 215                                 interrupt-names = "edma3_ccint", "edma3_mperr",
 216                                                   "edma3_ccerrint";
 217                                 dma-requests = <64>;
 218                                 #dma-cells = <2>;
 219
 220                                 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
 221                                            <&edma_tptc2 0>;
 222
 223                                 ti,edma-memcpy-channels = <20 21>;
 224                         };
 225                 };
 226
 227                 target-module@49800000 {
 228                         compatible = "ti,sysc-omap4", "ti,sysc";
 229                         reg = <0x49800000 0x4>,
 230                               <0x49800010 0x4>;
 231                         reg-names = "rev", "sysc";
 232                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 233                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
 234                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 235                                         <SYSC_IDLE_SMART>;
 236                         clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
 237                         clock-names = "fck";
 238                         #address-cells = <1>;
 239                         #size-cells = <1>;
 240                         ranges = <0x0 0x49800000 0x100000>;
 241
 242                         edma_tptc0: dma@0 {
 243                                 compatible = "ti,edma3-tptc";
 244                                 reg = <0 0x100000>;
 245                                 interrupts = <112>;
 246                                 interrupt-names = "edma3_tcerrint";
 247                         };
 248                 };
 249
 250                 target-module@49900000 {
 251                         compatible = "ti,sysc-omap4", "ti,sysc";
 252                         reg = <0x49900000 0x4>,
 253                               <0x49900010 0x4>;
 254                         reg-names = "rev", "sysc";
 255                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 256                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
 257                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 258                                         <SYSC_IDLE_SMART>;
 259                         clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
 260                         clock-names = "fck";
 261                         #address-cells = <1>;
 262                         #size-cells = <1>;
 263                         ranges = <0x0 0x49900000 0x100000>;
 264
 265                         edma_tptc1: dma@0 {
 266                                 compatible = "ti,edma3-tptc";
 267                                 reg = <0 0x100000>;
 268                                 interrupts = <113>;
 269                                 interrupt-names = "edma3_tcerrint";
 270                         };
 271                 };
 272
 273                 target-module@49a00000 {
 274                         compatible = "ti,sysc-omap4", "ti,sysc";
 275                         reg = <0x49a00000 0x4>,
 276                               <0x49a00010 0x4>;
 277                         reg-names = "rev", "sysc";
 278                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 279                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
 280                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 281                                         <SYSC_IDLE_SMART>;
 282                         clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
 283                         clock-names = "fck";
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         ranges = <0x0 0x49a00000 0x100000>;
 287
 288                         edma_tptc2: dma@0 {
 289                                 compatible = "ti,edma3-tptc";
 290                                 reg = <0 0x100000>;
 291                                 interrupts = <114>;
 292                                 interrupt-names = "edma3_tcerrint";
 293                         };
 294                 };
 295
 296                 target-module@47810000 {
 297                         compatible = "ti,sysc-omap2", "ti,sysc";
 298                         reg = <0x478102fc 0x4>,
 299                               <0x47810110 0x4>,
 300                               <0x47810114 0x4>;
 301                         reg-names = "rev", "sysc", "syss";
 302                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 303                                          SYSC_OMAP2_ENAWAKEUP |
 304                                          SYSC_OMAP2_SOFTRESET |
 305                                          SYSC_OMAP2_AUTOIDLE)>;
 306                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 307                                         <SYSC_IDLE_NO>,
 308                                         <SYSC_IDLE_SMART>;
 309                         ti,syss-mask = <1>;
 310                         clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
 311                         clock-names = "fck";
 312                         #address-cells = <1>;
 313                         #size-cells = <1>;
 314                         ranges = <0x0 0x47810000 0x1000>;
 315
 316                         mmc3: mmc@0 {
 317                                 compatible = "ti,am335-sdhci";
 318                                 ti,needs-special-reset;
 319                                 interrupts = <29>;
 320                                 reg = <0x0 0x1000>;
 321                                 status = "disabled";
 322                         };
 323                 };
 324
 325                 usb: target-module@47400000 {
 326                         compatible = "ti,sysc-omap4", "ti,sysc";
 327                         reg = <0x47400000 0x4>,
 328                               <0x47400010 0x4>;
 329                         reg-names = "rev", "sysc";
 330                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 331                                          SYSC_OMAP4_SOFTRESET)>;
 332                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 333                                         <SYSC_IDLE_NO>,
 334                                         <SYSC_IDLE_SMART>;
 335                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 336                                         <SYSC_IDLE_NO>,
 337                                         <SYSC_IDLE_SMART>,
 338                                         <SYSC_IDLE_SMART_WKUP>;
 339                         clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
 340                         clock-names = "fck";
 341                         #address-cells = <1>;
 342                         #size-cells = <1>;
 343                         ranges = <0x0 0x47400000 0x8000>;
 344
 345                         usb0_phy: usb-phy@1300 {
 346                                 compatible = "ti,am335x-usb-phy";
 347                                 reg = <0x1300 0x100>;
 348                                 reg-names = "phy";
 349                                 ti,ctrl_mod = <&usb_ctrl_mod>;
 350                                 #phy-cells = <0>;
 351                         };
 352
 353                         usb0: usb@1400 {
 354                                 compatible = "ti,musb-am33xx";
 355                                 reg = <0x1400 0x400>,
 356                                       <0x1000 0x200>;
 357                                 reg-names = "mc", "control";
 358
 359                                 interrupts = <18>;
 360                                 interrupt-names = "mc";
 361                                 dr_mode = "otg";
 362                                 mentor,multipoint = <1>;
 363                                 mentor,num-eps = <16>;
 364                                 mentor,ram-bits = <12>;
 365                                 mentor,power = <500>;
 366                                 phys = <&usb0_phy>;
 367
 368                                 dmas = <&cppi41dma  0 0 &cppi41dma  1 0
 369                                         &cppi41dma  2 0 &cppi41dma  3 0
 370                                         &cppi41dma  4 0 &cppi41dma  5 0
 371                                         &cppi41dma  6 0 &cppi41dma  7 0
 372                                         &cppi41dma  8 0 &cppi41dma  9 0
 373                                         &cppi41dma 10 0 &cppi41dma 11 0
 374                                         &cppi41dma 12 0 &cppi41dma 13 0
 375                                         &cppi41dma 14 0 &cppi41dma  0 1
 376                                         &cppi41dma  1 1 &cppi41dma  2 1
 377                                         &cppi41dma  3 1 &cppi41dma  4 1
 378                                         &cppi41dma  5 1 &cppi41dma  6 1
 379                                         &cppi41dma  7 1 &cppi41dma  8 1
 380                                         &cppi41dma  9 1 &cppi41dma 10 1
 381                                         &cppi41dma 11 1 &cppi41dma 12 1
 382                                         &cppi41dma 13 1 &cppi41dma 14 1>;
 383                                 dma-names =
 384                                         "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
 385                                         "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
 386                                         "rx14", "rx15",
 387                                         "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
 388                                         "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
 389                                         "tx14", "tx15";
 390                         };
 391
 392                         usb1_phy: usb-phy@1b00 {
 393                                 compatible = "ti,am335x-usb-phy";
 394                                 reg = <0x1b00 0x100>;
 395                                 reg-names = "phy";
 396                                 ti,ctrl_mod = <&usb_ctrl_mod>;
 397                                 #phy-cells = <0>;
 398                         };
 399
 400                         usb1: usb@1800 {
 401                                 compatible = "ti,musb-am33xx";
 402                                 reg = <0x1c00 0x400>,
 403                                       <0x1800 0x200>;
 404                                 reg-names = "mc", "control";
 405                                 interrupts = <19>;
 406                                 interrupt-names = "mc";
 407                                 dr_mode = "otg";
 408                                 mentor,multipoint = <1>;
 409                                 mentor,num-eps = <16>;
 410                                 mentor,ram-bits = <12>;
 411                                 mentor,power = <500>;
 412                                 phys = <&usb1_phy>;
 413
 414                                 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
 415                                         &cppi41dma 17 0 &cppi41dma 18 0
 416                                         &cppi41dma 19 0 &cppi41dma 20 0
 417                                         &cppi41dma 21 0 &cppi41dma 22 0
 418                                         &cppi41dma 23 0 &cppi41dma 24 0
 419                                         &cppi41dma 25 0 &cppi41dma 26 0
 420                                         &cppi41dma 27 0 &cppi41dma 28 0
 421                                         &cppi41dma 29 0 &cppi41dma 15 1
 422                                         &cppi41dma 16 1 &cppi41dma 17 1
 423                                         &cppi41dma 18 1 &cppi41dma 19 1
 424                                         &cppi41dma 20 1 &cppi41dma 21 1
 425                                         &cppi41dma 22 1 &cppi41dma 23 1
 426                                         &cppi41dma 24 1 &cppi41dma 25 1
 427                                         &cppi41dma 26 1 &cppi41dma 27 1
 428                                         &cppi41dma 28 1 &cppi41dma 29 1>;
 429                                 dma-names =
 430                                         "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
 431                                         "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
 432                                         "rx14", "rx15",
 433                                         "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
 434                                         "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
 435                                         "tx14", "tx15";
 436                         };
 437
 438                         cppi41dma: dma-controller@2000 {
 439                                 compatible = "ti,am3359-cppi41";
 440                                 reg =  <0x0000 0x1000>,
 441                                        <0x2000 0x1000>,
 442                                        <0x3000 0x1000>,
 443                                        <0x4000 0x4000>;
 444                                 reg-names = "glue", "controller", "scheduler", "queuemgr";
 445                                 interrupts = <17>;
 446                                 interrupt-names = "glue";
 447                                 #dma-cells = <2>;
 448                                 #dma-channels = <30>;
 449                                 #dma-requests = <256>;
 450                         };
 451                 };
 452
 453                 ocmcram: sram@40300000 {
 454                         compatible = "mmio-sram";
 455                         reg = <0x40300000 0x10000>; /* 64k */
 456                         ranges = <0x0 0x40300000 0x10000>;
 457                         #address-cells = <1>;
 458                         #size-cells = <1>;
 459
 460                         pm_sram_code: pm-code-sram@0 {
 461                                 compatible = "ti,sram";
 462                                 reg = <0x0 0x1000>;
 463                                 protect-exec;
 464                         };
 465
 466                         pm_sram_data: pm-data-sram@1000 {
 467                                 compatible = "ti,sram";
 468                                 reg = <0x1000 0x1000>;
 469                                 pool;
 470                         };
 471                 };
 472
 473                 emif: emif@4c000000 {
 474                         compatible = "ti,emif-am3352";
 475                         reg = <0x4c000000 0x1000000>;
 476                         ti,hwmods = "emif";
 477                         interrupts = <101>;
 478                         sram = <&pm_sram_code
 479                                 &pm_sram_data>;
 480                         ti,no-idle;
 481                 };
 482
 483                 target-module@50000000 {
 484                         compatible = "ti,sysc-omap2", "ti,sysc";
 485                         reg = <0x50000000 4>,
 486                               <0x50000010 4>,
 487                               <0x50000014 4>;
 488                         reg-names = "rev", "sysc", "syss";
 489                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 490                                         <SYSC_IDLE_NO>,
 491                                         <SYSC_IDLE_SMART>;
 492                         ti,syss-mask = <1>;
 493                         clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
 494                         clock-names = "fck";
 495                         #address-cells = <1>;
 496                         #size-cells = <1>;
 497                         ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
 498                                  <0x00000000 0x00000000 0x40000000>; /* data */
 499
 500                         gpmc: gpmc@50000000 {
 501                                 compatible = "ti,am3352-gpmc";
 502                                 reg = <0x50000000 0x2000>;
 503                                 interrupts = <100>;
 504                                 dmas = <&edma 52 0>;
 505                                 dma-names = "rxtx";
 506                                 gpmc,num-cs = <7>;
 507                                 gpmc,num-waitpins = <2>;
 508                                 #address-cells = <2>;
 509                                 #size-cells = <1>;
 510                                 interrupt-controller;
 511                                 #interrupt-cells = <2>;
 512                                 gpio-controller;
 513                                 #gpio-cells = <2>;
 514                                 status = "disabled";
 515                         };
 516                 };
 517
 518                 sham_target: target-module@53100000 {
 519                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
 520                         reg = <0x53100100 0x4>,
 521                               <0x53100110 0x4>,
 522                               <0x53100114 0x4>;
 523                         reg-names = "rev", "sysc", "syss";
 524                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 525                                          SYSC_OMAP2_AUTOIDLE)>;
 526                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 527                                         <SYSC_IDLE_NO>,
 528                                         <SYSC_IDLE_SMART>;
 529                         ti,syss-mask = <1>;
 530                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 531                         clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
 532                         clock-names = "fck";
 533                         #address-cells = <1>;
 534                         #size-cells = <1>;
 535                         ranges = <0x0 0x53100000 0x1000>;
 536
 537                         sham: sham@0 {
 538                                 compatible = "ti,omap4-sham";
 539                                 reg = <0 0x200>;
 540                                 interrupts = <109>;
 541                                 dmas = <&edma 36 0>;
 542                                 dma-names = "rx";
 543                         };
 544                 };
 545
 546                 aes_target: target-module@53500000 {
 547                         compatible = "ti,sysc-omap2", "ti,sysc";
 548                         reg = <0x53500080 0x4>,
 549                               <0x53500084 0x4>,
 550                               <0x53500088 0x4>;
 551                         reg-names = "rev", "sysc", "syss";
 552                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 553                                          SYSC_OMAP2_AUTOIDLE)>;
 554                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 555                                         <SYSC_IDLE_NO>,
 556                                         <SYSC_IDLE_SMART>,
 557                                         <SYSC_IDLE_SMART_WKUP>;
 558                         ti,syss-mask = <1>;
 559                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 560                         clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
 561                         clock-names = "fck";
 562                         #address-cells = <1>;
 563                         #size-cells = <1>;
 564                         ranges = <0x0 0x53500000 0x1000>;
 565
 566                         aes: aes@0 {
 567                                 compatible = "ti,omap4-aes";
 568                                 reg = <0 0xa0>;
 569                                 interrupts = <103>;
 570                                 dmas = <&edma 6 0>,
 571                                        <&edma 5 0>;
 572                                 dma-names = "tx", "rx";
 573                         };
 574                 };
 575
 576                 target-module@56000000 {
 577                         compatible = "ti,sysc-omap4", "ti,sysc";
 578                         reg = <0x5600fe00 0x4>,
 579                               <0x5600fe10 0x4>;
 580                         reg-names = "rev", "sysc";
 581                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 582                                         <SYSC_IDLE_NO>,
 583                                         <SYSC_IDLE_SMART>;
 584                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 585                                         <SYSC_IDLE_NO>,
 586                                         <SYSC_IDLE_SMART>;
 587                         clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
 588                         clock-names = "fck";
 589                         power-domains = <&prm_gfx>;
 590                         resets = <&prm_gfx 0>;
 591                         reset-names = "rstctrl";
 592                         #address-cells = <1>;
 593                         #size-cells = <1>;
 594                         ranges = <0 0x56000000 0x1000000>;
 595
 596                         /*
 597                          * Closed source PowerVR driver, no child device
 598                          * binding or driver in mainline
 599                          */
 600                 };
 601         };
 602 };
 603
 604 #include "am33xx-l4.dtsi"
 605 #include "am33xx-clocks.dtsi"
 606
 607 &prcm {
 608         prm_per: prm@c00 {
 609                 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
 610                 reg = <0xc00 0x100>;
 611                 #reset-cells = <1>;
 612                 #power-domain-cells = <0>;
 613         };
 614
 615         prm_wkup: prm@d00 {
 616                 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
 617                 reg = <0xd00 0x100>;
 618                 #reset-cells = <1>;
 619                 #power-domain-cells = <0>;
 620         };
 621
 622         prm_mpu: prm@e00 {
 623                 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
 624                 reg = <0xe00 0x100>;
 625                 #power-domain-cells = <0>;
 626         };
 627
 628         prm_device: prm@f00 {
 629                 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
 630                 reg = <0xf00 0x100>;
 631                 #reset-cells = <1>;
 632         };
 633
 634         prm_rtc: prm@1000 {
 635                 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
 636                 reg = <0x1000 0x100>;
 637                 #power-domain-cells = <0>;
 638         };
 639
 640         prm_gfx: prm@1100 {
 641                 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
 642                 reg = <0x1100 0x100>;
 643                 #power-domain-cells = <0>;
 644                 #reset-cells = <1>;
 645         };
 646
 647         prm_cefuse: prm@1200 {
 648                 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
 649                 reg = <0x1200 0x100>;
 650                 #power-domain-cells = <0>;
 651         };
 652 };
 653
 654 /* Preferred always-on timer for clocksource */
 655 &timer1_target {
 656         clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
 657                  <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
 658         clock-names = "fck", "ick";
 659         ti,no-reset-on-init;
 660         ti,no-idle;
 661         timer@0 {
 662                 assigned-clocks = <&timer1_fck>;
 663                 assigned-clock-parents = <&sys_clkin_ck>;
 664         };
 665 };
 666
 667 /* Preferred timer for clockevent */
 668 &timer2_target {
 669         clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
 670                  <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
 671         clock-names = "fck", "ick";
 672         ti,no-reset-on-init;
 673         ti,no-idle;
 674         timer@0 {
 675                 assigned-clocks = <&timer2_fck>;
 676                 assigned-clock-parents = <&sys_clkin_ck>;
 677         };
 678 };