1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Phytec Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
8 #include <dt-bindings/interrupt-controller/irq.h>
11 model = "Phytec AM335x phyCORE";
12 compatible = "phytec,am335x-phycore-som", "ti,am33xx";
21 cpu0-supply = <&vdd1_reg>;
26 device_type = "memory";
27 reg = <0x80000000 0x10000000>; /* 256 MB */
31 compatible = "simple-bus";
33 vcc5v: fixedregulator0 {
34 compatible = "regulator-fixed";
35 regulator-name = "vcc5v";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
55 ethernet0_pins: pinmux_ethernet0 {
56 pinctrl-single,pins = <
57 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
58 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
59 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
60 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
61 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
62 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
63 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
64 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
68 mdio_pins: pinmux_mdio {
69 pinctrl-single,pins = <
71 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
72 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
80 dual_emac_res_vlan = <1>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&mdio_pins>;
88 phy0: ethernet-phy@0 {
95 pinctrl-names = "default";
96 pinctrl-0 = <ðernet0_pins>;
102 i2c0_pins: pinmux_i2c0 {
103 pinctrl-single,pins = <
104 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
105 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
111 pinctrl-names = "default";
112 pinctrl-0 = <&i2c0_pins>;
113 clock-frequency = <400000>;
120 i2c_tmp102: temp@4b {
121 compatible = "ti,tmp102";
126 i2c_eeprom: eeprom@52 {
127 compatible = "atmel,24c32";
134 compatible = "microcrystal,rv4162";
142 nandflash_pins: pinmux_nandflash {
143 pinctrl-single,pins = <
144 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
145 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
146 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
147 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
148 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
149 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
150 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
151 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
152 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
153 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
154 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
155 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
156 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
157 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
168 pinctrl-names = "default";
169 pinctrl-0 = <&nandflash_pins>;
170 ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
171 nandflash: nand@0,0 {
172 compatible = "ti,omap2-nand";
173 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
174 interrupt-parent = <&gpmc>;
175 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
176 <1 IRQ_TYPE_NONE>; /* termcount */
177 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
178 nand-bus-width = <8>;
179 ti,nand-ecc-opt = "bch8";
180 gpmc,device-nand = "true";
181 gpmc,device-width = <1>;
182 gpmc,sync-clk-ps = <0>;
184 gpmc,cs-rd-off-ns = <30>;
185 gpmc,cs-wr-off-ns = <30>;
186 gpmc,adv-on-ns = <0>;
187 gpmc,adv-rd-off-ns = <30>;
188 gpmc,adv-wr-off-ns = <30>;
190 gpmc,we-off-ns = <20>;
191 gpmc,oe-on-ns = <10>;
192 gpmc,oe-off-ns = <30>;
193 gpmc,access-ns = <30>;
194 gpmc,rd-cycle-ns = <30>;
195 gpmc,wr-cycle-ns = <30>;
196 gpmc,bus-turnaround-ns = <0>;
197 gpmc,cycle2cycle-delay-ns = <50>;
198 gpmc,cycle2cycle-diffcsen;
199 gpmc,clk-activation-ns = <0>;
200 gpmc,wr-access-ns = <30>;
201 gpmc,wr-data-mux-bus-ns = <0>;
205 #address-cells = <1>;
211 #include "tps65910.dtsi"
214 vcc1-supply = <&vcc5v>;
215 vcc2-supply = <&vcc5v>;
216 vcc3-supply = <&vcc5v>;
217 vcc4-supply = <&vcc5v>;
218 vcc5-supply = <&vcc5v>;
219 vcc6-supply = <&vcc5v>;
220 vcc7-supply = <&vcc5v>;
221 vccio-supply = <&vcc5v>;
224 vrtc_reg: regulator@0 {
228 vio_reg: regulator@1 {
232 vdd1_reg: regulator@2 {
233 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
234 regulator-name = "vdd_mpu";
235 regulator-min-microvolt = <912500>;
236 regulator-max-microvolt = <1378000>;
241 vdd2_reg: regulator@3 {
242 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
243 regulator-name = "vdd_core";
244 regulator-min-microvolt = <912500>;
245 regulator-max-microvolt = <1150000>;
250 vdd3_reg: regulator@4 {
254 vdig1_reg: regulator@5 {
255 regulator-name = "vdig1_1p8v";
256 regulator-min-microvolt = <1800000>;
257 regulator-max-microvolt = <1800000>;
260 vdig2_reg: regulator@6 {
264 vpll_reg: regulator@7 {
268 vdac_reg: regulator@8 {
272 vaux1_reg: regulator@9 {
276 vaux2_reg: regulator@10 {
280 vaux33_reg: regulator@11 {
284 vmmc_reg: regulator@12 {
285 regulator-min-microvolt = <3300000>;
286 regulator-max-microvolt = <3300000>;
294 spi0_pins: pinmux_spi0 {
295 pinctrl-single,pins = <
296 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
297 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
298 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
299 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
305 pinctrl-names = "default";
306 pinctrl-0 = <&spi0_pins>;
309 serial_flash: m25p80@0 {
310 compatible = "jedec,spi-nor";
311 spi-max-frequency = <48000000>;
315 #address-cells = <1>;