2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
25 .macro loadsp, rb, tmp
28 mcr p14, 0, \ch, c0, c5, 0
30 #elif defined(CONFIG_CPU_V7)
31 .macro loadsp, rb, tmp
34 wait: mrc p14, 0, pc, c0, c1, 0
36 mcr p14, 0, \ch, c0, c5, 0
38 #elif defined(CONFIG_CPU_XSCALE)
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c8, c0, 0
45 .macro loadsp, rb, tmp
48 mcr p14, 0, \ch, c1, c0, 0
54 #include <mach/debug-macro.S>
60 #if defined(CONFIG_ARCH_SA1100)
61 .macro loadsp, rb, tmp
62 mov \rb, #0x80000000 @ physical base address
63 #ifdef CONFIG_DEBUG_LL_SER3
64 add \rb, \rb, #0x00050000 @ Ser3
66 add \rb, \rb, #0x00010000 @ Ser1
69 #elif defined(CONFIG_ARCH_S3C2410)
70 .macro loadsp, rb, tmp
72 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
75 .macro loadsp, rb, tmp
93 .macro debug_reloc_start
96 kphex r6, 8 /* processor id */
98 kphex r7, 8 /* architecture id */
99 #ifdef CONFIG_CPU_CP15
101 mrc p15, 0, r0, c1, c0
102 kphex r0, 8 /* control reg */
105 kphex r5, 8 /* decompressed kernel start */
107 kphex r9, 8 /* decompressed kernel end */
109 kphex r4, 8 /* kernel execution address */
114 .macro debug_reloc_end
116 kphex r5, 8 /* end of kernel */
119 bl memdump /* dump 256 bytes at start of kernel */
123 .section ".start", #alloc, #execinstr
125 * sort out different calling conventions
129 .type start,#function
135 .word 0x016f2818 @ Magic numbers to help the loader
136 .word start @ absolute load/run zImage address
137 .word _edata @ zImage end address
138 1: mov r7, r1 @ save architecture ID
139 mov r8, r2 @ save atags pointer
141 #ifndef __ARM_ARCH_2__
143 * Booting from Angel - need to enter SVC mode and disable
144 * FIQs/IRQs (numeric definitions from angel arm.h source).
145 * We only do this if we were in user mode on entry.
147 mrs r2, cpsr @ get current mode
148 tst r2, #3 @ not user?
150 mov r0, #0x17 @ angel_SWIreason_EnterSVC
151 ARM( swi 0x123456 ) @ angel_SWI_ARM
152 THUMB( svc 0xab ) @ angel_SWI_THUMB
154 mrs r2, cpsr @ turn off interrupts to
155 orr r2, r2, #0xc0 @ prevent angel from running
158 teqp pc, #0x0c000003 @ turn off interrupts
162 * Note that some cache flushing and other stuff may
163 * be needed here - is there an Angel SWI call for this?
167 * some architecture specific code can be inserted
168 * by the linker here, but it should preserve r7, r8, and r9.
173 ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
174 THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} )
175 THUMB( ldr sp, [r0, #32] )
176 subs r0, r0, r1 @ calculate the delta offset
178 @ if delta is zero, we are
179 beq not_relocated @ running at the address we
183 * We're running at a different address. We need to fix
184 * up various pointers:
185 * r5 - zImage base address (_start)
186 * r6 - size of decompressed image
194 #ifndef CONFIG_ZBOOT_ROM
196 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
197 * we need to fix up pointers into the BSS region.
207 * Relocate all entries in the GOT table.
209 1: ldr r1, [r11, #0] @ relocate entries in the GOT
210 add r1, r1, r0 @ table. This fixes up the
211 str r1, [r11], #4 @ C references.
217 * Relocate entries in the GOT table. We only relocate
218 * the entries that are outside the (relocated) BSS region.
220 1: ldr r1, [r11, #0] @ relocate entries in the GOT
221 cmp r1, r2 @ entry < bss_start ||
222 cmphs r3, r1 @ _end < entry
223 addlo r1, r1, r0 @ table. This fixes up the
224 str r1, [r11], #4 @ C references.
229 not_relocated: mov r0, #0
230 1: str r0, [r2], #4 @ clear bss
238 * The C runtime environment should now be setup
239 * sufficiently. Turn the cache on, set up some
240 * pointers, and start decompressing.
244 mov r1, sp @ malloc space above stack
245 add r2, sp, #0x10000 @ 64k max
248 * Check to see if we will overwrite ourselves.
249 * r4 = final kernel address
250 * r5 = start of this image
251 * r6 = size of decompressed image
252 * r2 = end of malloc space (and therefore this image)
255 * r4 + image length <= r5 -> OK
263 mov r5, r2 @ decompress after malloc space
268 add r0, r0, #127 + 128 @ alignment + stack
269 bic r0, r0, #127 @ align the kernel length
271 * r0 = decompressed kernel length
273 * r4 = kernel execution address
274 * r5 = decompressed kernel start
275 * r7 = architecture ID
277 * r9-r12,r14 = corrupted
279 add r1, r5, r0 @ end of decompressed kernel
283 1: ldmia r2!, {r9 - r12, r14} @ copy relocation code
284 stmia r1!, {r9 - r12, r14}
285 ldmia r2!, {r9 - r12, r14}
286 stmia r1!, {r9 - r12, r14}
290 add sp, sp, #128 @ relocate the stack
293 ARM( add pc, r5, r0 ) @ call relocation code
294 THUMB( add r12, r5, r0 )
295 THUMB( mov pc, r12 ) @ call relocation code
298 * We're not in danger of overwriting ourselves. Do this the simple way.
300 * r4 = kernel execution address
301 * r7 = architecture ID
303 wont_overwrite: mov r0, r4
311 .word __bss_start @ r2
315 .word _image_size @ r6
316 .word _got_start @ r11
318 .word user_stack_end @ sp
319 LC1: .word reloc_end - reloc_start
322 #ifdef CONFIG_ARCH_RPC
324 params: ldr r0, =params_phys
331 * Turn on the cache. We need to setup some page tables so that we
332 * can have both the I and D caches on.
334 * We place the page tables 16k down from the kernel execution address,
335 * and we hope that nothing else is using it. If we're using it, we
339 * r4 = kernel execution address
340 * r7 = architecture number
343 * r0, r1, r2, r3, r9, r10, r12 corrupted
344 * This routine must preserve:
348 cache_on: mov r3, #8 @ cache_on function
352 * Initialize the highest priority protection region, PR7
353 * to cover all 32bit address and cacheable and bufferable.
355 __armv4_mpu_cache_on:
356 mov r0, #0x3f @ 4G, the whole
357 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
358 mcr p15, 0, r0, c6, c7, 1
361 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
362 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
363 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
366 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
367 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
370 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
371 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
372 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
373 mrc p15, 0, r0, c1, c0, 0 @ read control reg
374 @ ...I .... ..D. WC.M
375 orr r0, r0, #0x002d @ .... .... ..1. 11.1
376 orr r0, r0, #0x1000 @ ...1 .... .... ....
378 mcr p15, 0, r0, c1, c0, 0 @ write control reg
381 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
382 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
385 __armv3_mpu_cache_on:
386 mov r0, #0x3f @ 4G, the whole
387 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
390 mcr p15, 0, r0, c2, c0, 0 @ cache on
391 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
394 mcr p15, 0, r0, c5, c0, 0 @ access permission
397 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
399 * ?? ARMv3 MMU does not allow reading the control register,
400 * does this really work on ARMv3 MPU?
402 mrc p15, 0, r0, c1, c0, 0 @ read control reg
403 @ .... .... .... WC.M
404 orr r0, r0, #0x000d @ .... .... .... 11.1
405 /* ?? this overwrites the value constructed above? */
407 mcr p15, 0, r0, c1, c0, 0 @ write control reg
409 /* ?? invalidate for the second time? */
410 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
413 __setup_mmu: sub r3, r4, #16384 @ Page directory size
414 bic r3, r3, #0xff @ Align the pointer
417 * Initialise the page tables, turning on the cacheable and bufferable
418 * bits for the RAM area only.
422 mov r9, r9, lsl #18 @ start of RAM
423 add r10, r9, #0x10000000 @ a reasonable RAM size
427 1: cmp r1, r9 @ if virt > start of RAM
428 orrhs r1, r1, #0x0c @ set cacheable, bufferable
429 cmp r1, r10 @ if virt > end of RAM
430 bichs r1, r1, #0x0c @ clear cacheable, bufferable
431 str r1, [r0], #4 @ 1:1 mapping
436 * If ever we are running from Flash, then we surely want the cache
437 * to be enabled also for our execution instance... We map 2MB of it
438 * so there is no map overlap problem for up to 1 MB compressed kernel.
439 * If the execution is in RAM then we would only be duplicating the above.
444 orr r1, r1, r2, lsl #20
445 add r0, r3, r2, lsl #2
452 __armv4_mmu_cache_on:
457 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
458 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
459 mrc p15, 0, r0, c1, c0, 0 @ read control reg
460 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
462 #ifdef CONFIG_CPU_ENDIAN_BE8
463 orr r0, r0, #1 << 25 @ big-endian page tables
465 bl __common_mmu_cache_on
467 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
471 __armv7_mmu_cache_on:
474 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
478 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
480 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
482 mrc p15, 0, r0, c1, c0, 0 @ read control reg
483 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
484 orr r0, r0, #0x003c @ write buffer
486 #ifdef CONFIG_CPU_ENDIAN_BE8
487 orr r0, r0, #1 << 25 @ big-endian page tables
489 orrne r0, r0, #1 @ MMU enabled
491 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
492 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
494 mcr p15, 0, r0, c1, c0, 0 @ load control register
495 mrc p15, 0, r0, c1, c0, 0 @ and read it back
497 mcr p15, 0, r0, c7, c5, 4 @ ISB
504 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
505 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
506 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
507 mrc p15, 0, r0, c1, c0, 0 @ read control reg
508 orr r0, r0, #0x1000 @ I-cache enable
509 bl __common_mmu_cache_on
511 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
518 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
519 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
521 bl __common_mmu_cache_on
523 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
526 __common_mmu_cache_on:
527 #ifndef CONFIG_THUMB2_KERNEL
529 orr r0, r0, #0x000d @ Write buffer, mmu
532 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
533 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
535 .align 5 @ cache line aligned
536 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
537 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
538 sub pc, lr, r0, lsr #32 @ properly flush pipeline
542 * All code following this line is relocatable. It is relocated by
543 * the above code to the end of the decompressed kernel image and
544 * executed there. During this time, we have no stacks.
546 * r0 = decompressed kernel length
548 * r4 = kernel execution address
549 * r5 = decompressed kernel start
550 * r7 = architecture ID
552 * r9-r12,r14 = corrupted
555 reloc_start: add r9, r5, r0
556 sub r9, r9, #128 @ do not copy the stack
561 ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel
562 stmia r1!, {r0, r2, r3, r10 - r12, r14}
568 add sp, sp, #128 @ relocate the stack
571 call_kernel: bl cache_clean_flush
573 mov r0, #0 @ must be zero
574 mov r1, r7 @ restore architecture number
575 mov r2, r8 @ restore atags pointer
576 mov pc, r4 @ call kernel
579 * Here follow the relocatable cache support functions for the
580 * various processors. This is a generic hook for locating an
581 * entry and jumping to an instruction at the specified offset
582 * from the start of the block. Please note this is all position
592 call_cache_fn: adr r12, proc_types
593 #ifdef CONFIG_CPU_CP15
594 mrc p15, 0, r9, c0, c0 @ get processor ID
596 ldr r9, =CONFIG_PROCESSOR_ID
598 1: ldr r1, [r12, #0] @ get value
599 ldr r2, [r12, #4] @ get mask
600 eor r1, r1, r9 @ (real ^ match)
602 ARM( addeq pc, r12, r3 ) @ call cache function
603 THUMB( addeq r12, r3 )
604 THUMB( moveq pc, r12 ) @ call cache function
609 * Table for cache operations. This is basically:
612 * - 'cache on' method instruction
613 * - 'cache off' method instruction
614 * - 'cache flush' method instruction
616 * We match an entry using: ((real_id ^ match) & mask) == 0
618 * Writethrough caches generally only need 'on' and 'off'
619 * methods. Writeback caches _must_ have the flush method
623 .type proc_types,#object
625 .word 0x41560600 @ ARM6/610
627 W(b) __arm6_mmu_cache_off @ works, but slow
628 W(b) __arm6_mmu_cache_off
631 @ b __arm6_mmu_cache_on @ untested
632 @ b __arm6_mmu_cache_off
633 @ b __armv3_mmu_cache_flush
635 .word 0x00000000 @ old ARM ID
644 .word 0x41007000 @ ARM7/710
646 W(b) __arm7_mmu_cache_off
647 W(b) __arm7_mmu_cache_off
651 .word 0x41807200 @ ARM720T (writethrough)
653 W(b) __armv4_mmu_cache_on
654 W(b) __armv4_mmu_cache_off
658 .word 0x41007400 @ ARM74x
660 W(b) __armv3_mpu_cache_on
661 W(b) __armv3_mpu_cache_off
662 W(b) __armv3_mpu_cache_flush
664 .word 0x41009400 @ ARM94x
666 W(b) __armv4_mpu_cache_on
667 W(b) __armv4_mpu_cache_off
668 W(b) __armv4_mpu_cache_flush
670 .word 0x00007000 @ ARM7 IDs
679 @ Everything from here on will be the new ID system.
681 .word 0x4401a100 @ sa110 / sa1100
683 W(b) __armv4_mmu_cache_on
684 W(b) __armv4_mmu_cache_off
685 W(b) __armv4_mmu_cache_flush
687 .word 0x6901b110 @ sa1110
689 W(b) __armv4_mmu_cache_on
690 W(b) __armv4_mmu_cache_off
691 W(b) __armv4_mmu_cache_flush
694 .word 0xffffff00 @ PXA9xx
695 W(b) __armv4_mmu_cache_on
696 W(b) __armv4_mmu_cache_off
697 W(b) __armv4_mmu_cache_flush
699 .word 0x56158000 @ PXA168
701 W(b) __armv4_mmu_cache_on
702 W(b) __armv4_mmu_cache_off
703 W(b) __armv5tej_mmu_cache_flush
705 .word 0x56050000 @ Feroceon
707 W(b) __armv4_mmu_cache_on
708 W(b) __armv4_mmu_cache_off
709 W(b) __armv5tej_mmu_cache_flush
711 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
712 /* this conflicts with the standard ARMv5TE entry */
713 .long 0x41009260 @ Old Feroceon
715 b __armv4_mmu_cache_on
716 b __armv4_mmu_cache_off
717 b __armv5tej_mmu_cache_flush
720 .word 0x66015261 @ FA526
722 W(b) __fa526_cache_on
723 W(b) __armv4_mmu_cache_off
724 W(b) __fa526_cache_flush
726 @ These match on the architecture ID
728 .word 0x00020000 @ ARMv4T
730 W(b) __armv4_mmu_cache_on
731 W(b) __armv4_mmu_cache_off
732 W(b) __armv4_mmu_cache_flush
734 .word 0x00050000 @ ARMv5TE
736 W(b) __armv4_mmu_cache_on
737 W(b) __armv4_mmu_cache_off
738 W(b) __armv4_mmu_cache_flush
740 .word 0x00060000 @ ARMv5TEJ
742 W(b) __armv4_mmu_cache_on
743 W(b) __armv4_mmu_cache_off
744 W(b) __armv5tej_mmu_cache_flush
746 .word 0x0007b000 @ ARMv6
748 W(b) __armv4_mmu_cache_on
749 W(b) __armv4_mmu_cache_off
750 W(b) __armv6_mmu_cache_flush
752 .word 0x560f5810 @ Marvell PJ4 ARMv6
754 W(b) __armv4_mmu_cache_on
755 W(b) __armv4_mmu_cache_off
756 W(b) __armv6_mmu_cache_flush
758 .word 0x000f0000 @ new CPU Id
760 W(b) __armv7_mmu_cache_on
761 W(b) __armv7_mmu_cache_off
762 W(b) __armv7_mmu_cache_flush
764 .word 0 @ unrecognised type
773 .size proc_types, . - proc_types
776 * Turn off the Cache and MMU. ARMv3 does not support
777 * reading the control register, but ARMv4 does.
780 * r0, r1, r2, r3, r9, r12 corrupted
781 * This routine must preserve:
785 cache_off: mov r3, #12 @ cache_off function
788 __armv4_mpu_cache_off:
789 mrc p15, 0, r0, c1, c0
791 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
793 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
794 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
795 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
798 __armv3_mpu_cache_off:
799 mrc p15, 0, r0, c1, c0
801 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
803 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
806 __armv4_mmu_cache_off:
808 mrc p15, 0, r0, c1, c0
810 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
812 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
813 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
817 __armv7_mmu_cache_off:
818 mrc p15, 0, r0, c1, c0
824 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
826 bl __armv7_mmu_cache_flush
829 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
831 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
832 mcr p15, 0, r0, c7, c10, 4 @ DSB
833 mcr p15, 0, r0, c7, c5, 4 @ ISB
836 __arm6_mmu_cache_off:
837 mov r0, #0x00000030 @ ARM6 control reg.
838 b __armv3_mmu_cache_off
840 __arm7_mmu_cache_off:
841 mov r0, #0x00000070 @ ARM7 control reg.
842 b __armv3_mmu_cache_off
844 __armv3_mmu_cache_off:
845 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
847 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
848 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
852 * Clean and flush the cache to maintain consistency.
855 * r1, r2, r3, r9, r10, r11, r12 corrupted
856 * This routine must preserve:
864 __armv4_mpu_cache_flush:
867 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
868 mov r1, #7 << 5 @ 8 segments
869 1: orr r3, r1, #63 << 26 @ 64 entries
870 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
871 subs r3, r3, #1 << 26
872 bcs 2b @ entries 63 to 0
874 bcs 1b @ segments 7 to 0
877 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
878 mcr p15, 0, ip, c7, c10, 4 @ drain WB
883 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
884 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
885 mcr p15, 0, r1, c7, c10, 4 @ drain WB
888 __armv6_mmu_cache_flush:
890 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
891 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
892 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
893 mcr p15, 0, r1, c7, c10, 4 @ drain WB
896 __armv7_mmu_cache_flush:
897 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
898 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
901 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
904 mcr p15, 0, r10, c7, c10, 5 @ DMB
905 stmfd sp!, {r0-r7, r9-r11}
906 mrc p15, 1, r0, c0, c0, 1 @ read clidr
907 ands r3, r0, #0x7000000 @ extract loc from clidr
908 mov r3, r3, lsr #23 @ left align loc bit field
909 beq finished @ if loc is 0, then no need to clean
910 mov r10, #0 @ start clean at cache level 0
912 add r2, r10, r10, lsr #1 @ work out 3x current cache level
913 mov r1, r0, lsr r2 @ extract cache type bits from clidr
914 and r1, r1, #7 @ mask of the bits for current cache only
915 cmp r1, #2 @ see what cache we have at this level
916 blt skip @ skip if no cache, or just i-cache
917 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
918 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
919 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
920 and r2, r1, #7 @ extract the length of the cache lines
921 add r2, r2, #4 @ add 4 (line length offset)
923 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
924 clz r5, r4 @ find bit position of way size increment
926 ands r7, r7, r1, lsr #13 @ extract max number of the index size
928 mov r9, r4 @ create working copy of max way size
930 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
931 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
932 THUMB( lsl r6, r9, r5 )
933 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
934 THUMB( lsl r6, r7, r2 )
935 THUMB( orr r11, r11, r6 ) @ factor index number into r11
936 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
937 subs r9, r9, #1 @ decrement the way
939 subs r7, r7, #1 @ decrement the index
942 add r10, r10, #2 @ increment cache number
946 ldmfd sp!, {r0-r7, r9-r11}
947 mov r10, #0 @ swith back to cache level 0
948 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
950 mcr p15, 0, r10, c7, c10, 4 @ DSB
951 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
952 mcr p15, 0, r10, c7, c10, 4 @ DSB
953 mcr p15, 0, r10, c7, c5, 4 @ ISB
956 __armv5tej_mmu_cache_flush:
957 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
959 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
960 mcr p15, 0, r0, c7, c10, 4 @ drain WB
963 __armv4_mmu_cache_flush:
964 mov r2, #64*1024 @ default: 32K dcache size (*2)
965 mov r11, #32 @ default: 32 byte line size
966 mrc p15, 0, r3, c0, c0, 1 @ read cache type
967 teq r3, r9 @ cache ID register present?
972 mov r2, r2, lsl r1 @ base dcache size *2
973 tst r3, #1 << 14 @ test M bit
974 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
978 mov r11, r11, lsl r3 @ cache line size in bytes
981 bic r1, r1, #63 @ align to longest cache line
984 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
985 THUMB( ldr r3, [r1] ) @ s/w flush D cache
986 THUMB( add r1, r1, r11 )
990 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
991 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
992 mcr p15, 0, r1, c7, c10, 4 @ drain WB
995 __armv3_mmu_cache_flush:
996 __armv3_mpu_cache_flush:
998 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1002 * Various debugging routines for printing hex characters and
1003 * memory, which again must be relocatable.
1007 .type phexbuf,#object
1009 .size phexbuf, . - phexbuf
1011 @ phex corrupts {r0, r1, r2, r3}
1012 phex: adr r3, phexbuf
1026 @ puts corrupts {r0, r1, r2, r3}
1028 1: ldrb r2, [r0], #1
1041 @ putc corrupts {r0, r1, r2, r3}
1048 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1049 memdump: mov r12, r0
1052 2: mov r0, r11, lsl #2
1060 ldr r0, [r12, r11, lsl #2]
1082 .section ".stack", "w"
1083 user_stack: .space 4096