2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
15 #include "efi-header.S"
17 AR_CLASS( .arch armv7-a )
18 M_CLASS( .arch armv7-m )
23 * Note that these macros must not contain any code which is not
24 * 100% relocatable. Any attempt to do so will result in a crash.
25 * Please select one of the following when turning on debugging.
29 #if defined(CONFIG_DEBUG_ICEDCC)
31 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
32 .macro loadsp, rb, tmp1, tmp2
35 mcr p14, 0, \ch, c0, c5, 0
37 #elif defined(CONFIG_CPU_XSCALE)
38 .macro loadsp, rb, tmp1, tmp2
41 mcr p14, 0, \ch, c8, c0, 0
44 .macro loadsp, rb, tmp1, tmp2
47 mcr p14, 0, \ch, c1, c0, 0
53 #include CONFIG_DEBUG_LL_INCLUDE
59 #if defined(CONFIG_ARCH_SA1100)
60 .macro loadsp, rb, tmp1, tmp2
61 mov \rb, #0x80000000 @ physical base address
62 #ifdef CONFIG_DEBUG_LL_SER3
63 add \rb, \rb, #0x00050000 @ Ser3
65 add \rb, \rb, #0x00010000 @ Ser1
69 .macro loadsp, rb, tmp1, tmp2
70 addruart \rb, \tmp1, \tmp2
87 .macro debug_reloc_start
90 kphex r6, 8 /* processor id */
92 kphex r7, 8 /* architecture id */
93 #ifdef CONFIG_CPU_CP15
95 mrc p15, 0, r0, c1, c0
96 kphex r0, 8 /* control reg */
99 kphex r5, 8 /* decompressed kernel start */
101 kphex r9, 8 /* decompressed kernel end */
103 kphex r4, 8 /* kernel execution address */
108 .macro debug_reloc_end
110 kphex r5, 8 /* end of kernel */
113 bl memdump /* dump 256 bytes at start of kernel */
118 * Debug kernel copy by printing the memory addresses involved
120 .macro dbgkc, begin, end, cbegin, cend
127 kphex \begin, 8 /* Start of compressed kernel */
131 kphex \end, 8 /* End of compressed kernel */
136 kphex \cbegin, 8 /* Start of kernel copy */
140 kphex \cend, 8 /* End of kernel copy */
146 .section ".start", #alloc, #execinstr
148 * sort out different calling conventions
152 * Always enter in ARM state for CPUs that support the ARM ISA.
153 * As of today (2014) that's exactly the members of the A and R
158 .type start,#function
162 #ifndef CONFIG_THUMB2_KERNEL
165 AR_CLASS( sub pc, pc, #3 ) @ A/R: switch to Thumb2 mode
166 M_CLASS( nop.w ) @ M: already in Thumb2 mode
171 .word _magic_sig @ Magic numbers to help the loader
172 .word _magic_start @ absolute load/run zImage address
173 .word _magic_end @ zImage end address
174 .word 0x04030201 @ endianness flag
175 .word 0x45454545 @ another magic number to indicate
176 .word _magic_table @ additional data table
180 ARM_BE8( setend be ) @ go BE8 if compiled for BE8
181 AR_CLASS( mrs r9, cpsr )
182 #ifdef CONFIG_ARM_VIRT_EXT
183 bl __hyp_stub_install @ get into SVC mode, reversibly
185 mov r7, r1 @ save architecture ID
186 mov r8, r2 @ save atags pointer
188 #ifndef CONFIG_CPU_V7M
190 * Booting from Angel - need to enter SVC mode and disable
191 * FIQs/IRQs (numeric definitions from angel arm.h source).
192 * We only do this if we were in user mode on entry.
194 mrs r2, cpsr @ get current mode
195 tst r2, #3 @ not user?
197 mov r0, #0x17 @ angel_SWIreason_EnterSVC
198 ARM( swi 0x123456 ) @ angel_SWI_ARM
199 THUMB( svc 0xab ) @ angel_SWI_THUMB
201 safe_svcmode_maskall r0
202 msr spsr_cxsf, r9 @ Save the CPU boot mode in
206 * Note that some cache flushing and other stuff may
207 * be needed here - is there an Angel SWI call for this?
211 * some architecture specific code can be inserted
212 * by the linker here, but it should preserve r7, r8, and r9.
217 #ifdef CONFIG_AUTO_ZRELADDR
219 * Find the start of physical memory. As we are executing
220 * without the MMU on, we are in the physical address space.
221 * We just need to get rid of any offset by aligning the
224 * This alignment is a balance between the requirements of
225 * different platforms - we have chosen 128MB to allow
226 * platforms which align the start of their physical memory
227 * to 128MB to use this feature, while allowing the zImage
228 * to be placed within the first 128MB of memory on other
229 * platforms. Increasing the alignment means we place
230 * stricter alignment requirements on the start of physical
231 * memory, but relaxing it means that we break people who
232 * are already placing their zImage in (eg) the top 64MB
236 and r4, r4, #0xf8000000
237 /* Determine final kernel image address. */
238 add r4, r4, #TEXT_OFFSET
244 * Set up a page table only if it won't overwrite ourself.
245 * That means r4 < pc || r4 - 16k page directory > &_end.
246 * Given that r4 > &_end is most unfrequent, we add a rough
247 * additional 1MB of room for a possible appended DTB.
254 orrcc r4, r4, #1 @ remember we skipped cache_on
258 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
262 * We might be running at a different address. We need
263 * to fix up various pointers.
265 sub r0, r0, r1 @ calculate the delta offset
266 add r6, r6, r0 @ _edata
267 add r10, r10, r0 @ inflated kernel size location
270 * The kernel build system appends the size of the
271 * decompressed kernel at the end of the compressed data
272 * in little-endian form.
276 orr r9, r9, lr, lsl #8
279 orr r9, r9, lr, lsl #16
280 orr r9, r9, r10, lsl #24
282 #ifndef CONFIG_ZBOOT_ROM
283 /* malloc space is above the relocated stack (64k max) */
285 add r10, sp, #0x10000
288 * With ZBOOT_ROM the bss/stack is non relocatable,
289 * but someone could still run this code from RAM,
290 * in which case our reference is _edata.
295 mov r5, #0 @ init dtb size to 0
296 #ifdef CONFIG_ARM_APPENDED_DTB
301 * r4 = final kernel address (possibly with LSB set)
302 * r5 = appended dtb size (still unknown)
304 * r7 = architecture ID
305 * r8 = atags/device tree pointer
306 * r9 = size of decompressed image
307 * r10 = end of this image, including bss/stack/malloc space if non XIP
312 * if there are device trees (dtb) appended to zImage, advance r10 so that the
313 * dtb data will get relocated along with the kernel if necessary.
318 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
323 bne dtb_check_done @ not found
325 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
327 * OK... Let's do some funky business here.
328 * If we do have a DTB appended to zImage, and we do have
329 * an ATAG list around, we want the later to be translated
330 * and folded into the former here. No GOT fixup has occurred
331 * yet, but none of the code we're about to call uses any
335 /* Get the initial DTB size */
338 /* convert to little endian */
339 eor r1, r5, r5, ror #16
340 bic r1, r1, #0x00ff0000
342 eor r5, r5, r1, lsr #8
344 /* 50% DTB growth should be good enough */
345 add r5, r5, r5, lsr #1
346 /* preserve 64-bit alignment */
349 /* clamp to 32KB min and 1MB max */
354 /* temporarily relocate the stack past the DTB work space */
357 stmfd sp!, {r0-r3, ip, lr}
364 * If returned value is 1, there is no ATAG at the location
365 * pointed by r8. Try the typical 0x100 offset from start
366 * of RAM and hope for the best.
369 sub r0, r4, #TEXT_OFFSET
376 ldmfd sp!, {r0-r3, ip, lr}
380 mov r8, r6 @ use the appended device tree
383 * Make sure that the DTB doesn't end up in the final
384 * kernel's .bss area. To do so, we adjust the decompressed
385 * kernel size to compensate if that .bss size is larger
386 * than the relocated code.
388 ldr r5, =_kernel_bss_size
389 adr r1, wont_overwrite
394 /* Get the current DTB size */
397 /* convert r5 (dtb size) to little endian */
398 eor r1, r5, r5, ror #16
399 bic r1, r1, #0x00ff0000
401 eor r5, r5, r1, lsr #8
404 /* preserve 64-bit alignment */
408 /* relocate some pointers past the appended dtb */
416 * Check to see if we will overwrite ourselves.
417 * r4 = final kernel address (possibly with LSB set)
418 * r9 = size of decompressed image
419 * r10 = end of this image, including bss/stack/malloc space if non XIP
421 * r4 - 16k page directory >= r10 -> OK
422 * r4 + image length <= address of wont_overwrite -> OK
423 * Note: the possible LSB in r4 is harmless here.
429 adr r9, wont_overwrite
434 * Relocate ourselves past the end of the decompressed kernel.
436 * r10 = end of the decompressed kernel
437 * Because we always copy ahead, we need to do it from the end and go
438 * backward in case the source and destination overlap.
441 * Bump to the next 256-byte boundary with the size of
442 * the relocation code added. This avoids overwriting
443 * ourself when the offset is small.
445 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
448 /* Get start of code we want to copy and align it down. */
452 /* Relocate the hyp vector base if necessary */
453 #ifdef CONFIG_ARM_VIRT_EXT
455 and r0, r0, #MODE_MASK
460 * Compute the address of the hyp vectors after relocation.
461 * This requires some arithmetic since we cannot directly
462 * reference __hyp_stub_vectors in a PC-relative way.
463 * Call __hyp_set_vectors with the new address so that we
464 * can HVC again after the copy.
467 movw r1, #:lower16:__hyp_stub_vectors - 0b
468 movt r1, #:upper16:__hyp_stub_vectors - 0b
476 sub r9, r6, r5 @ size to copy
477 add r9, r9, #31 @ rounded up to a multiple
478 bic r9, r9, #31 @ ... of 32 bytes
486 * We are about to copy the kernel to a new memory area.
487 * The boundaries of the new memory area can be found in
488 * r10 and r9, whilst r5 and r6 contain the boundaries
489 * of the memory we are going to copy.
490 * Calling dbgkc will help with the printing of this
493 dbgkc r5, r6, r10, r9
496 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
498 stmdb r9!, {r0 - r3, r10 - r12, lr}
501 /* Preserve offset to relocated code. */
504 #ifndef CONFIG_ZBOOT_ROM
505 /* cache_clean_flush may use the stack, so relocate it */
517 * If delta is zero, we are running at the address we were linked at.
521 * r4 = kernel execution address (possibly with LSB set)
522 * r5 = appended dtb size (0 if not present)
523 * r7 = architecture ID
535 #ifndef CONFIG_ZBOOT_ROM
537 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
538 * we need to fix up pointers into the BSS region.
539 * Note that the stack pointer has already been fixed up.
545 * Relocate all entries in the GOT table.
546 * Bump bss entries to _edata + dtb size
548 1: ldr r1, [r11, #0] @ relocate entries in the GOT
549 add r1, r1, r0 @ This fixes up C references
550 cmp r1, r2 @ if entry >= bss_start &&
551 cmphs r3, r1 @ bss_end > entry
552 addhi r1, r1, r5 @ entry += dtb size
553 str r1, [r11], #4 @ next entry
557 /* bump our bss pointers too */
564 * Relocate entries in the GOT table. We only relocate
565 * the entries that are outside the (relocated) BSS region.
567 1: ldr r1, [r11, #0] @ relocate entries in the GOT
568 cmp r1, r2 @ entry < bss_start ||
569 cmphs r3, r1 @ _end < entry
570 addlo r1, r1, r0 @ table. This fixes up the
571 str r1, [r11], #4 @ C references.
576 not_relocated: mov r0, #0
577 1: str r0, [r2], #4 @ clear bss
585 * Did we skip the cache setup earlier?
586 * That is indicated by the LSB in r4.
594 * The C runtime environment should now be setup sufficiently.
595 * Set up some pointers, and start decompressing.
596 * r4 = kernel execution address
597 * r7 = architecture ID
601 mov r1, sp @ malloc space above stack
602 add r2, sp, #0x10000 @ 64k max
608 #ifdef CONFIG_ARM_VIRT_EXT
609 mrs r0, spsr @ Get saved CPU boot mode
610 and r0, r0, #MODE_MASK
611 cmp r0, #HYP_MODE @ if not booted in HYP mode...
612 bne __enter_kernel @ boot kernel directly
614 adr r12, .L__hyp_reentry_vectors_offset
619 __HVC(0) @ otherwise bounce to hyp mode
621 b . @ should never be reached
624 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
632 .word __bss_start @ r2
635 .word input_data_end - 4 @ r10 (inflated size location)
636 .word _got_start @ r11
638 .word .L_user_stack_end @ sp
639 .word _end - restart + 16384 + 1024*1024
642 #ifdef CONFIG_ARCH_RPC
644 params: ldr r0, =0x10000100 @ params_phys for RPC
651 * Turn on the cache. We need to setup some page tables so that we
652 * can have both the I and D caches on.
654 * We place the page tables 16k down from the kernel execution address,
655 * and we hope that nothing else is using it. If we're using it, we
659 * r4 = kernel execution address
660 * r7 = architecture number
663 * r0, r1, r2, r3, r9, r10, r12 corrupted
664 * This routine must preserve:
668 cache_on: mov r3, #8 @ cache_on function
672 * Initialize the highest priority protection region, PR7
673 * to cover all 32bit address and cacheable and bufferable.
675 __armv4_mpu_cache_on:
676 mov r0, #0x3f @ 4G, the whole
677 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
678 mcr p15, 0, r0, c6, c7, 1
681 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
682 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
683 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
686 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
687 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
690 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
691 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
692 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
693 mrc p15, 0, r0, c1, c0, 0 @ read control reg
694 @ ...I .... ..D. WC.M
695 orr r0, r0, #0x002d @ .... .... ..1. 11.1
696 orr r0, r0, #0x1000 @ ...1 .... .... ....
698 mcr p15, 0, r0, c1, c0, 0 @ write control reg
701 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
702 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
705 __armv3_mpu_cache_on:
706 mov r0, #0x3f @ 4G, the whole
707 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
710 mcr p15, 0, r0, c2, c0, 0 @ cache on
711 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
714 mcr p15, 0, r0, c5, c0, 0 @ access permission
717 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
719 * ?? ARMv3 MMU does not allow reading the control register,
720 * does this really work on ARMv3 MPU?
722 mrc p15, 0, r0, c1, c0, 0 @ read control reg
723 @ .... .... .... WC.M
724 orr r0, r0, #0x000d @ .... .... .... 11.1
725 /* ?? this overwrites the value constructed above? */
727 mcr p15, 0, r0, c1, c0, 0 @ write control reg
729 /* ?? invalidate for the second time? */
730 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
733 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
739 __setup_mmu: sub r3, r4, #16384 @ Page directory size
740 bic r3, r3, #0xff @ Align the pointer
743 * Initialise the page tables, turning on the cacheable and bufferable
744 * bits for the RAM area only.
748 mov r9, r9, lsl #18 @ start of RAM
749 add r10, r9, #0x10000000 @ a reasonable RAM size
750 mov r1, #0x12 @ XN|U + section mapping
751 orr r1, r1, #3 << 10 @ AP=11
753 1: cmp r1, r9 @ if virt > start of RAM
754 cmphs r10, r1 @ && end of RAM > virt
755 bic r1, r1, #0x1c @ clear XN|U + C + B
756 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
757 orrhs r1, r1, r6 @ set RAM section settings
758 str r1, [r0], #4 @ 1:1 mapping
763 * If ever we are running from Flash, then we surely want the cache
764 * to be enabled also for our execution instance... We map 2MB of it
765 * so there is no map overlap problem for up to 1 MB compressed kernel.
766 * If the execution is in RAM then we would only be duplicating the above.
768 orr r1, r6, #0x04 @ ensure B is set for this
772 orr r1, r1, r2, lsl #20
773 add r0, r3, r2, lsl #2
780 @ Enable unaligned access on v6, to allow better code generation
781 @ for the decompressor C code:
782 __armv6_mmu_cache_on:
783 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
784 bic r0, r0, #2 @ A (no unaligned access fault)
785 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
786 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
787 b __armv4_mmu_cache_on
789 __arm926ejs_mmu_cache_on:
790 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
791 mov r0, #4 @ put dcache in WT mode
792 mcr p15, 7, r0, c15, c0, 0
795 __armv4_mmu_cache_on:
798 mov r6, #CB_BITS | 0x12 @ U
801 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
802 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
803 mrc p15, 0, r0, c1, c0, 0 @ read control reg
804 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
806 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
807 bl __common_mmu_cache_on
809 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
813 __armv7_mmu_cache_on:
816 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
818 movne r6, #CB_BITS | 0x02 @ !XN
821 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
823 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
825 mrc p15, 0, r0, c1, c0, 0 @ read control reg
826 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
827 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
828 orr r0, r0, #0x003c @ write buffer
829 bic r0, r0, #2 @ A (no unaligned access fault)
830 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
831 @ (needed for ARM1176)
833 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
834 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
835 orrne r0, r0, #1 @ MMU enabled
836 movne r1, #0xfffffffd @ domain 0 = client
837 bic r6, r6, #1 << 31 @ 32-bit translation system
838 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
839 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
840 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
841 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
843 mcr p15, 0, r0, c7, c5, 4 @ ISB
844 mcr p15, 0, r0, c1, c0, 0 @ load control register
845 mrc p15, 0, r0, c1, c0, 0 @ and read it back
847 mcr p15, 0, r0, c7, c5, 4 @ ISB
852 mov r6, #CB_BITS | 0x12 @ U
855 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
856 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
857 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
858 mrc p15, 0, r0, c1, c0, 0 @ read control reg
859 orr r0, r0, #0x1000 @ I-cache enable
860 bl __common_mmu_cache_on
862 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
865 __common_mmu_cache_on:
866 #ifndef CONFIG_THUMB2_KERNEL
868 orr r0, r0, #0x000d @ Write buffer, mmu
871 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
872 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
874 .align 5 @ cache line aligned
875 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
876 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
877 sub pc, lr, r0, lsr #32 @ properly flush pipeline
880 #define PROC_ENTRY_SIZE (4*5)
883 * Here follow the relocatable cache support functions for the
884 * various processors. This is a generic hook for locating an
885 * entry and jumping to an instruction at the specified offset
886 * from the start of the block. Please note this is all position
896 call_cache_fn: adr r12, proc_types
897 #ifdef CONFIG_CPU_CP15
898 mrc p15, 0, r9, c0, c0 @ get processor ID
899 #elif defined(CONFIG_CPU_V7M)
901 * On v7-M the processor id is located in the V7M_SCB_CPUID
902 * register, but as cache handling is IMPLEMENTATION DEFINED on
903 * v7-M (if existant at all) we just return early here.
904 * If V7M_SCB_CPUID were used the cpu ID functions (i.e.
905 * __armv7_mmu_cache_{on,off,flush}) would be selected which
906 * use cp15 registers that are not implemented on v7-M.
910 ldr r9, =CONFIG_PROCESSOR_ID
912 1: ldr r1, [r12, #0] @ get value
913 ldr r2, [r12, #4] @ get mask
914 eor r1, r1, r9 @ (real ^ match)
916 ARM( addeq pc, r12, r3 ) @ call cache function
917 THUMB( addeq r12, r3 )
918 THUMB( moveq pc, r12 ) @ call cache function
919 add r12, r12, #PROC_ENTRY_SIZE
923 * Table for cache operations. This is basically:
926 * - 'cache on' method instruction
927 * - 'cache off' method instruction
928 * - 'cache flush' method instruction
930 * We match an entry using: ((real_id ^ match) & mask) == 0
932 * Writethrough caches generally only need 'on' and 'off'
933 * methods. Writeback caches _must_ have the flush method
937 .type proc_types,#object
939 .word 0x41000000 @ old ARM ID
948 .word 0x41007000 @ ARM7/710
957 .word 0x41807200 @ ARM720T (writethrough)
959 W(b) __armv4_mmu_cache_on
960 W(b) __armv4_mmu_cache_off
964 .word 0x41007400 @ ARM74x
966 W(b) __armv3_mpu_cache_on
967 W(b) __armv3_mpu_cache_off
968 W(b) __armv3_mpu_cache_flush
970 .word 0x41009400 @ ARM94x
972 W(b) __armv4_mpu_cache_on
973 W(b) __armv4_mpu_cache_off
974 W(b) __armv4_mpu_cache_flush
976 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
978 W(b) __arm926ejs_mmu_cache_on
979 W(b) __armv4_mmu_cache_off
980 W(b) __armv5tej_mmu_cache_flush
982 .word 0x00007000 @ ARM7 IDs
991 @ Everything from here on will be the new ID system.
993 .word 0x4401a100 @ sa110 / sa1100
995 W(b) __armv4_mmu_cache_on
996 W(b) __armv4_mmu_cache_off
997 W(b) __armv4_mmu_cache_flush
999 .word 0x6901b110 @ sa1110
1001 W(b) __armv4_mmu_cache_on
1002 W(b) __armv4_mmu_cache_off
1003 W(b) __armv4_mmu_cache_flush
1006 .word 0xffffff00 @ PXA9xx
1007 W(b) __armv4_mmu_cache_on
1008 W(b) __armv4_mmu_cache_off
1009 W(b) __armv4_mmu_cache_flush
1011 .word 0x56158000 @ PXA168
1013 W(b) __armv4_mmu_cache_on
1014 W(b) __armv4_mmu_cache_off
1015 W(b) __armv5tej_mmu_cache_flush
1017 .word 0x56050000 @ Feroceon
1019 W(b) __armv4_mmu_cache_on
1020 W(b) __armv4_mmu_cache_off
1021 W(b) __armv5tej_mmu_cache_flush
1023 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
1024 /* this conflicts with the standard ARMv5TE entry */
1025 .long 0x41009260 @ Old Feroceon
1027 b __armv4_mmu_cache_on
1028 b __armv4_mmu_cache_off
1029 b __armv5tej_mmu_cache_flush
1032 .word 0x66015261 @ FA526
1034 W(b) __fa526_cache_on
1035 W(b) __armv4_mmu_cache_off
1036 W(b) __fa526_cache_flush
1038 @ These match on the architecture ID
1040 .word 0x00020000 @ ARMv4T
1042 W(b) __armv4_mmu_cache_on
1043 W(b) __armv4_mmu_cache_off
1044 W(b) __armv4_mmu_cache_flush
1046 .word 0x00050000 @ ARMv5TE
1048 W(b) __armv4_mmu_cache_on
1049 W(b) __armv4_mmu_cache_off
1050 W(b) __armv4_mmu_cache_flush
1052 .word 0x00060000 @ ARMv5TEJ
1054 W(b) __armv4_mmu_cache_on
1055 W(b) __armv4_mmu_cache_off
1056 W(b) __armv5tej_mmu_cache_flush
1058 .word 0x0007b000 @ ARMv6
1060 W(b) __armv6_mmu_cache_on
1061 W(b) __armv4_mmu_cache_off
1062 W(b) __armv6_mmu_cache_flush
1064 .word 0x000f0000 @ new CPU Id
1066 W(b) __armv7_mmu_cache_on
1067 W(b) __armv7_mmu_cache_off
1068 W(b) __armv7_mmu_cache_flush
1070 .word 0 @ unrecognised type
1079 .size proc_types, . - proc_types
1082 * If you get a "non-constant expression in ".if" statement"
1083 * error from the assembler on this line, check that you have
1084 * not accidentally written a "b" instruction where you should
1085 * have written W(b).
1087 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1088 .error "The size of one or more proc_types entries is wrong."
1092 * Turn off the Cache and MMU. ARMv3 does not support
1093 * reading the control register, but ARMv4 does.
1096 * r0, r1, r2, r3, r9, r12 corrupted
1097 * This routine must preserve:
1101 cache_off: mov r3, #12 @ cache_off function
1104 __armv4_mpu_cache_off:
1105 mrc p15, 0, r0, c1, c0
1107 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1109 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1110 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1111 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1114 __armv3_mpu_cache_off:
1115 mrc p15, 0, r0, c1, c0
1117 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1119 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1122 __armv4_mmu_cache_off:
1124 mrc p15, 0, r0, c1, c0
1126 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1128 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1129 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1133 __armv7_mmu_cache_off:
1134 mrc p15, 0, r0, c1, c0
1140 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1142 bl __armv7_mmu_cache_flush
1145 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1147 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1148 mcr p15, 0, r0, c7, c10, 4 @ DSB
1149 mcr p15, 0, r0, c7, c5, 4 @ ISB
1153 * Clean and flush the cache to maintain consistency.
1156 * r1, r2, r3, r9, r10, r11, r12 corrupted
1157 * This routine must preserve:
1165 __armv4_mpu_cache_flush:
1170 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1171 mov r1, #7 << 5 @ 8 segments
1172 1: orr r3, r1, #63 << 26 @ 64 entries
1173 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1174 subs r3, r3, #1 << 26
1175 bcs 2b @ entries 63 to 0
1176 subs r1, r1, #1 << 5
1177 bcs 1b @ segments 7 to 0
1180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1181 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1184 __fa526_cache_flush:
1188 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1189 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1190 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1193 __armv6_mmu_cache_flush:
1196 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1197 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1198 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1199 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1202 __armv7_mmu_cache_flush:
1205 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1206 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1209 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1212 mcr p15, 0, r10, c7, c10, 5 @ DMB
1213 stmfd sp!, {r0-r7, r9-r11}
1214 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1215 ands r3, r0, #0x7000000 @ extract loc from clidr
1216 mov r3, r3, lsr #23 @ left align loc bit field
1217 beq finished @ if loc is 0, then no need to clean
1218 mov r10, #0 @ start clean at cache level 0
1220 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1221 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1222 and r1, r1, #7 @ mask of the bits for current cache only
1223 cmp r1, #2 @ see what cache we have at this level
1224 blt skip @ skip if no cache, or just i-cache
1225 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1226 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1227 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1228 and r2, r1, #7 @ extract the length of the cache lines
1229 add r2, r2, #4 @ add 4 (line length offset)
1231 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1232 clz r5, r4 @ find bit position of way size increment
1234 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1236 mov r9, r4 @ create working copy of max way size
1238 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1239 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1240 THUMB( lsl r6, r9, r5 )
1241 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1242 THUMB( lsl r6, r7, r2 )
1243 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1244 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1245 subs r9, r9, #1 @ decrement the way
1247 subs r7, r7, #1 @ decrement the index
1250 add r10, r10, #2 @ increment cache number
1254 ldmfd sp!, {r0-r7, r9-r11}
1255 mov r10, #0 @ switch back to cache level 0
1256 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1258 mcr p15, 0, r10, c7, c10, 4 @ DSB
1259 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1260 mcr p15, 0, r10, c7, c10, 4 @ DSB
1261 mcr p15, 0, r10, c7, c5, 4 @ ISB
1264 __armv5tej_mmu_cache_flush:
1267 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1269 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1270 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1273 __armv4_mmu_cache_flush:
1276 mov r2, #64*1024 @ default: 32K dcache size (*2)
1277 mov r11, #32 @ default: 32 byte line size
1278 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1279 teq r3, r9 @ cache ID register present?
1284 mov r2, r2, lsl r1 @ base dcache size *2
1285 tst r3, #1 << 14 @ test M bit
1286 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1290 mov r11, r11, lsl r3 @ cache line size in bytes
1293 bic r1, r1, #63 @ align to longest cache line
1296 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1297 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1298 THUMB( add r1, r1, r11 )
1302 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1303 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1304 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1307 __armv3_mmu_cache_flush:
1308 __armv3_mpu_cache_flush:
1312 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1316 * Various debugging routines for printing hex characters and
1317 * memory, which again must be relocatable.
1321 .type phexbuf,#object
1323 .size phexbuf, . - phexbuf
1325 @ phex corrupts {r0, r1, r2, r3}
1326 phex: adr r3, phexbuf
1340 @ puts corrupts {r0, r1, r2, r3}
1341 puts: loadsp r3, r2, r1
1342 1: ldrb r2, [r0], #1
1355 @ putc corrupts {r0, r1, r2, r3}
1362 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1363 memdump: mov r12, r0
1366 2: mov r0, r11, lsl #2
1374 ldr r0, [r12, r11, lsl #2]
1394 #ifdef CONFIG_ARM_VIRT_EXT
1396 __hyp_reentry_vectors:
1402 W(b) __enter_kernel @ hyp
1405 #endif /* CONFIG_ARM_VIRT_EXT */
1408 mov r0, #0 @ must be 0
1409 mov r1, r7 @ restore architecture number
1410 mov r2, r8 @ restore atags pointer
1411 ARM( mov pc, r4 ) @ call kernel
1412 M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
1413 THUMB( bx r4 ) @ entry point is always ARM for A/R classes
1417 #ifdef CONFIG_EFI_STUB
1419 _start: .long start - .
1421 ENTRY(efi_stub_entry)
1422 @ allocate space on stack for passing current zImage address
1423 @ and for the EFI stub to return of new entry point of
1424 @ zImage, as EFI stub may copy the kernel. Pointer address
1425 @ is passed in r2. r0 and r1 are passed through from the
1426 @ EFI firmware to efi_entry
1431 mov r2, sp @ pass zImage address in r2
1434 @ Check for error return from EFI stub. r0 has FDT address
1439 @ Preserve return value of efi_entry() in r4
1442 @ our cache maintenance code relies on CP15 barrier instructions
1443 @ but since we arrived here with the MMU and caches configured
1444 @ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
1445 @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
1446 @ the enable path will be executed on v7+ only.
1447 mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
1448 tst r1, #(1 << 5) @ CP15BEN bit set?
1450 orr r1, r1, #(1 << 5) @ CP15 barrier instructions
1451 mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
1452 ARM( .inst 0xf57ff06f @ v7+ isb )
1455 0: bl cache_clean_flush
1458 @ Set parameters for booting zImage according to boot protocol
1459 @ put FDT address in r2, it was returned by efi_entry()
1460 @ r1 is the machine type, and r0 needs to be 0
1465 @ Branch to (possibly) relocated zImage that is in [sp]
1467 ldr ip, =start_offset
1469 mov pc, lr @ no mode switch
1472 @ Return EFI_LOAD_ERROR to EFI firmware on error.
1475 ENDPROC(efi_stub_entry)
1479 .section ".stack", "aw", %nobits
1480 .L_user_stack: .space 4096