5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary, or theoretically 64K
206 for the MSM machine class.
208 config ARM_PATCH_PHYS_VIRT_16BIT
210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
212 This option extends the physical to virtual translation patching
213 to allow physical memory down to a theoretical minimum of 64K
216 source "init/Kconfig"
218 source "kernel/Kconfig.freezer"
223 bool "MMU-based Paged Memory Management Support"
226 Select if you want MMU-based virtualised addressing space
227 support by paged memory management. If unsure, say 'Y'.
230 # The "ARM system type" choice list is ordered alphabetically by option
231 # text. Please add new entries in the option alphabetic order.
234 prompt "ARM system type"
235 default ARCH_VERSATILE
237 config ARCH_INTEGRATOR
238 bool "ARM Ltd. Integrator family"
240 select ARCH_HAS_CPUFREQ
243 select GENERIC_CLOCKEVENTS
244 select PLAT_VERSATILE
245 select PLAT_VERSATILE_FPGA_IRQ
247 Support for ARM's Integrator platform.
250 bool "ARM Ltd. RealView family"
254 select GENERIC_CLOCKEVENTS
255 select ARCH_WANT_OPTIONAL_GPIOLIB
256 select PLAT_VERSATILE
257 select PLAT_VERSATILE_CLCD
258 select ARM_TIMER_SP804
259 select GPIO_PL061 if GPIOLIB
261 This enables support for ARM Ltd RealView boards.
263 config ARCH_VERSATILE
264 bool "ARM Ltd. Versatile family"
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select PLAT_VERSATILE_FPGA_IRQ
274 select ARM_TIMER_SP804
276 This enables support for ARM Ltd Versatile board.
279 bool "ARM Ltd. Versatile Express family"
280 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select ARM_TIMER_SP804
284 select GENERIC_CLOCKEVENTS
286 select HAVE_PATA_PLATFORM
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
291 This enables support for the ARM Ltd Versatile Express boards.
295 select ARCH_REQUIRE_GPIOLIB
298 This enables support for systems based on the Atmel AT91RM9200,
299 AT91SAM9 and AT91CAP9 processors.
302 bool "Broadcom BCMRING"
306 select ARM_TIMER_SP804
308 select GENERIC_CLOCKEVENTS
309 select ARCH_WANT_OPTIONAL_GPIOLIB
311 Support for Broadcom's BCMRing platform.
314 bool "Cirrus Logic CLPS711x/EP721x-based"
316 select ARCH_USES_GETTIMEOFFSET
318 Support for Cirrus Logic 711x/721x based boards.
321 bool "Cavium Networks CNS3XXX family"
323 select GENERIC_CLOCKEVENTS
325 select MIGHT_HAVE_PCI
326 select PCI_DOMAINS if PCI
328 Support for Cavium Networks CNS3XXX platform.
331 bool "Cortina Systems Gemini"
333 select ARCH_REQUIRE_GPIOLIB
334 select ARCH_USES_GETTIMEOFFSET
336 Support for the Cortina Systems Gemini family SoCs
343 select ARCH_USES_GETTIMEOFFSET
345 This is an evaluation board for the StrongARM processor available
346 from Digital. It has limited hardware on-board, including an
347 Ethernet interface, two PCMCIA sockets, two serial ports and a
356 select ARCH_REQUIRE_GPIOLIB
357 select ARCH_HAS_HOLES_MEMORYMODEL
358 select ARCH_USES_GETTIMEOFFSET
360 This enables support for the Cirrus EP93xx series of CPUs.
362 config ARCH_FOOTBRIDGE
366 select GENERIC_CLOCKEVENTS
368 Support for systems based on the DC21285 companion chip
369 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
372 bool "Freescale MXC/iMX-based"
373 select GENERIC_CLOCKEVENTS
374 select ARCH_REQUIRE_GPIOLIB
377 select HAVE_SCHED_CLOCK
379 Support for Freescale MXC/iMX-based family of processors
382 bool "Freescale MXS-based"
383 select GENERIC_CLOCKEVENTS
384 select ARCH_REQUIRE_GPIOLIB
388 Support for Freescale MXS-based family of processors
391 bool "Hilscher NetX based"
395 select GENERIC_CLOCKEVENTS
397 This enables support for systems based on the Hilscher NetX Soc
400 bool "Hynix HMS720x-based"
403 select ARCH_USES_GETTIMEOFFSET
405 This enables support for systems based on the Hynix HMS720x
413 select ARCH_SUPPORTS_MSI
416 Support for Intel's IOP13XX (XScale) family of processors.
424 select ARCH_REQUIRE_GPIOLIB
426 Support for Intel's 80219 and IOP32X (XScale) family of
435 select ARCH_REQUIRE_GPIOLIB
437 Support for Intel's IOP33X (XScale) family of processors.
444 select ARCH_USES_GETTIMEOFFSET
446 Support for Intel's IXP23xx (XScale) family of processors.
449 bool "IXP2400/2800-based"
453 select ARCH_USES_GETTIMEOFFSET
455 Support for Intel's IXP2400/2800 (XScale) family of processors.
463 select GENERIC_CLOCKEVENTS
464 select HAVE_SCHED_CLOCK
465 select MIGHT_HAVE_PCI
466 select DMABOUNCE if PCI
468 Support for Intel's IXP4XX (XScale) family of processors.
474 select ARCH_REQUIRE_GPIOLIB
475 select GENERIC_CLOCKEVENTS
478 Support for the Marvell Dove SoC 88AP510
481 bool "Marvell Kirkwood"
484 select ARCH_REQUIRE_GPIOLIB
485 select GENERIC_CLOCKEVENTS
488 Support for the following Marvell Kirkwood series SoCs:
489 88F6180, 88F6192 and 88F6281.
492 bool "Marvell Loki (88RC8480)"
494 select GENERIC_CLOCKEVENTS
497 Support for the Marvell Loki (88RC8480) SoC.
503 select ARCH_REQUIRE_GPIOLIB
506 select USB_ARCH_HAS_OHCI
509 select GENERIC_CLOCKEVENTS
511 Support for the NXP LPC32XX family of processors
514 bool "Marvell MV78xx0"
517 select ARCH_REQUIRE_GPIOLIB
518 select GENERIC_CLOCKEVENTS
521 Support for the following Marvell MV78xx0 series SoCs:
529 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 Support for the following Marvell Orion 5x series SoCs:
534 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
535 Orion-2 (5281), Orion-1-90 (6183).
538 bool "Marvell PXA168/910/MMP2"
540 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
543 select HAVE_SCHED_CLOCK
548 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
551 bool "Micrel/Kendin KS8695"
553 select ARCH_REQUIRE_GPIOLIB
554 select ARCH_USES_GETTIMEOFFSET
556 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
557 System-on-Chip devices.
560 bool "Nuvoton W90X900 CPU"
562 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
567 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
568 At present, the w90x900 has been renamed nuc900, regarding
569 the ARM series product line, you can login the following
570 link address to know more.
572 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
573 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
576 bool "Nuvoton NUC93X CPU"
580 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
581 low-power and high performance MPEG-4/JPEG multimedia controller chip.
588 select GENERIC_CLOCKEVENTS
591 select HAVE_SCHED_CLOCK
592 select ARCH_HAS_BARRIERS if CACHE_L2X0
593 select ARCH_HAS_CPUFREQ
595 This enables support for NVIDIA Tegra based systems (Tegra APX,
596 Tegra 6xx and Tegra 2 series).
599 bool "Philips Nexperia PNX4008 Mobile"
602 select ARCH_USES_GETTIMEOFFSET
604 This enables support for Philips PNX4008 mobile platform.
607 bool "PXA2xx/PXA3xx-based"
610 select ARCH_HAS_CPUFREQ
613 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
615 select HAVE_SCHED_CLOCK
620 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
625 select GENERIC_CLOCKEVENTS
626 select ARCH_REQUIRE_GPIOLIB
629 Support for Qualcomm MSM/QSD based systems. This runs on the
630 apps processor of the MSM/QSD and depends on a shared memory
631 interface to the modem processor which runs the baseband
632 stack and controls some vital subsystems
633 (clock and power control, etc).
636 bool "Renesas SH-Mobile / R-Mobile"
639 select GENERIC_CLOCKEVENTS
642 select MULTI_IRQ_HANDLER
644 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
651 select ARCH_MAY_HAVE_PC_FDC
652 select HAVE_PATA_PLATFORM
655 select ARCH_SPARSEMEM_ENABLE
656 select ARCH_USES_GETTIMEOFFSET
658 On the Acorn Risc-PC, Linux can support the internal IDE disk and
659 CD-ROM interface, serial and parallel port, and the floppy drive.
666 select ARCH_SPARSEMEM_ENABLE
668 select ARCH_HAS_CPUFREQ
670 select GENERIC_CLOCKEVENTS
672 select HAVE_SCHED_CLOCK
674 select ARCH_REQUIRE_GPIOLIB
676 Support for StrongARM 11x0 based boards.
679 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
681 select ARCH_HAS_CPUFREQ
683 select ARCH_USES_GETTIMEOFFSET
684 select HAVE_S3C2410_I2C if I2C
686 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
687 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
688 the Samsung SMDK2410 development board (and derivatives).
690 Note, the S3C2416 and the S3C2450 are so close that they even share
691 the same SoC ID code. This means that there is no separate machine
692 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
695 bool "Samsung S3C64XX"
701 select ARCH_USES_GETTIMEOFFSET
702 select ARCH_HAS_CPUFREQ
703 select ARCH_REQUIRE_GPIOLIB
704 select SAMSUNG_CLKSRC
705 select SAMSUNG_IRQ_VIC_TIMER
706 select SAMSUNG_IRQ_UART
707 select S3C_GPIO_TRACK
708 select S3C_GPIO_PULL_UPDOWN
709 select S3C_GPIO_CFG_S3C24XX
710 select S3C_GPIO_CFG_S3C64XX
712 select USB_ARCH_HAS_OHCI
713 select SAMSUNG_GPIOLIB_4BIT
714 select HAVE_S3C2410_I2C if I2C
715 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 Samsung S3C64XX series based systems
720 bool "Samsung S5P6440 S5P6450"
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select GENERIC_CLOCKEVENTS
726 select HAVE_SCHED_CLOCK
727 select HAVE_S3C2410_I2C if I2C
728 select HAVE_S3C_RTC if RTC_CLASS
730 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
734 bool "Samsung S5PC100"
738 select ARM_L1_CACHE_SHIFT_6
739 select ARCH_USES_GETTIMEOFFSET
740 select HAVE_S3C2410_I2C if I2C
741 select HAVE_S3C_RTC if RTC_CLASS
742 select HAVE_S3C2410_WATCHDOG if WATCHDOG
744 Samsung S5PC100 series based systems
747 bool "Samsung S5PV210/S5PC110"
749 select ARCH_SPARSEMEM_ENABLE
752 select ARM_L1_CACHE_SHIFT_6
753 select ARCH_HAS_CPUFREQ
754 select GENERIC_CLOCKEVENTS
755 select HAVE_SCHED_CLOCK
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C_RTC if RTC_CLASS
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
760 Samsung S5PV210/S5PC110 series based systems
763 bool "Samsung EXYNOS4"
765 select ARCH_SPARSEMEM_ENABLE
768 select ARCH_HAS_CPUFREQ
769 select GENERIC_CLOCKEVENTS
770 select HAVE_S3C_RTC if RTC_CLASS
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 Samsung EXYNOS4 series based systems
783 select ARCH_USES_GETTIMEOFFSET
785 Support for the StrongARM based Digital DNARD machine, also known
786 as "Shark" (<http://www.shark-linux.de/shark.html>).
789 bool "Telechips TCC ARM926-based systems"
794 select GENERIC_CLOCKEVENTS
796 Support for Telechips TCC ARM926-based systems.
799 bool "ST-Ericsson U300 Series"
803 select HAVE_SCHED_CLOCK
807 select GENERIC_CLOCKEVENTS
811 Support for ST-Ericsson U300 series mobile platforms.
814 bool "ST-Ericsson U8500 Series"
817 select GENERIC_CLOCKEVENTS
819 select ARCH_REQUIRE_GPIOLIB
820 select ARCH_HAS_CPUFREQ
822 Support for ST-Ericsson's Ux500 architecture
825 bool "STMicroelectronics Nomadik"
830 select GENERIC_CLOCKEVENTS
831 select ARCH_REQUIRE_GPIOLIB
833 Support for the Nomadik platform by ST-Ericsson
837 select GENERIC_CLOCKEVENTS
838 select ARCH_REQUIRE_GPIOLIB
842 select GENERIC_ALLOCATOR
843 select GENERIC_IRQ_CHIP
844 select ARCH_HAS_HOLES_MEMORYMODEL
846 Support for TI's DaVinci platform.
851 select ARCH_REQUIRE_GPIOLIB
852 select ARCH_HAS_CPUFREQ
853 select GENERIC_CLOCKEVENTS
854 select HAVE_SCHED_CLOCK
855 select ARCH_HAS_HOLES_MEMORYMODEL
857 Support for TI's OMAP platform (OMAP1/2/3/4).
862 select ARCH_REQUIRE_GPIOLIB
865 select GENERIC_CLOCKEVENTS
868 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
871 bool "VIA/WonderMedia 85xx"
874 select ARCH_HAS_CPUFREQ
875 select GENERIC_CLOCKEVENTS
876 select ARCH_REQUIRE_GPIOLIB
879 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
883 # This is sorted alphabetically by mach-* pathname. However, plat-*
884 # Kconfigs may be included either alphabetically (according to the
885 # plat- suffix) or along side the corresponding mach-* source.
887 source "arch/arm/mach-at91/Kconfig"
889 source "arch/arm/mach-bcmring/Kconfig"
891 source "arch/arm/mach-clps711x/Kconfig"
893 source "arch/arm/mach-cns3xxx/Kconfig"
895 source "arch/arm/mach-davinci/Kconfig"
897 source "arch/arm/mach-dove/Kconfig"
899 source "arch/arm/mach-ep93xx/Kconfig"
901 source "arch/arm/mach-footbridge/Kconfig"
903 source "arch/arm/mach-gemini/Kconfig"
905 source "arch/arm/mach-h720x/Kconfig"
907 source "arch/arm/mach-integrator/Kconfig"
909 source "arch/arm/mach-iop32x/Kconfig"
911 source "arch/arm/mach-iop33x/Kconfig"
913 source "arch/arm/mach-iop13xx/Kconfig"
915 source "arch/arm/mach-ixp4xx/Kconfig"
917 source "arch/arm/mach-ixp2000/Kconfig"
919 source "arch/arm/mach-ixp23xx/Kconfig"
921 source "arch/arm/mach-kirkwood/Kconfig"
923 source "arch/arm/mach-ks8695/Kconfig"
925 source "arch/arm/mach-loki/Kconfig"
927 source "arch/arm/mach-lpc32xx/Kconfig"
929 source "arch/arm/mach-msm/Kconfig"
931 source "arch/arm/mach-mv78xx0/Kconfig"
933 source "arch/arm/plat-mxc/Kconfig"
935 source "arch/arm/mach-mxs/Kconfig"
937 source "arch/arm/mach-netx/Kconfig"
939 source "arch/arm/mach-nomadik/Kconfig"
940 source "arch/arm/plat-nomadik/Kconfig"
942 source "arch/arm/mach-nuc93x/Kconfig"
944 source "arch/arm/plat-omap/Kconfig"
946 source "arch/arm/mach-omap1/Kconfig"
948 source "arch/arm/mach-omap2/Kconfig"
950 source "arch/arm/mach-orion5x/Kconfig"
952 source "arch/arm/mach-pxa/Kconfig"
953 source "arch/arm/plat-pxa/Kconfig"
955 source "arch/arm/mach-mmp/Kconfig"
957 source "arch/arm/mach-realview/Kconfig"
959 source "arch/arm/mach-sa1100/Kconfig"
961 source "arch/arm/plat-samsung/Kconfig"
962 source "arch/arm/plat-s3c24xx/Kconfig"
963 source "arch/arm/plat-s5p/Kconfig"
965 source "arch/arm/plat-spear/Kconfig"
967 source "arch/arm/plat-tcc/Kconfig"
970 source "arch/arm/mach-s3c2400/Kconfig"
971 source "arch/arm/mach-s3c2410/Kconfig"
972 source "arch/arm/mach-s3c2412/Kconfig"
973 source "arch/arm/mach-s3c2416/Kconfig"
974 source "arch/arm/mach-s3c2440/Kconfig"
975 source "arch/arm/mach-s3c2443/Kconfig"
979 source "arch/arm/mach-s3c64xx/Kconfig"
982 source "arch/arm/mach-s5p64x0/Kconfig"
984 source "arch/arm/mach-s5pc100/Kconfig"
986 source "arch/arm/mach-s5pv210/Kconfig"
988 source "arch/arm/mach-exynos4/Kconfig"
990 source "arch/arm/mach-shmobile/Kconfig"
992 source "arch/arm/mach-tegra/Kconfig"
994 source "arch/arm/mach-u300/Kconfig"
996 source "arch/arm/mach-ux500/Kconfig"
998 source "arch/arm/mach-versatile/Kconfig"
1000 source "arch/arm/mach-vexpress/Kconfig"
1001 source "arch/arm/plat-versatile/Kconfig"
1003 source "arch/arm/mach-vt8500/Kconfig"
1005 source "arch/arm/mach-w90x900/Kconfig"
1007 # Definitions to make life easier
1013 select GENERIC_CLOCKEVENTS
1014 select HAVE_SCHED_CLOCK
1019 select GENERIC_IRQ_CHIP
1020 select HAVE_SCHED_CLOCK
1025 config PLAT_VERSATILE
1028 config ARM_TIMER_SP804
1032 source arch/arm/mm/Kconfig
1035 bool "Enable iWMMXt support"
1036 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1037 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1039 Enable support for iWMMXt context switching at run time if
1040 running on a CPU that supports it.
1042 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1045 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1049 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1050 (!ARCH_OMAP3 || OMAP3_EMU)
1054 config MULTI_IRQ_HANDLER
1057 Allow each machine to specify it's own IRQ handler at run time.
1060 source "arch/arm/Kconfig-nommu"
1063 config ARM_ERRATA_411920
1064 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1065 depends on CPU_V6 || CPU_V6K
1067 Invalidation of the Instruction Cache operation can
1068 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1069 It does not affect the MPCore. This option enables the ARM Ltd.
1070 recommended workaround.
1072 config ARM_ERRATA_430973
1073 bool "ARM errata: Stale prediction on replaced interworking branch"
1076 This option enables the workaround for the 430973 Cortex-A8
1077 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1078 interworking branch is replaced with another code sequence at the
1079 same virtual address, whether due to self-modifying code or virtual
1080 to physical address re-mapping, Cortex-A8 does not recover from the
1081 stale interworking branch prediction. This results in Cortex-A8
1082 executing the new code sequence in the incorrect ARM or Thumb state.
1083 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1084 and also flushes the branch target cache at every context switch.
1085 Note that setting specific bits in the ACTLR register may not be
1086 available in non-secure mode.
1088 config ARM_ERRATA_458693
1089 bool "ARM errata: Processor deadlock when a false hazard is created"
1092 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1093 erratum. For very specific sequences of memory operations, it is
1094 possible for a hazard condition intended for a cache line to instead
1095 be incorrectly associated with a different cache line. This false
1096 hazard might then cause a processor deadlock. The workaround enables
1097 the L1 caching of the NEON accesses and disables the PLD instruction
1098 in the ACTLR register. Note that setting specific bits in the ACTLR
1099 register may not be available in non-secure mode.
1101 config ARM_ERRATA_460075
1102 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1105 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1106 erratum. Any asynchronous access to the L2 cache may encounter a
1107 situation in which recent store transactions to the L2 cache are lost
1108 and overwritten with stale memory contents from external memory. The
1109 workaround disables the write-allocate mode for the L2 cache via the
1110 ACTLR register. Note that setting specific bits in the ACTLR register
1111 may not be available in non-secure mode.
1113 config ARM_ERRATA_742230
1114 bool "ARM errata: DMB operation may be faulty"
1115 depends on CPU_V7 && SMP
1117 This option enables the workaround for the 742230 Cortex-A9
1118 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1119 between two write operations may not ensure the correct visibility
1120 ordering of the two writes. This workaround sets a specific bit in
1121 the diagnostic register of the Cortex-A9 which causes the DMB
1122 instruction to behave as a DSB, ensuring the correct behaviour of
1125 config ARM_ERRATA_742231
1126 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1127 depends on CPU_V7 && SMP
1129 This option enables the workaround for the 742231 Cortex-A9
1130 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1131 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1132 accessing some data located in the same cache line, may get corrupted
1133 data due to bad handling of the address hazard when the line gets
1134 replaced from one of the CPUs at the same time as another CPU is
1135 accessing it. This workaround sets specific bits in the diagnostic
1136 register of the Cortex-A9 which reduces the linefill issuing
1137 capabilities of the processor.
1139 config PL310_ERRATA_588369
1140 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1141 depends on CACHE_L2X0
1143 The PL310 L2 cache controller implements three types of Clean &
1144 Invalidate maintenance operations: by Physical Address
1145 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1146 They are architecturally defined to behave as the execution of a
1147 clean operation followed immediately by an invalidate operation,
1148 both performing to the same memory location. This functionality
1149 is not correctly implemented in PL310 as clean lines are not
1150 invalidated as a result of these operations.
1152 config ARM_ERRATA_720789
1153 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1154 depends on CPU_V7 && SMP
1156 This option enables the workaround for the 720789 Cortex-A9 (prior to
1157 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1158 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1159 As a consequence of this erratum, some TLB entries which should be
1160 invalidated are not, resulting in an incoherency in the system page
1161 tables. The workaround changes the TLB flushing routines to invalidate
1162 entries regardless of the ASID.
1164 config PL310_ERRATA_727915
1165 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1166 depends on CACHE_L2X0
1168 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1169 operation (offset 0x7FC). This operation runs in background so that
1170 PL310 can handle normal accesses while it is in progress. Under very
1171 rare circumstances, due to this erratum, write data can be lost when
1172 PL310 treats a cacheable write transaction during a Clean &
1173 Invalidate by Way operation.
1175 config ARM_ERRATA_743622
1176 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1179 This option enables the workaround for the 743622 Cortex-A9
1180 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1181 optimisation in the Cortex-A9 Store Buffer may lead to data
1182 corruption. This workaround sets a specific bit in the diagnostic
1183 register of the Cortex-A9 which disables the Store Buffer
1184 optimisation, preventing the defect from occurring. This has no
1185 visible impact on the overall performance or power consumption of the
1188 config ARM_ERRATA_751472
1189 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1190 depends on CPU_V7 && SMP
1192 This option enables the workaround for the 751472 Cortex-A9 (prior
1193 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1194 completion of a following broadcasted operation if the second
1195 operation is received by a CPU before the ICIALLUIS has completed,
1196 potentially leading to corrupted entries in the cache or TLB.
1198 config ARM_ERRATA_753970
1199 bool "ARM errata: cache sync operation may be faulty"
1200 depends on CACHE_PL310
1202 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1204 Under some condition the effect of cache sync operation on
1205 the store buffer still remains when the operation completes.
1206 This means that the store buffer is always asked to drain and
1207 this prevents it from merging any further writes. The workaround
1208 is to replace the normal offset of cache sync operation (0x730)
1209 by another offset targeting an unmapped PL310 register 0x740.
1210 This has the same effect as the cache sync operation: store buffer
1211 drain and waiting for all buffers empty.
1213 config ARM_ERRATA_754322
1214 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1217 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1218 r3p*) erratum. A speculative memory access may cause a page table walk
1219 which starts prior to an ASID switch but completes afterwards. This
1220 can populate the micro-TLB with a stale entry which may be hit with
1221 the new ASID. This workaround places two dsb instructions in the mm
1222 switching code so that no page table walks can cross the ASID switch.
1224 config ARM_ERRATA_754327
1225 bool "ARM errata: no automatic Store Buffer drain"
1226 depends on CPU_V7 && SMP
1228 This option enables the workaround for the 754327 Cortex-A9 (prior to
1229 r2p0) erratum. The Store Buffer does not have any automatic draining
1230 mechanism and therefore a livelock may occur if an external agent
1231 continuously polls a memory location waiting to observe an update.
1232 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1233 written polling loops from denying visibility of updates to memory.
1237 source "arch/arm/common/Kconfig"
1247 Find out whether you have ISA slots on your motherboard. ISA is the
1248 name of a bus system, i.e. the way the CPU talks to the other stuff
1249 inside your box. Other bus systems are PCI, EISA, MicroChannel
1250 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1251 newer boards don't support it. If you have ISA, say Y, otherwise N.
1253 # Select ISA DMA controller support
1258 # Select ISA DMA interface
1263 bool "PCI support" if MIGHT_HAVE_PCI
1265 Find out whether you have a PCI motherboard. PCI is the name of a
1266 bus system, i.e. the way the CPU talks to the other stuff inside
1267 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1268 VESA. If you have PCI, say Y, otherwise N.
1274 config PCI_NANOENGINE
1275 bool "BSE nanoEngine PCI support"
1276 depends on SA1100_NANOENGINE
1278 Enable PCI on the BSE nanoEngine board.
1283 # Select the host bridge type
1284 config PCI_HOST_VIA82C505
1286 depends on PCI && ARCH_SHARK
1289 config PCI_HOST_ITE8152
1291 depends on PCI && MACH_ARMCORE
1295 source "drivers/pci/Kconfig"
1297 source "drivers/pcmcia/Kconfig"
1301 menu "Kernel Features"
1303 source "kernel/time/Kconfig"
1306 bool "Symmetric Multi-Processing"
1307 depends on CPU_V6K || CPU_V7
1308 depends on GENERIC_CLOCKEVENTS
1309 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1310 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1311 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1312 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1313 select USE_GENERIC_SMP_HELPERS
1314 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1316 This enables support for systems with more than one CPU. If you have
1317 a system with only one CPU, like most personal computers, say N. If
1318 you have a system with more than one CPU, say Y.
1320 If you say N here, the kernel will run on single and multiprocessor
1321 machines, but will use only one CPU of a multiprocessor machine. If
1322 you say Y here, the kernel will run on many, but not all, single
1323 processor machines. On a single processor machine, the kernel will
1324 run faster if you say N here.
1326 See also <file:Documentation/i386/IO-APIC.txt>,
1327 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1328 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1330 If you don't know what to do here, say N.
1333 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1334 depends on EXPERIMENTAL
1335 depends on SMP && !XIP_KERNEL
1338 SMP kernels contain instructions which fail on non-SMP processors.
1339 Enabling this option allows the kernel to modify itself to make
1340 these instructions safe. Disabling it allows about 1K of space
1343 If you don't know what to do here, say Y.
1349 This option enables support for the ARM system coherency unit
1356 This options enables support for the ARM timer and watchdog unit
1359 prompt "Memory split"
1362 Select the desired split between kernel and user memory.
1364 If you are not absolutely sure what you are doing, leave this
1368 bool "3G/1G user/kernel split"
1370 bool "2G/2G user/kernel split"
1372 bool "1G/3G user/kernel split"
1377 default 0x40000000 if VMSPLIT_1G
1378 default 0x80000000 if VMSPLIT_2G
1382 int "Maximum number of CPUs (2-32)"
1388 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1389 depends on SMP && HOTPLUG && EXPERIMENTAL
1390 depends on !ARCH_MSM
1392 Say Y here to experiment with turning CPUs off and on. CPUs
1393 can be controlled through /sys/devices/system/cpu.
1396 bool "Use local timer interrupts"
1399 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1401 Enable support for local timers on SMP platforms, rather then the
1402 legacy IPI broadcast method. Local timers allows the system
1403 accounting to be spread across the timer interval, preventing a
1404 "thundering herd" at every timer tick.
1406 source kernel/Kconfig.preempt
1410 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1411 ARCH_S5PV210 || ARCH_EXYNOS4
1412 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1413 default AT91_TIMER_HZ if ARCH_AT91
1414 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1417 config THUMB2_KERNEL
1418 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1419 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1421 select ARM_ASM_UNIFIED
1423 By enabling this option, the kernel will be compiled in
1424 Thumb-2 mode. A compiler/assembler that understand the unified
1425 ARM-Thumb syntax is needed.
1429 config THUMB2_AVOID_R_ARM_THM_JUMP11
1430 bool "Work around buggy Thumb-2 short branch relocations in gas"
1431 depends on THUMB2_KERNEL && MODULES
1434 Various binutils versions can resolve Thumb-2 branches to
1435 locally-defined, preemptible global symbols as short-range "b.n"
1436 branch instructions.
1438 This is a problem, because there's no guarantee the final
1439 destination of the symbol, or any candidate locations for a
1440 trampoline, are within range of the branch. For this reason, the
1441 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1442 relocation in modules at all, and it makes little sense to add
1445 The symptom is that the kernel fails with an "unsupported
1446 relocation" error when loading some modules.
1448 Until fixed tools are available, passing
1449 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1450 code which hits this problem, at the cost of a bit of extra runtime
1451 stack usage in some cases.
1453 The problem is described in more detail at:
1454 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1456 Only Thumb-2 kernels are affected.
1458 Unless you are sure your tools don't have this problem, say Y.
1460 config ARM_ASM_UNIFIED
1464 bool "Use the ARM EABI to compile the kernel"
1466 This option allows for the kernel to be compiled using the latest
1467 ARM ABI (aka EABI). This is only useful if you are using a user
1468 space environment that is also compiled with EABI.
1470 Since there are major incompatibilities between the legacy ABI and
1471 EABI, especially with regard to structure member alignment, this
1472 option also changes the kernel syscall calling convention to
1473 disambiguate both ABIs and allow for backward compatibility support
1474 (selected with CONFIG_OABI_COMPAT).
1476 To use this you need GCC version 4.0.0 or later.
1479 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1480 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1483 This option preserves the old syscall interface along with the
1484 new (ARM EABI) one. It also provides a compatibility layer to
1485 intercept syscalls that have structure arguments which layout
1486 in memory differs between the legacy ABI and the new ARM EABI
1487 (only for non "thumb" binaries). This option adds a tiny
1488 overhead to all syscalls and produces a slightly larger kernel.
1489 If you know you'll be using only pure EABI user space then you
1490 can say N here. If this option is not selected and you attempt
1491 to execute a legacy ABI binary then the result will be
1492 UNPREDICTABLE (in fact it can be predicted that it won't work
1493 at all). If in doubt say Y.
1495 config ARCH_HAS_HOLES_MEMORYMODEL
1498 config ARCH_SPARSEMEM_ENABLE
1501 config ARCH_SPARSEMEM_DEFAULT
1502 def_bool ARCH_SPARSEMEM_ENABLE
1504 config ARCH_SELECT_MEMORY_MODEL
1505 def_bool ARCH_SPARSEMEM_ENABLE
1508 bool "High Memory Support"
1511 The address space of ARM processors is only 4 Gigabytes large
1512 and it has to accommodate user address space, kernel address
1513 space as well as some memory mapped IO. That means that, if you
1514 have a large amount of physical memory and/or IO, not all of the
1515 memory can be "permanently mapped" by the kernel. The physical
1516 memory that is not permanently mapped is called "high memory".
1518 Depending on the selected kernel/user memory split, minimum
1519 vmalloc space and actual amount of RAM, you may not need this
1520 option which should result in a slightly faster kernel.
1525 bool "Allocate 2nd-level pagetables from highmem"
1528 config HW_PERF_EVENTS
1529 bool "Enable hardware performance counter support for perf events"
1530 depends on PERF_EVENTS && CPU_HAS_PMU
1533 Enable hardware performance counter support for perf events. If
1534 disabled, perf events will use software events only.
1538 config FORCE_MAX_ZONEORDER
1539 int "Maximum zone order" if ARCH_SHMOBILE
1540 range 11 64 if ARCH_SHMOBILE
1541 default "9" if SA1111
1544 The kernel memory allocator divides physically contiguous memory
1545 blocks into "zones", where each zone is a power of two number of
1546 pages. This option selects the largest power of two that the kernel
1547 keeps in the memory allocator. If you need to allocate very large
1548 blocks of physically contiguous memory, then you may need to
1549 increase this value.
1551 This config option is actually maximum order plus one. For example,
1552 a value of 11 means that the largest free memory block is 2^10 pages.
1555 bool "Timer and CPU usage LEDs"
1556 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1557 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1558 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1559 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1560 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1561 ARCH_AT91 || ARCH_DAVINCI || \
1562 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1564 If you say Y here, the LEDs on your machine will be used
1565 to provide useful information about your current system status.
1567 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1568 be able to select which LEDs are active using the options below. If
1569 you are compiling a kernel for the EBSA-110 or the LART however, the
1570 red LED will simply flash regularly to indicate that the system is
1571 still functional. It is safe to say Y here if you have a CATS
1572 system, but the driver will do nothing.
1575 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1576 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1577 || MACH_OMAP_PERSEUS2
1579 depends on !GENERIC_CLOCKEVENTS
1580 default y if ARCH_EBSA110
1582 If you say Y here, one of the system LEDs (the green one on the
1583 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1584 will flash regularly to indicate that the system is still
1585 operational. This is mainly useful to kernel hackers who are
1586 debugging unstable kernels.
1588 The LART uses the same LED for both Timer LED and CPU usage LED
1589 functions. You may choose to use both, but the Timer LED function
1590 will overrule the CPU usage LED.
1593 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1595 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1596 || MACH_OMAP_PERSEUS2
1599 If you say Y here, the red LED will be used to give a good real
1600 time indication of CPU usage, by lighting whenever the idle task
1601 is not currently executing.
1603 The LART uses the same LED for both Timer LED and CPU usage LED
1604 functions. You may choose to use both, but the Timer LED function
1605 will overrule the CPU usage LED.
1607 config ALIGNMENT_TRAP
1609 depends on CPU_CP15_MMU
1610 default y if !ARCH_EBSA110
1611 select HAVE_PROC_CPU if PROC_FS
1613 ARM processors cannot fetch/store information which is not
1614 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1615 address divisible by 4. On 32-bit ARM processors, these non-aligned
1616 fetch/store instructions will be emulated in software if you say
1617 here, which has a severe performance impact. This is necessary for
1618 correct operation of some network protocols. With an IP-only
1619 configuration it is safe to say N, otherwise say Y.
1621 config UACCESS_WITH_MEMCPY
1622 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1623 depends on MMU && EXPERIMENTAL
1624 default y if CPU_FEROCEON
1626 Implement faster copy_to_user and clear_user methods for CPU
1627 cores where a 8-word STM instruction give significantly higher
1628 memory write throughput than a sequence of individual 32bit stores.
1630 A possible side effect is a slight increase in scheduling latency
1631 between threads sharing the same address space if they invoke
1632 such copy operations with large buffers.
1634 However, if the CPU data cache is using a write-allocate mode,
1635 this option is unlikely to provide any performance gain.
1639 prompt "Enable seccomp to safely compute untrusted bytecode"
1641 This kernel feature is useful for number crunching applications
1642 that may need to compute untrusted bytecode during their
1643 execution. By using pipes or other transports made available to
1644 the process as file descriptors supporting the read/write
1645 syscalls, it's possible to isolate those applications in
1646 their own address space using seccomp. Once seccomp is
1647 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1648 and the task is only allowed to execute a few safe syscalls
1649 defined by each seccomp mode.
1651 config CC_STACKPROTECTOR
1652 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1653 depends on EXPERIMENTAL
1655 This option turns on the -fstack-protector GCC feature. This
1656 feature puts, at the beginning of functions, a canary value on
1657 the stack just before the return address, and validates
1658 the value just before actually returning. Stack based buffer
1659 overflows (that need to overwrite this return address) now also
1660 overwrite the canary, which gets detected and the attack is then
1661 neutralized via a kernel panic.
1662 This feature requires gcc version 4.2 or above.
1664 config DEPRECATED_PARAM_STRUCT
1665 bool "Provide old way to pass kernel parameters"
1667 This was deprecated in 2001 and announced to live on for 5 years.
1668 Some old boot loaders still use this way.
1675 bool "Flattened Device Tree support"
1677 select OF_EARLY_FLATTREE
1679 Include support for flattened device tree machine descriptions.
1681 # Compressed boot loader in ROM. Yes, we really want to ask about
1682 # TEXT and BSS so we preserve their values in the config files.
1683 config ZBOOT_ROM_TEXT
1684 hex "Compressed ROM boot loader base address"
1687 The physical address at which the ROM-able zImage is to be
1688 placed in the target. Platforms which normally make use of
1689 ROM-able zImage formats normally set this to a suitable
1690 value in their defconfig file.
1692 If ZBOOT_ROM is not enabled, this has no effect.
1694 config ZBOOT_ROM_BSS
1695 hex "Compressed ROM boot loader BSS address"
1698 The base address of an area of read/write memory in the target
1699 for the ROM-able zImage which must be available while the
1700 decompressor is running. It must be large enough to hold the
1701 entire decompressed kernel plus an additional 128 KiB.
1702 Platforms which normally make use of ROM-able zImage formats
1703 normally set this to a suitable value in their defconfig file.
1705 If ZBOOT_ROM is not enabled, this has no effect.
1708 bool "Compressed boot loader in ROM/flash"
1709 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1711 Say Y here if you intend to execute your compressed kernel image
1712 (zImage) directly from ROM or flash. If unsure, say N.
1714 config ZBOOT_ROM_MMCIF
1715 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1716 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1718 Say Y here to include experimental MMCIF loading code in the
1719 ROM-able zImage. With this enabled it is possible to write the
1720 the ROM-able zImage kernel image to an MMC card and boot the
1721 kernel straight from the reset vector. At reset the processor
1722 Mask ROM will load the first part of the the ROM-able zImage
1723 which in turn loads the rest the kernel image to RAM using the
1724 MMCIF hardware block.
1727 string "Default kernel command string"
1730 On some architectures (EBSA110 and CATS), there is currently no way
1731 for the boot loader to pass arguments to the kernel. For these
1732 architectures, you should supply some command-line options at build
1733 time by entering them here. As a minimum, you should specify the
1734 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1737 prompt "Kernel command line type" if CMDLINE != ""
1738 default CMDLINE_FROM_BOOTLOADER
1740 config CMDLINE_FROM_BOOTLOADER
1741 bool "Use bootloader kernel arguments if available"
1743 Uses the command-line options passed by the boot loader. If
1744 the boot loader doesn't provide any, the default kernel command
1745 string provided in CMDLINE will be used.
1747 config CMDLINE_EXTEND
1748 bool "Extend bootloader kernel arguments"
1750 The command-line arguments provided by the boot loader will be
1751 appended to the default kernel command string.
1753 config CMDLINE_FORCE
1754 bool "Always use the default kernel command string"
1756 Always use the default kernel command string, even if the boot
1757 loader passes other arguments to the kernel.
1758 This is useful if you cannot or don't want to change the
1759 command-line options your boot loader passes to the kernel.
1763 bool "Kernel Execute-In-Place from ROM"
1764 depends on !ZBOOT_ROM
1766 Execute-In-Place allows the kernel to run from non-volatile storage
1767 directly addressable by the CPU, such as NOR flash. This saves RAM
1768 space since the text section of the kernel is not loaded from flash
1769 to RAM. Read-write sections, such as the data section and stack,
1770 are still copied to RAM. The XIP kernel is not compressed since
1771 it has to run directly from flash, so it will take more space to
1772 store it. The flash address used to link the kernel object files,
1773 and for storing it, is configuration dependent. Therefore, if you
1774 say Y here, you must know the proper physical address where to
1775 store the kernel image depending on your own flash memory usage.
1777 Also note that the make target becomes "make xipImage" rather than
1778 "make zImage" or "make Image". The final kernel binary to put in
1779 ROM memory will be arch/arm/boot/xipImage.
1783 config XIP_PHYS_ADDR
1784 hex "XIP Kernel Physical Location"
1785 depends on XIP_KERNEL
1786 default "0x00080000"
1788 This is the physical address in your flash memory the kernel will
1789 be linked for and stored to. This address is dependent on your
1793 bool "Kexec system call (EXPERIMENTAL)"
1794 depends on EXPERIMENTAL
1796 kexec is a system call that implements the ability to shutdown your
1797 current kernel, and to start another kernel. It is like a reboot
1798 but it is independent of the system firmware. And like a reboot
1799 you can start any kernel with it, not just Linux.
1801 It is an ongoing process to be certain the hardware in a machine
1802 is properly shutdown, so do not be surprised if this code does not
1803 initially work for you. It may help to enable device hotplugging
1807 bool "Export atags in procfs"
1811 Should the atags used to boot the kernel be exported in an "atags"
1812 file in procfs. Useful with kexec.
1815 bool "Build kdump crash kernel (EXPERIMENTAL)"
1816 depends on EXPERIMENTAL
1818 Generate crash dump after being started by kexec. This should
1819 be normally only set in special crash dump kernels which are
1820 loaded in the main kernel with kexec-tools into a specially
1821 reserved region and then later executed after a crash by
1822 kdump/kexec. The crash dump kernel must be compiled to a
1823 memory address not used by the main kernel
1825 For more details see Documentation/kdump/kdump.txt
1827 config AUTO_ZRELADDR
1828 bool "Auto calculation of the decompressed kernel image address"
1829 depends on !ZBOOT_ROM && !ARCH_U300
1831 ZRELADDR is the physical address where the decompressed kernel
1832 image will be placed. If AUTO_ZRELADDR is selected, the address
1833 will be determined at run-time by masking the current IP with
1834 0xf8000000. This assumes the zImage being placed in the first 128MB
1835 from start of memory.
1839 menu "CPU Power Management"
1843 source "drivers/cpufreq/Kconfig"
1846 tristate "CPUfreq driver for i.MX CPUs"
1847 depends on ARCH_MXC && CPU_FREQ
1849 This enables the CPUfreq driver for i.MX CPUs.
1851 config CPU_FREQ_SA1100
1854 config CPU_FREQ_SA1110
1857 config CPU_FREQ_INTEGRATOR
1858 tristate "CPUfreq driver for ARM Integrator CPUs"
1859 depends on ARCH_INTEGRATOR && CPU_FREQ
1862 This enables the CPUfreq driver for ARM Integrator CPUs.
1864 For details, take a look at <file:Documentation/cpu-freq>.
1870 depends on CPU_FREQ && ARCH_PXA && PXA25x
1872 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1874 config CPU_FREQ_S3C64XX
1875 bool "CPUfreq support for Samsung S3C64XX CPUs"
1876 depends on CPU_FREQ && CPU_S3C6410
1881 Internal configuration node for common cpufreq on Samsung SoC
1883 config CPU_FREQ_S3C24XX
1884 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1885 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1888 This enables the CPUfreq driver for the Samsung S3C24XX family
1891 For details, take a look at <file:Documentation/cpu-freq>.
1895 config CPU_FREQ_S3C24XX_PLL
1896 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1897 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1899 Compile in support for changing the PLL frequency from the
1900 S3C24XX series CPUfreq driver. The PLL takes time to settle
1901 after a frequency change, so by default it is not enabled.
1903 This also means that the PLL tables for the selected CPU(s) will
1904 be built which may increase the size of the kernel image.
1906 config CPU_FREQ_S3C24XX_DEBUG
1907 bool "Debug CPUfreq Samsung driver core"
1908 depends on CPU_FREQ_S3C24XX
1910 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1912 config CPU_FREQ_S3C24XX_IODEBUG
1913 bool "Debug CPUfreq Samsung driver IO timing"
1914 depends on CPU_FREQ_S3C24XX
1916 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1918 config CPU_FREQ_S3C24XX_DEBUGFS
1919 bool "Export debugfs for CPUFreq"
1920 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1922 Export status information via debugfs.
1926 source "drivers/cpuidle/Kconfig"
1930 menu "Floating point emulation"
1932 comment "At least one emulation must be selected"
1935 bool "NWFPE math emulation"
1936 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1938 Say Y to include the NWFPE floating point emulator in the kernel.
1939 This is necessary to run most binaries. Linux does not currently
1940 support floating point hardware so you need to say Y here even if
1941 your machine has an FPA or floating point co-processor podule.
1943 You may say N here if you are going to load the Acorn FPEmulator
1944 early in the bootup.
1947 bool "Support extended precision"
1948 depends on FPE_NWFPE
1950 Say Y to include 80-bit support in the kernel floating-point
1951 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1952 Note that gcc does not generate 80-bit operations by default,
1953 so in most cases this option only enlarges the size of the
1954 floating point emulator without any good reason.
1956 You almost surely want to say N here.
1959 bool "FastFPE math emulation (EXPERIMENTAL)"
1960 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1962 Say Y here to include the FAST floating point emulator in the kernel.
1963 This is an experimental much faster emulator which now also has full
1964 precision for the mantissa. It does not support any exceptions.
1965 It is very simple, and approximately 3-6 times faster than NWFPE.
1967 It should be sufficient for most programs. It may be not suitable
1968 for scientific calculations, but you have to check this for yourself.
1969 If you do not feel you need a faster FP emulation you should better
1973 bool "VFP-format floating point maths"
1974 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1976 Say Y to include VFP support code in the kernel. This is needed
1977 if your hardware includes a VFP unit.
1979 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1980 release notes and additional status information.
1982 Say N if your target does not have VFP hardware.
1990 bool "Advanced SIMD (NEON) Extension support"
1991 depends on VFPv3 && CPU_V7
1993 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1998 menu "Userspace binary formats"
2000 source "fs/Kconfig.binfmt"
2003 tristate "RISC OS personality"
2006 Say Y here to include the kernel code necessary if you want to run
2007 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2008 experimental; if this sounds frightening, say N and sleep in peace.
2009 You can also say M here to compile this support as a module (which
2010 will be called arthur).
2014 menu "Power management options"
2016 source "kernel/power/Kconfig"
2018 config ARCH_SUSPEND_POSSIBLE
2019 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2020 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2021 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2026 source "net/Kconfig"
2028 source "drivers/Kconfig"
2032 source "arch/arm/Kconfig.debug"
2034 source "security/Kconfig"
2036 source "crypto/Kconfig"
2038 source "lib/Kconfig"