1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_MEMBARRIER_SYNC_CORE
13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
14 select ARCH_HAS_PHYS_TO_DMA
15 select ARCH_HAS_SET_MEMORY
16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
17 select ARCH_HAS_STRICT_MODULE_RWX if MMU
18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
19 select ARCH_HAVE_CUSTOM_GPIO_H
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_MIGHT_HAVE_PC_PARPORT
22 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
23 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
24 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
25 select ARCH_SUPPORTS_ATOMIC_RMW
26 select ARCH_USE_BUILTIN_BSWAP
27 select ARCH_USE_CMPXCHG_LOCKREF
28 select ARCH_WANT_IPC_PARSE_VERSION
29 select BUILDTIME_EXTABLE_SORT if MMU
30 select CLONE_BACKWARDS
31 select CPU_PM if SUSPEND || CPU_IDLE
32 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
33 select DMA_REMAP if MMU
35 select EDAC_ATOMIC_SCRUB
36 select GENERIC_ALLOCATOR
37 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
38 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
39 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
40 select GENERIC_CPU_AUTOPROBE
41 select GENERIC_EARLY_IOREMAP
42 select GENERIC_IDLE_POLL_SETUP
43 select GENERIC_IRQ_PROBE
44 select GENERIC_IRQ_SHOW
45 select GENERIC_IRQ_SHOW_LEVEL
46 select GENERIC_PCI_IOMAP
47 select GENERIC_SCHED_CLOCK
48 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select HANDLE_DOMAIN_IRQ
52 select HARDIRQS_SW_RESEND
53 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
54 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
55 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
56 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
57 select HAVE_ARCH_MMAP_RND_BITS if MMU
58 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
59 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
60 select HAVE_ARCH_TRACEHOOK
61 select HAVE_ARM_SMCCC if CPU_V7
62 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
63 select HAVE_CONTEXT_TRACKING
64 select HAVE_C_RECORDMCOUNT
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DMA_CONTIGUOUS if MMU
67 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
68 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
69 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
70 select HAVE_EXIT_THREAD
71 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
72 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL
73 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
74 select HAVE_GCC_PLUGINS
75 select HAVE_GENERIC_DMA_COHERENT
76 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
77 select HAVE_IDE if PCI || ISA || PCMCIA
78 select HAVE_IRQ_TIME_ACCOUNTING
79 select HAVE_KERNEL_GZIP
80 select HAVE_KERNEL_LZ4
81 select HAVE_KERNEL_LZMA
82 select HAVE_KERNEL_LZO
84 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
85 select HAVE_KRETPROBES if HAVE_KPROBES
86 select HAVE_MOD_ARCH_SPECIFIC
88 select HAVE_OPROFILE if HAVE_PERF_EVENTS
89 select HAVE_OPTPROBES if !THUMB2_KERNEL
90 select HAVE_PERF_EVENTS
92 select HAVE_PERF_USER_STACK_DUMP
93 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
94 select HAVE_REGS_AND_STACK_ACCESS_API
96 select HAVE_STACKPROTECTOR
97 select HAVE_SYSCALL_TRACEPOINTS
99 select HAVE_VIRT_CPU_ACCOUNTING_GEN
100 select IRQ_FORCED_THREADING
101 select MODULES_USE_ELF_REL
102 select NEED_DMA_MAP_STATE
103 select OF_EARLY_FLATTREE if OF
104 select OF_RESERVED_MEM if OF
106 select OLD_SIGSUSPEND3
107 select PCI_SYSCALL if PCI
108 select PERF_USE_VMALLOC
111 select SYS_SUPPORTS_APM_EMULATION
112 # Above selects are sorted alphabetically; please add new ones
113 # according to that. Thanks.
115 The ARM series is a line of low-power-consumption RISC chip designs
116 licensed by ARM Ltd and targeted at embedded applications and
117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
118 manufactured, but legacy ARM-based PC hardware remains popular in
119 Europe. There is an ARM Linux project with a web page at
120 <http://www.arm.linux.org.uk/>.
122 config ARM_HAS_SG_CHAIN
125 config ARM_DMA_USE_IOMMU
127 select ARM_HAS_SG_CHAIN
128 select NEED_SG_DMA_LENGTH
132 config ARM_DMA_IOMMU_ALIGNMENT
133 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
137 DMA mapping framework by default aligns all buffers to the smallest
138 PAGE_SIZE order which is greater than or equal to the requested buffer
139 size. This works well for buffers up to a few hundreds kilobytes, but
140 for larger buffers it just a waste of address space. Drivers which has
141 relatively small addressing window (like 64Mib) might run out of
142 virtual space with just a few allocations.
144 With this parameter you can specify the maximum PAGE_SIZE order for
145 DMA IOMMU buffers. Larger buffers will be aligned only to this
146 specified order. The order is expressed as a power of two multiplied
151 config SYS_SUPPORTS_APM_EMULATION
156 select GENERIC_ALLOCATOR
167 config STACKTRACE_SUPPORT
171 config LOCKDEP_SUPPORT
175 config TRACE_IRQFLAGS_SUPPORT
179 config RWSEM_XCHGADD_ALGORITHM
183 config ARCH_HAS_ILOG2_U32
186 config ARCH_HAS_ILOG2_U64
189 config ARCH_HAS_BANDGAP
192 config FIX_EARLYCON_MEM
195 config GENERIC_HWEIGHT
199 config GENERIC_CALIBRATE_DELAY
203 config ARCH_MAY_HAVE_PC_FDC
209 config ARCH_SUPPORTS_UPROBES
212 config ARCH_HAS_DMA_SET_COHERENT_MASK
215 config GENERIC_ISA_DMA
221 config NEED_RET_TO_USER
227 config ARM_PATCH_PHYS_VIRT
228 bool "Patch physical to virtual translations at runtime" if EMBEDDED
230 depends on !XIP_KERNEL && MMU
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT
260 default DRAM_BASE if !MMU
261 default 0x00000000 if ARCH_EBSA110 || \
267 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
268 default 0x20000000 if ARCH_S5PV210
269 default 0xc0000000 if ARCH_SA1100
271 Please provide the physical address corresponding to the
272 location of main memory in your system.
278 config PGTABLE_LEVELS
280 default 3 if ARM_LPAE
286 bool "MMU-based Paged Memory Management Support"
289 Select if you want MMU-based virtualised addressing space
290 support by paged memory management. If unsure, say 'Y'.
292 config ARCH_MMAP_RND_BITS_MIN
295 config ARCH_MMAP_RND_BITS_MAX
296 default 14 if PAGE_OFFSET=0x40000000
297 default 15 if PAGE_OFFSET=0x80000000
301 # The "ARM system type" choice list is ordered alphabetically by option
302 # text. Please add new entries in the option alphabetic order.
305 prompt "ARM system type"
306 default ARM_SINGLE_ARMV7M if !MMU
307 default ARCH_MULTIPLATFORM if MMU
309 config ARCH_MULTIPLATFORM
310 bool "Allow multiple platforms to be selected"
312 select ARM_HAS_SG_CHAIN
313 select ARM_PATCH_PHYS_VIRT
317 select GENERIC_CLOCKEVENTS
318 select GENERIC_IRQ_MULTI_HANDLER
320 select PCI_DOMAINS_GENERIC if PCI
324 config ARM_SINGLE_ARMV7M
325 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
332 select GENERIC_CLOCKEVENTS
339 select ARCH_USES_GETTIMEOFFSET
342 select NEED_MACH_IO_H
343 select NEED_MACH_MEMORY_H
346 This is an evaluation board for the StrongARM processor available
347 from Digital. It has limited hardware on-board, including an
348 Ethernet interface, two PCMCIA sockets, two serial ports and a
353 select ARCH_SPARSEMEM_ENABLE
355 imply ARM_PATCH_PHYS_VIRT
361 select GENERIC_CLOCKEVENTS
364 This enables support for the Cirrus EP93xx series of CPUs.
366 config ARCH_FOOTBRIDGE
370 select GENERIC_CLOCKEVENTS
372 select NEED_MACH_IO_H if !MMU
373 select NEED_MACH_MEMORY_H
375 Support for systems based on the DC21285 companion chip
376 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
379 bool "Hilscher NetX based"
383 select GENERIC_CLOCKEVENTS
385 This enables support for systems based on the Hilscher NetX Soc
391 select NEED_MACH_MEMORY_H
392 select NEED_RET_TO_USER
398 Support for Intel's IOP13XX (XScale) family of processors.
406 select NEED_RET_TO_USER
410 Support for Intel's 80219 and IOP32X (XScale) family of
419 select NEED_RET_TO_USER
423 Support for Intel's IOP33X (XScale) family of processors.
428 select ARCH_HAS_DMA_SET_COHERENT_MASK
429 select ARCH_SUPPORTS_BIG_ENDIAN
432 select DMABOUNCE if PCI
433 select GENERIC_CLOCKEVENTS
436 select NEED_MACH_IO_H
437 select USB_EHCI_BIG_ENDIAN_DESC
438 select USB_EHCI_BIG_ENDIAN_MMIO
440 Support for Intel's IXP4XX (XScale) family of processors.
445 select GENERIC_CLOCKEVENTS
446 select GENERIC_IRQ_MULTI_HANDLER
452 select PLAT_ORION_LEGACY
454 select PM_GENERIC_DOMAINS if PM
456 Support for the Marvell Dove SoC 88AP510
459 bool "Micrel/Kendin KS8695"
462 select GENERIC_CLOCKEVENTS
464 select NEED_MACH_MEMORY_H
466 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
467 System-on-Chip devices.
470 bool "Nuvoton W90X900 CPU"
474 select GENERIC_CLOCKEVENTS
477 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
478 At present, the w90x900 has been renamed nuc900, regarding
479 the ARM series product line, you can login the following
480 link address to know more.
482 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
483 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
489 select CLKSRC_LPC32XX
492 select GENERIC_CLOCKEVENTS
493 select GENERIC_IRQ_MULTI_HANDLER
498 Support for the NXP LPC32XX family of processors
501 bool "PXA2xx/PXA3xx-based"
504 select ARM_CPU_SUSPEND if PM
511 select CPU_XSCALE if !CPU_XSC3
512 select GENERIC_CLOCKEVENTS
513 select GENERIC_IRQ_MULTI_HANDLER
521 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
527 select ARCH_MAY_HAVE_PC_FDC
528 select ARCH_SPARSEMEM_ENABLE
529 select ARCH_USES_GETTIMEOFFSET
533 select HAVE_PATA_PLATFORM
535 select NEED_MACH_IO_H
536 select NEED_MACH_MEMORY_H
539 On the Acorn Risc-PC, Linux can support the internal IDE disk and
540 CD-ROM interface, serial and parallel port, and the floppy drive.
545 select ARCH_SPARSEMEM_ENABLE
549 select TIMER_OF if OF
552 select GENERIC_CLOCKEVENTS
553 select GENERIC_IRQ_MULTI_HANDLER
558 select NEED_MACH_MEMORY_H
561 Support for StrongARM 11x0 based boards.
564 bool "Samsung S3C24XX SoCs"
567 select CLKSRC_SAMSUNG_PWM
568 select GENERIC_CLOCKEVENTS
571 select GENERIC_IRQ_MULTI_HANDLER
572 select HAVE_S3C2410_I2C if I2C
573 select HAVE_S3C2410_WATCHDOG if WATCHDOG
574 select HAVE_S3C_RTC if RTC_CLASS
575 select NEED_MACH_IO_H
579 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
580 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
581 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
582 Samsung SMDK2410 development board (and derivatives).
586 select ARCH_HAS_HOLES_MEMORYMODEL
589 select GENERIC_ALLOCATOR
590 select GENERIC_CLOCKEVENTS
591 select GENERIC_IRQ_CHIP
594 select PM_GENERIC_DOMAINS if PM
595 select PM_GENERIC_DOMAINS_OF if PM && OF
596 select RESET_CONTROLLER
600 Support for TI's DaVinci platform.
605 select ARCH_HAS_HOLES_MEMORYMODEL
609 select GENERIC_CLOCKEVENTS
610 select GENERIC_IRQ_CHIP
611 select GENERIC_IRQ_MULTI_HANDLER
615 select NEED_MACH_IO_H if PCCARD
616 select NEED_MACH_MEMORY_H
619 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
623 menu "Multiple platform selection"
624 depends on ARCH_MULTIPLATFORM
626 comment "CPU Core family selection"
629 bool "ARMv4 based platforms (FA526)"
630 depends on !ARCH_MULTI_V6_V7
631 select ARCH_MULTI_V4_V5
634 config ARCH_MULTI_V4T
635 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
636 depends on !ARCH_MULTI_V6_V7
637 select ARCH_MULTI_V4_V5
638 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
639 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
640 CPU_ARM925T || CPU_ARM940T)
643 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
644 depends on !ARCH_MULTI_V6_V7
645 select ARCH_MULTI_V4_V5
646 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
647 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
648 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
650 config ARCH_MULTI_V4_V5
654 bool "ARMv6 based platforms (ARM11)"
655 select ARCH_MULTI_V6_V7
659 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
661 select ARCH_MULTI_V6_V7
665 config ARCH_MULTI_V6_V7
667 select MIGHT_HAVE_CACHE_L2X0
669 config ARCH_MULTI_CPU_AUTO
670 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
676 bool "Dummy Virtual Machine"
677 depends on ARCH_MULTI_V7
680 select ARM_GIC_V2M if PCI
682 select ARM_GIC_V3_ITS if PCI
684 select HAVE_ARM_ARCH_TIMER
685 select ARCH_SUPPORTS_BIG_ENDIAN
688 # This is sorted alphabetically by mach-* pathname. However, plat-*
689 # Kconfigs may be included either alphabetically (according to the
690 # plat- suffix) or along side the corresponding mach-* source.
692 source "arch/arm/mach-actions/Kconfig"
694 source "arch/arm/mach-alpine/Kconfig"
696 source "arch/arm/mach-artpec/Kconfig"
698 source "arch/arm/mach-asm9260/Kconfig"
700 source "arch/arm/mach-aspeed/Kconfig"
702 source "arch/arm/mach-at91/Kconfig"
704 source "arch/arm/mach-axxia/Kconfig"
706 source "arch/arm/mach-bcm/Kconfig"
708 source "arch/arm/mach-berlin/Kconfig"
710 source "arch/arm/mach-clps711x/Kconfig"
712 source "arch/arm/mach-cns3xxx/Kconfig"
714 source "arch/arm/mach-davinci/Kconfig"
716 source "arch/arm/mach-digicolor/Kconfig"
718 source "arch/arm/mach-dove/Kconfig"
720 source "arch/arm/mach-ep93xx/Kconfig"
722 source "arch/arm/mach-exynos/Kconfig"
723 source "arch/arm/plat-samsung/Kconfig"
725 source "arch/arm/mach-footbridge/Kconfig"
727 source "arch/arm/mach-gemini/Kconfig"
729 source "arch/arm/mach-highbank/Kconfig"
731 source "arch/arm/mach-hisi/Kconfig"
733 source "arch/arm/mach-imx/Kconfig"
735 source "arch/arm/mach-integrator/Kconfig"
737 source "arch/arm/mach-iop13xx/Kconfig"
739 source "arch/arm/mach-iop32x/Kconfig"
741 source "arch/arm/mach-iop33x/Kconfig"
743 source "arch/arm/mach-ixp4xx/Kconfig"
745 source "arch/arm/mach-keystone/Kconfig"
747 source "arch/arm/mach-ks8695/Kconfig"
749 source "arch/arm/mach-mediatek/Kconfig"
751 source "arch/arm/mach-meson/Kconfig"
753 source "arch/arm/mach-mmp/Kconfig"
755 source "arch/arm/mach-moxart/Kconfig"
757 source "arch/arm/mach-mv78xx0/Kconfig"
759 source "arch/arm/mach-mvebu/Kconfig"
761 source "arch/arm/mach-mxs/Kconfig"
763 source "arch/arm/mach-netx/Kconfig"
765 source "arch/arm/mach-nomadik/Kconfig"
767 source "arch/arm/mach-npcm/Kconfig"
769 source "arch/arm/mach-nspire/Kconfig"
771 source "arch/arm/plat-omap/Kconfig"
773 source "arch/arm/mach-omap1/Kconfig"
775 source "arch/arm/mach-omap2/Kconfig"
777 source "arch/arm/mach-orion5x/Kconfig"
779 source "arch/arm/mach-oxnas/Kconfig"
781 source "arch/arm/mach-picoxcell/Kconfig"
783 source "arch/arm/mach-prima2/Kconfig"
785 source "arch/arm/mach-pxa/Kconfig"
786 source "arch/arm/plat-pxa/Kconfig"
788 source "arch/arm/mach-qcom/Kconfig"
790 source "arch/arm/mach-rda/Kconfig"
792 source "arch/arm/mach-realview/Kconfig"
794 source "arch/arm/mach-rockchip/Kconfig"
796 source "arch/arm/mach-s3c24xx/Kconfig"
798 source "arch/arm/mach-s3c64xx/Kconfig"
800 source "arch/arm/mach-s5pv210/Kconfig"
802 source "arch/arm/mach-sa1100/Kconfig"
804 source "arch/arm/mach-shmobile/Kconfig"
806 source "arch/arm/mach-socfpga/Kconfig"
808 source "arch/arm/mach-spear/Kconfig"
810 source "arch/arm/mach-sti/Kconfig"
812 source "arch/arm/mach-stm32/Kconfig"
814 source "arch/arm/mach-sunxi/Kconfig"
816 source "arch/arm/mach-tango/Kconfig"
818 source "arch/arm/mach-tegra/Kconfig"
820 source "arch/arm/mach-u300/Kconfig"
822 source "arch/arm/mach-uniphier/Kconfig"
824 source "arch/arm/mach-ux500/Kconfig"
826 source "arch/arm/mach-versatile/Kconfig"
828 source "arch/arm/mach-vexpress/Kconfig"
829 source "arch/arm/plat-versatile/Kconfig"
831 source "arch/arm/mach-vt8500/Kconfig"
833 source "arch/arm/mach-w90x900/Kconfig"
835 source "arch/arm/mach-zx/Kconfig"
837 source "arch/arm/mach-zynq/Kconfig"
839 # ARMv7-M architecture
841 bool "Energy Micro efm32"
842 depends on ARM_SINGLE_ARMV7M
845 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
849 bool "NXP LPC18xx/LPC43xx"
850 depends on ARM_SINGLE_ARMV7M
851 select ARCH_HAS_RESET_CONTROLLER
853 select CLKSRC_LPC32XX
856 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
857 high performance microcontrollers.
860 bool "ARM MPS2 platform"
861 depends on ARM_SINGLE_ARMV7M
865 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
866 with a range of available cores like Cortex-M3/M4/M7.
868 Please, note that depends which Application Note is used memory map
869 for the platform may vary, so adjustment of RAM base might be needed.
871 # Definitions to make life easier
877 select GENERIC_CLOCKEVENTS
883 select GENERIC_IRQ_CHIP
886 config PLAT_ORION_LEGACY
893 config PLAT_VERSATILE
896 source "arch/arm/firmware/Kconfig"
898 source "arch/arm/mm/Kconfig"
901 bool "Enable iWMMXt support"
902 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
903 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
905 Enable support for iWMMXt context switching at run time if
906 running on a CPU that supports it.
909 source "arch/arm/Kconfig-nommu"
912 config PJ4B_ERRATA_4742
913 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
914 depends on CPU_PJ4B && MACH_ARMADA_370
917 When coming out of either a Wait for Interrupt (WFI) or a Wait for
918 Event (WFE) IDLE states, a specific timing sensitivity exists between
919 the retiring WFI/WFE instructions and the newly issued subsequent
920 instructions. This sensitivity can result in a CPU hang scenario.
922 The software must insert either a Data Synchronization Barrier (DSB)
923 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
926 config ARM_ERRATA_326103
927 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
930 Executing a SWP instruction to read-only memory does not set bit 11
931 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
932 treat the access as a read, preventing a COW from occurring and
933 causing the faulting task to livelock.
935 config ARM_ERRATA_411920
936 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
937 depends on CPU_V6 || CPU_V6K
939 Invalidation of the Instruction Cache operation can
940 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
941 It does not affect the MPCore. This option enables the ARM Ltd.
942 recommended workaround.
944 config ARM_ERRATA_430973
945 bool "ARM errata: Stale prediction on replaced interworking branch"
948 This option enables the workaround for the 430973 Cortex-A8
949 r1p* erratum. If a code sequence containing an ARM/Thumb
950 interworking branch is replaced with another code sequence at the
951 same virtual address, whether due to self-modifying code or virtual
952 to physical address re-mapping, Cortex-A8 does not recover from the
953 stale interworking branch prediction. This results in Cortex-A8
954 executing the new code sequence in the incorrect ARM or Thumb state.
955 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
956 and also flushes the branch target cache at every context switch.
957 Note that setting specific bits in the ACTLR register may not be
958 available in non-secure mode.
960 config ARM_ERRATA_458693
961 bool "ARM errata: Processor deadlock when a false hazard is created"
963 depends on !ARCH_MULTIPLATFORM
965 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
966 erratum. For very specific sequences of memory operations, it is
967 possible for a hazard condition intended for a cache line to instead
968 be incorrectly associated with a different cache line. This false
969 hazard might then cause a processor deadlock. The workaround enables
970 the L1 caching of the NEON accesses and disables the PLD instruction
971 in the ACTLR register. Note that setting specific bits in the ACTLR
972 register may not be available in non-secure mode.
974 config ARM_ERRATA_460075
975 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
977 depends on !ARCH_MULTIPLATFORM
979 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
980 erratum. Any asynchronous access to the L2 cache may encounter a
981 situation in which recent store transactions to the L2 cache are lost
982 and overwritten with stale memory contents from external memory. The
983 workaround disables the write-allocate mode for the L2 cache via the
984 ACTLR register. Note that setting specific bits in the ACTLR register
985 may not be available in non-secure mode.
987 config ARM_ERRATA_742230
988 bool "ARM errata: DMB operation may be faulty"
989 depends on CPU_V7 && SMP
990 depends on !ARCH_MULTIPLATFORM
992 This option enables the workaround for the 742230 Cortex-A9
993 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
994 between two write operations may not ensure the correct visibility
995 ordering of the two writes. This workaround sets a specific bit in
996 the diagnostic register of the Cortex-A9 which causes the DMB
997 instruction to behave as a DSB, ensuring the correct behaviour of
1000 config ARM_ERRATA_742231
1001 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1002 depends on CPU_V7 && SMP
1003 depends on !ARCH_MULTIPLATFORM
1005 This option enables the workaround for the 742231 Cortex-A9
1006 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1007 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1008 accessing some data located in the same cache line, may get corrupted
1009 data due to bad handling of the address hazard when the line gets
1010 replaced from one of the CPUs at the same time as another CPU is
1011 accessing it. This workaround sets specific bits in the diagnostic
1012 register of the Cortex-A9 which reduces the linefill issuing
1013 capabilities of the processor.
1015 config ARM_ERRATA_643719
1016 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1017 depends on CPU_V7 && SMP
1020 This option enables the workaround for the 643719 Cortex-A9 (prior to
1021 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1022 register returns zero when it should return one. The workaround
1023 corrects this value, ensuring cache maintenance operations which use
1024 it behave as intended and avoiding data corruption.
1026 config ARM_ERRATA_720789
1027 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1030 This option enables the workaround for the 720789 Cortex-A9 (prior to
1031 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1032 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1033 As a consequence of this erratum, some TLB entries which should be
1034 invalidated are not, resulting in an incoherency in the system page
1035 tables. The workaround changes the TLB flushing routines to invalidate
1036 entries regardless of the ASID.
1038 config ARM_ERRATA_743622
1039 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1041 depends on !ARCH_MULTIPLATFORM
1043 This option enables the workaround for the 743622 Cortex-A9
1044 (r2p*) erratum. Under very rare conditions, a faulty
1045 optimisation in the Cortex-A9 Store Buffer may lead to data
1046 corruption. This workaround sets a specific bit in the diagnostic
1047 register of the Cortex-A9 which disables the Store Buffer
1048 optimisation, preventing the defect from occurring. This has no
1049 visible impact on the overall performance or power consumption of the
1052 config ARM_ERRATA_751472
1053 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1055 depends on !ARCH_MULTIPLATFORM
1057 This option enables the workaround for the 751472 Cortex-A9 (prior
1058 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1059 completion of a following broadcasted operation if the second
1060 operation is received by a CPU before the ICIALLUIS has completed,
1061 potentially leading to corrupted entries in the cache or TLB.
1063 config ARM_ERRATA_754322
1064 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1067 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1068 r3p*) erratum. A speculative memory access may cause a page table walk
1069 which starts prior to an ASID switch but completes afterwards. This
1070 can populate the micro-TLB with a stale entry which may be hit with
1071 the new ASID. This workaround places two dsb instructions in the mm
1072 switching code so that no page table walks can cross the ASID switch.
1074 config ARM_ERRATA_754327
1075 bool "ARM errata: no automatic Store Buffer drain"
1076 depends on CPU_V7 && SMP
1078 This option enables the workaround for the 754327 Cortex-A9 (prior to
1079 r2p0) erratum. The Store Buffer does not have any automatic draining
1080 mechanism and therefore a livelock may occur if an external agent
1081 continuously polls a memory location waiting to observe an update.
1082 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1083 written polling loops from denying visibility of updates to memory.
1085 config ARM_ERRATA_364296
1086 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1089 This options enables the workaround for the 364296 ARM1136
1090 r0p2 erratum (possible cache data corruption with
1091 hit-under-miss enabled). It sets the undocumented bit 31 in
1092 the auxiliary control register and the FI bit in the control
1093 register, thus disabling hit-under-miss without putting the
1094 processor into full low interrupt latency mode. ARM11MPCore
1097 config ARM_ERRATA_764369
1098 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1099 depends on CPU_V7 && SMP
1101 This option enables the workaround for erratum 764369
1102 affecting Cortex-A9 MPCore with two or more processors (all
1103 current revisions). Under certain timing circumstances, a data
1104 cache line maintenance operation by MVA targeting an Inner
1105 Shareable memory region may fail to proceed up to either the
1106 Point of Coherency or to the Point of Unification of the
1107 system. This workaround adds a DSB instruction before the
1108 relevant cache maintenance functions and sets a specific bit
1109 in the diagnostic control register of the SCU.
1111 config ARM_ERRATA_775420
1112 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1115 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1116 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1117 operation aborts with MMU exception, it might cause the processor
1118 to deadlock. This workaround puts DSB before executing ISB if
1119 an abort may occur on cache maintenance.
1121 config ARM_ERRATA_798181
1122 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1123 depends on CPU_V7 && SMP
1125 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1126 adequately shooting down all use of the old entries. This
1127 option enables the Linux kernel workaround for this erratum
1128 which sends an IPI to the CPUs that are running the same ASID
1129 as the one being invalidated.
1131 config ARM_ERRATA_773022
1132 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1135 This option enables the workaround for the 773022 Cortex-A15
1136 (up to r0p4) erratum. In certain rare sequences of code, the
1137 loop buffer may deliver incorrect instructions. This
1138 workaround disables the loop buffer to avoid the erratum.
1140 config ARM_ERRATA_818325_852422
1141 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1144 This option enables the workaround for:
1145 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1146 instruction might deadlock. Fixed in r0p1.
1147 - Cortex-A12 852422: Execution of a sequence of instructions might
1148 lead to either a data corruption or a CPU deadlock. Not fixed in
1149 any Cortex-A12 cores yet.
1150 This workaround for all both errata involves setting bit[12] of the
1151 Feature Register. This bit disables an optimisation applied to a
1152 sequence of 2 instructions that use opposing condition codes.
1154 config ARM_ERRATA_821420
1155 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1158 This option enables the workaround for the 821420 Cortex-A12
1159 (all revs) erratum. In very rare timing conditions, a sequence
1160 of VMOV to Core registers instructions, for which the second
1161 one is in the shadow of a branch or abort, can lead to a
1162 deadlock when the VMOV instructions are issued out-of-order.
1164 config ARM_ERRATA_825619
1165 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1168 This option enables the workaround for the 825619 Cortex-A12
1169 (all revs) erratum. Within rare timing constraints, executing a
1170 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1171 and Device/Strongly-Ordered loads and stores might cause deadlock
1173 config ARM_ERRATA_852421
1174 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1177 This option enables the workaround for the 852421 Cortex-A17
1178 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1179 execution of a DMB ST instruction might fail to properly order
1180 stores from GroupA and stores from GroupB.
1182 config ARM_ERRATA_852423
1183 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1186 This option enables the workaround for:
1187 - Cortex-A17 852423: Execution of a sequence of instructions might
1188 lead to either a data corruption or a CPU deadlock. Not fixed in
1189 any Cortex-A17 cores yet.
1190 This is identical to Cortex-A12 erratum 852422. It is a separate
1191 config option from the A12 erratum due to the way errata are checked
1196 source "arch/arm/common/Kconfig"
1203 Find out whether you have ISA slots on your motherboard. ISA is the
1204 name of a bus system, i.e. the way the CPU talks to the other stuff
1205 inside your box. Other bus systems are PCI, EISA, MicroChannel
1206 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1207 newer boards don't support it. If you have ISA, say Y, otherwise N.
1209 # Select ISA DMA controller support
1214 # Select ISA DMA interface
1218 config PCI_NANOENGINE
1219 bool "BSE nanoEngine PCI support"
1220 depends on SA1100_NANOENGINE
1222 Enable PCI on the BSE nanoEngine board.
1224 config PCI_HOST_ITE8152
1226 depends on PCI && MACH_ARMCORE
1232 menu "Kernel Features"
1237 This option should be selected by machines which have an SMP-
1240 The only effect of this option is to make the SMP-related
1241 options available to the user for configuration.
1244 bool "Symmetric Multi-Processing"
1245 depends on CPU_V6K || CPU_V7
1246 depends on GENERIC_CLOCKEVENTS
1248 depends on MMU || ARM_MPU
1251 This enables support for systems with more than one CPU. If you have
1252 a system with only one CPU, say N. If you have a system with more
1253 than one CPU, say Y.
1255 If you say N here, the kernel will run on uni- and multiprocessor
1256 machines, but will use only one CPU of a multiprocessor machine. If
1257 you say Y here, the kernel will run on many, but not all,
1258 uniprocessor machines. On a uniprocessor machine, the kernel
1259 will run faster if you say N here.
1261 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1262 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1263 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1265 If you don't know what to do here, say N.
1268 bool "Allow booting SMP kernel on uniprocessor systems"
1269 depends on SMP && !XIP_KERNEL && MMU
1272 SMP kernels contain instructions which fail on non-SMP processors.
1273 Enabling this option allows the kernel to modify itself to make
1274 these instructions safe. Disabling it allows about 1K of space
1277 If you don't know what to do here, say Y.
1279 config ARM_CPU_TOPOLOGY
1280 bool "Support cpu topology definition"
1281 depends on SMP && CPU_V7
1284 Support ARM cpu topology definition. The MPIDR register defines
1285 affinity between processors which is then used to describe the cpu
1286 topology of an ARM System.
1289 bool "Multi-core scheduler support"
1290 depends on ARM_CPU_TOPOLOGY
1292 Multi-core scheduler support improves the CPU scheduler's decision
1293 making when dealing with multi-core CPU chips at a cost of slightly
1294 increased overhead in some places. If unsure say N here.
1297 bool "SMT scheduler support"
1298 depends on ARM_CPU_TOPOLOGY
1300 Improves the CPU scheduler's decision making when dealing with
1301 MultiThreading at a cost of slightly increased overhead in some
1302 places. If unsure say N here.
1307 This option enables support for the ARM system coherency unit
1309 config HAVE_ARM_ARCH_TIMER
1310 bool "Architected timer support"
1312 select ARM_ARCH_TIMER
1313 select GENERIC_CLOCKEVENTS
1315 This option enables support for the ARM architected timer
1319 select TIMER_OF if OF
1321 This options enables support for the ARM timer and watchdog unit
1324 bool "Multi-Cluster Power Management"
1325 depends on CPU_V7 && SMP
1327 This option provides the common power management infrastructure
1328 for (multi-)cluster based systems, such as big.LITTLE based
1331 config MCPM_QUAD_CLUSTER
1335 To avoid wasting resources unnecessarily, MCPM only supports up
1336 to 2 clusters by default.
1337 Platforms with 3 or 4 clusters that use MCPM must select this
1338 option to allow the additional clusters to be managed.
1341 bool "big.LITTLE support (Experimental)"
1342 depends on CPU_V7 && SMP
1345 This option enables support selections for the big.LITTLE
1346 system architecture.
1349 bool "big.LITTLE switcher support"
1350 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1353 The big.LITTLE "switcher" provides the core functionality to
1354 transparently handle transition between a cluster of A15's
1355 and a cluster of A7's in a big.LITTLE system.
1357 config BL_SWITCHER_DUMMY_IF
1358 tristate "Simple big.LITTLE switcher user interface"
1359 depends on BL_SWITCHER && DEBUG_KERNEL
1361 This is a simple and dummy char dev interface to control
1362 the big.LITTLE switcher core code. It is meant for
1363 debugging purposes only.
1366 prompt "Memory split"
1370 Select the desired split between kernel and user memory.
1372 If you are not absolutely sure what you are doing, leave this
1376 bool "3G/1G user/kernel split"
1377 config VMSPLIT_3G_OPT
1378 depends on !ARM_LPAE
1379 bool "3G/1G user/kernel split (for full 1G low memory)"
1381 bool "2G/2G user/kernel split"
1383 bool "1G/3G user/kernel split"
1388 default PHYS_OFFSET if !MMU
1389 default 0x40000000 if VMSPLIT_1G
1390 default 0x80000000 if VMSPLIT_2G
1391 default 0xB0000000 if VMSPLIT_3G_OPT
1395 int "Maximum number of CPUs (2-32)"
1401 bool "Support for hot-pluggable CPUs"
1403 select GENERIC_IRQ_MIGRATION
1405 Say Y here to experiment with turning CPUs off and on. CPUs
1406 can be controlled through /sys/devices/system/cpu.
1409 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1410 depends on HAVE_ARM_SMCCC
1413 Say Y here if you want Linux to communicate with system firmware
1414 implementing the PSCI specification for CPU-centric power
1415 management operations described in ARM document number ARM DEN
1416 0022A ("Power State Coordination Interface System Software on
1419 # The GPIO number here must be sorted by descending number. In case of
1420 # a multiplatform kernel, we just want the highest value required by the
1421 # selected platforms.
1424 default 2048 if ARCH_SOCFPGA
1425 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1427 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1428 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1429 default 416 if ARCH_SUNXI
1430 default 392 if ARCH_U8500
1431 default 352 if ARCH_VT8500
1432 default 288 if ARCH_ROCKCHIP
1433 default 264 if MACH_H4700
1436 Maximum number of GPIOs in the system.
1438 If unsure, leave the default value.
1442 default 200 if ARCH_EBSA110
1443 default 128 if SOC_AT91RM9200
1447 depends on HZ_FIXED = 0
1448 prompt "Timer frequency"
1472 default HZ_FIXED if HZ_FIXED != 0
1473 default 100 if HZ_100
1474 default 200 if HZ_200
1475 default 250 if HZ_250
1476 default 300 if HZ_300
1477 default 500 if HZ_500
1481 def_bool HIGH_RES_TIMERS
1483 config THUMB2_KERNEL
1484 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1485 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1486 default y if CPU_THUMBONLY
1489 By enabling this option, the kernel will be compiled in
1494 config THUMB2_AVOID_R_ARM_THM_JUMP11
1495 bool "Work around buggy Thumb-2 short branch relocations in gas"
1496 depends on THUMB2_KERNEL && MODULES
1499 Various binutils versions can resolve Thumb-2 branches to
1500 locally-defined, preemptible global symbols as short-range "b.n"
1501 branch instructions.
1503 This is a problem, because there's no guarantee the final
1504 destination of the symbol, or any candidate locations for a
1505 trampoline, are within range of the branch. For this reason, the
1506 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1507 relocation in modules at all, and it makes little sense to add
1510 The symptom is that the kernel fails with an "unsupported
1511 relocation" error when loading some modules.
1513 Until fixed tools are available, passing
1514 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1515 code which hits this problem, at the cost of a bit of extra runtime
1516 stack usage in some cases.
1518 The problem is described in more detail at:
1519 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1521 Only Thumb-2 kernels are affected.
1523 Unless you are sure your tools don't have this problem, say Y.
1525 config ARM_PATCH_IDIV
1526 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1527 depends on CPU_32v7 && !XIP_KERNEL
1530 The ARM compiler inserts calls to __aeabi_idiv() and
1531 __aeabi_uidiv() when it needs to perform division on signed
1532 and unsigned integers. Some v7 CPUs have support for the sdiv
1533 and udiv instructions that can be used to implement those
1536 Enabling this option allows the kernel to modify itself to
1537 replace the first two instructions of these library functions
1538 with the sdiv or udiv plus "bx lr" instructions when the CPU
1539 it is running on supports them. Typically this will be faster
1540 and less power intensive than running the original library
1541 code to do integer division.
1544 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1545 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1547 This option allows for the kernel to be compiled using the latest
1548 ARM ABI (aka EABI). This is only useful if you are using a user
1549 space environment that is also compiled with EABI.
1551 Since there are major incompatibilities between the legacy ABI and
1552 EABI, especially with regard to structure member alignment, this
1553 option also changes the kernel syscall calling convention to
1554 disambiguate both ABIs and allow for backward compatibility support
1555 (selected with CONFIG_OABI_COMPAT).
1557 To use this you need GCC version 4.0.0 or later.
1560 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1561 depends on AEABI && !THUMB2_KERNEL
1563 This option preserves the old syscall interface along with the
1564 new (ARM EABI) one. It also provides a compatibility layer to
1565 intercept syscalls that have structure arguments which layout
1566 in memory differs between the legacy ABI and the new ARM EABI
1567 (only for non "thumb" binaries). This option adds a tiny
1568 overhead to all syscalls and produces a slightly larger kernel.
1570 The seccomp filter system will not be available when this is
1571 selected, since there is no way yet to sensibly distinguish
1572 between calling conventions during filtering.
1574 If you know you'll be using only pure EABI user space then you
1575 can say N here. If this option is not selected and you attempt
1576 to execute a legacy ABI binary then the result will be
1577 UNPREDICTABLE (in fact it can be predicted that it won't work
1578 at all). If in doubt say N.
1580 config ARCH_HAS_HOLES_MEMORYMODEL
1583 config ARCH_SPARSEMEM_ENABLE
1586 config ARCH_SPARSEMEM_DEFAULT
1587 def_bool ARCH_SPARSEMEM_ENABLE
1589 config ARCH_SELECT_MEMORY_MODEL
1590 def_bool ARCH_SPARSEMEM_ENABLE
1592 config HAVE_ARCH_PFN_VALID
1593 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1595 config HAVE_GENERIC_GUP
1600 bool "High Memory Support"
1603 The address space of ARM processors is only 4 Gigabytes large
1604 and it has to accommodate user address space, kernel address
1605 space as well as some memory mapped IO. That means that, if you
1606 have a large amount of physical memory and/or IO, not all of the
1607 memory can be "permanently mapped" by the kernel. The physical
1608 memory that is not permanently mapped is called "high memory".
1610 Depending on the selected kernel/user memory split, minimum
1611 vmalloc space and actual amount of RAM, you may not need this
1612 option which should result in a slightly faster kernel.
1617 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1621 The VM uses one page of physical memory for each page table.
1622 For systems with a lot of processes, this can use a lot of
1623 precious low memory, eventually leading to low memory being
1624 consumed by page tables. Setting this option will allow
1625 user-space 2nd level page tables to reside in high memory.
1627 config CPU_SW_DOMAIN_PAN
1628 bool "Enable use of CPU domains to implement privileged no-access"
1629 depends on MMU && !ARM_LPAE
1632 Increase kernel security by ensuring that normal kernel accesses
1633 are unable to access userspace addresses. This can help prevent
1634 use-after-free bugs becoming an exploitable privilege escalation
1635 by ensuring that magic values (such as LIST_POISON) will always
1636 fault when dereferenced.
1638 CPUs with low-vector mappings use a best-efforts implementation.
1639 Their lower 1MB needs to remain accessible for the vectors, but
1640 the remainder of userspace will become appropriately inaccessible.
1642 config HW_PERF_EVENTS
1646 config SYS_SUPPORTS_HUGETLBFS
1650 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1654 config ARCH_WANT_GENERAL_HUGETLB
1657 config ARM_MODULE_PLTS
1658 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1662 Allocate PLTs when loading modules so that jumps and calls whose
1663 targets are too far away for their relative offsets to be encoded
1664 in the instructions themselves can be bounced via veneers in the
1665 module's PLT. This allows modules to be allocated in the generic
1666 vmalloc area after the dedicated module memory area has been
1667 exhausted. The modules will use slightly more memory, but after
1668 rounding up to page size, the actual memory footprint is usually
1671 Disabling this is usually safe for small single-platform
1672 configurations. If unsure, say y.
1674 config FORCE_MAX_ZONEORDER
1675 int "Maximum zone order"
1676 default "12" if SOC_AM33XX
1677 default "9" if SA1111 || ARCH_EFM32
1680 The kernel memory allocator divides physically contiguous memory
1681 blocks into "zones", where each zone is a power of two number of
1682 pages. This option selects the largest power of two that the kernel
1683 keeps in the memory allocator. If you need to allocate very large
1684 blocks of physically contiguous memory, then you may need to
1685 increase this value.
1687 This config option is actually maximum order plus one. For example,
1688 a value of 11 means that the largest free memory block is 2^10 pages.
1690 config ALIGNMENT_TRAP
1692 depends on CPU_CP15_MMU
1693 default y if !ARCH_EBSA110
1694 select HAVE_PROC_CPU if PROC_FS
1696 ARM processors cannot fetch/store information which is not
1697 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1698 address divisible by 4. On 32-bit ARM processors, these non-aligned
1699 fetch/store instructions will be emulated in software if you say
1700 here, which has a severe performance impact. This is necessary for
1701 correct operation of some network protocols. With an IP-only
1702 configuration it is safe to say N, otherwise say Y.
1704 config UACCESS_WITH_MEMCPY
1705 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1707 default y if CPU_FEROCEON
1709 Implement faster copy_to_user and clear_user methods for CPU
1710 cores where a 8-word STM instruction give significantly higher
1711 memory write throughput than a sequence of individual 32bit stores.
1713 A possible side effect is a slight increase in scheduling latency
1714 between threads sharing the same address space if they invoke
1715 such copy operations with large buffers.
1717 However, if the CPU data cache is using a write-allocate mode,
1718 this option is unlikely to provide any performance gain.
1722 prompt "Enable seccomp to safely compute untrusted bytecode"
1724 This kernel feature is useful for number crunching applications
1725 that may need to compute untrusted bytecode during their
1726 execution. By using pipes or other transports made available to
1727 the process as file descriptors supporting the read/write
1728 syscalls, it's possible to isolate those applications in
1729 their own address space using seccomp. Once seccomp is
1730 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1731 and the task is only allowed to execute a few safe syscalls
1732 defined by each seccomp mode.
1735 bool "Enable paravirtualization code"
1737 This changes the kernel so it can modify itself when it is run
1738 under a hypervisor, potentially improving performance significantly
1739 over full virtualization.
1741 config PARAVIRT_TIME_ACCOUNTING
1742 bool "Paravirtual steal time accounting"
1745 Select this option to enable fine granularity task steal time
1746 accounting. Time spent executing other tasks in parallel with
1747 the current vCPU is discounted from the vCPU power. To account for
1748 that, there can be a small performance impact.
1750 If in doubt, say N here.
1757 bool "Xen guest support on ARM"
1758 depends on ARM && AEABI && OF
1759 depends on CPU_V7 && !CPU_V6
1760 depends on !GENERIC_ATOMIC64
1762 select ARCH_DMA_ADDR_T_64BIT
1768 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1770 config STACKPROTECTOR_PER_TASK
1771 bool "Use a unique stack canary value for each task"
1772 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1773 select GCC_PLUGIN_ARM_SSP_PER_TASK
1776 Due to the fact that GCC uses an ordinary symbol reference from
1777 which to load the value of the stack canary, this value can only
1778 change at reboot time on SMP systems, and all tasks running in the
1779 kernel's address space are forced to use the same canary value for
1780 the entire duration that the system is up.
1782 Enable this option to switch to a different method that uses a
1783 different canary value for each task.
1790 bool "Flattened Device Tree support"
1794 Include support for flattened device tree machine descriptions.
1797 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1800 This is the traditional way of passing data to the kernel at boot
1801 time. If you are solely relying on the flattened device tree (or
1802 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1803 to remove ATAGS support from your kernel binary. If unsure,
1806 config DEPRECATED_PARAM_STRUCT
1807 bool "Provide old way to pass kernel parameters"
1810 This was deprecated in 2001 and announced to live on for 5 years.
1811 Some old boot loaders still use this way.
1813 # Compressed boot loader in ROM. Yes, we really want to ask about
1814 # TEXT and BSS so we preserve their values in the config files.
1815 config ZBOOT_ROM_TEXT
1816 hex "Compressed ROM boot loader base address"
1819 The physical address at which the ROM-able zImage is to be
1820 placed in the target. Platforms which normally make use of
1821 ROM-able zImage formats normally set this to a suitable
1822 value in their defconfig file.
1824 If ZBOOT_ROM is not enabled, this has no effect.
1826 config ZBOOT_ROM_BSS
1827 hex "Compressed ROM boot loader BSS address"
1830 The base address of an area of read/write memory in the target
1831 for the ROM-able zImage which must be available while the
1832 decompressor is running. It must be large enough to hold the
1833 entire decompressed kernel plus an additional 128 KiB.
1834 Platforms which normally make use of ROM-able zImage formats
1835 normally set this to a suitable value in their defconfig file.
1837 If ZBOOT_ROM is not enabled, this has no effect.
1840 bool "Compressed boot loader in ROM/flash"
1841 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1842 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1844 Say Y here if you intend to execute your compressed kernel image
1845 (zImage) directly from ROM or flash. If unsure, say N.
1847 config ARM_APPENDED_DTB
1848 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1851 With this option, the boot code will look for a device tree binary
1852 (DTB) appended to zImage
1853 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1855 This is meant as a backward compatibility convenience for those
1856 systems with a bootloader that can't be upgraded to accommodate
1857 the documented boot protocol using a device tree.
1859 Beware that there is very little in terms of protection against
1860 this option being confused by leftover garbage in memory that might
1861 look like a DTB header after a reboot if no actual DTB is appended
1862 to zImage. Do not leave this option active in a production kernel
1863 if you don't intend to always append a DTB. Proper passing of the
1864 location into r2 of a bootloader provided DTB is always preferable
1867 config ARM_ATAG_DTB_COMPAT
1868 bool "Supplement the appended DTB with traditional ATAG information"
1869 depends on ARM_APPENDED_DTB
1871 Some old bootloaders can't be updated to a DTB capable one, yet
1872 they provide ATAGs with memory configuration, the ramdisk address,
1873 the kernel cmdline string, etc. Such information is dynamically
1874 provided by the bootloader and can't always be stored in a static
1875 DTB. To allow a device tree enabled kernel to be used with such
1876 bootloaders, this option allows zImage to extract the information
1877 from the ATAG list and store it at run time into the appended DTB.
1880 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1881 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1883 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1884 bool "Use bootloader kernel arguments if available"
1886 Uses the command-line options passed by the boot loader instead of
1887 the device tree bootargs property. If the boot loader doesn't provide
1888 any, the device tree bootargs property will be used.
1890 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1891 bool "Extend with bootloader kernel arguments"
1893 The command-line arguments provided by the boot loader will be
1894 appended to the the device tree bootargs property.
1899 string "Default kernel command string"
1902 On some architectures (EBSA110 and CATS), there is currently no way
1903 for the boot loader to pass arguments to the kernel. For these
1904 architectures, you should supply some command-line options at build
1905 time by entering them here. As a minimum, you should specify the
1906 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1909 prompt "Kernel command line type" if CMDLINE != ""
1910 default CMDLINE_FROM_BOOTLOADER
1913 config CMDLINE_FROM_BOOTLOADER
1914 bool "Use bootloader kernel arguments if available"
1916 Uses the command-line options passed by the boot loader. If
1917 the boot loader doesn't provide any, the default kernel command
1918 string provided in CMDLINE will be used.
1920 config CMDLINE_EXTEND
1921 bool "Extend bootloader kernel arguments"
1923 The command-line arguments provided by the boot loader will be
1924 appended to the default kernel command string.
1926 config CMDLINE_FORCE
1927 bool "Always use the default kernel command string"
1929 Always use the default kernel command string, even if the boot
1930 loader passes other arguments to the kernel.
1931 This is useful if you cannot or don't want to change the
1932 command-line options your boot loader passes to the kernel.
1936 bool "Kernel Execute-In-Place from ROM"
1937 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1939 Execute-In-Place allows the kernel to run from non-volatile storage
1940 directly addressable by the CPU, such as NOR flash. This saves RAM
1941 space since the text section of the kernel is not loaded from flash
1942 to RAM. Read-write sections, such as the data section and stack,
1943 are still copied to RAM. The XIP kernel is not compressed since
1944 it has to run directly from flash, so it will take more space to
1945 store it. The flash address used to link the kernel object files,
1946 and for storing it, is configuration dependent. Therefore, if you
1947 say Y here, you must know the proper physical address where to
1948 store the kernel image depending on your own flash memory usage.
1950 Also note that the make target becomes "make xipImage" rather than
1951 "make zImage" or "make Image". The final kernel binary to put in
1952 ROM memory will be arch/arm/boot/xipImage.
1956 config XIP_PHYS_ADDR
1957 hex "XIP Kernel Physical Location"
1958 depends on XIP_KERNEL
1959 default "0x00080000"
1961 This is the physical address in your flash memory the kernel will
1962 be linked for and stored to. This address is dependent on your
1965 config XIP_DEFLATED_DATA
1966 bool "Store kernel .data section compressed in ROM"
1967 depends on XIP_KERNEL
1970 Before the kernel is actually executed, its .data section has to be
1971 copied to RAM from ROM. This option allows for storing that data
1972 in compressed form and decompressed to RAM rather than merely being
1973 copied, saving some precious ROM space. A possible drawback is a
1974 slightly longer boot delay.
1977 bool "Kexec system call (EXPERIMENTAL)"
1978 depends on (!SMP || PM_SLEEP_SMP)
1982 kexec is a system call that implements the ability to shutdown your
1983 current kernel, and to start another kernel. It is like a reboot
1984 but it is independent of the system firmware. And like a reboot
1985 you can start any kernel with it, not just Linux.
1987 It is an ongoing process to be certain the hardware in a machine
1988 is properly shutdown, so do not be surprised if this code does not
1989 initially work for you.
1992 bool "Export atags in procfs"
1993 depends on ATAGS && KEXEC
1996 Should the atags used to boot the kernel be exported in an "atags"
1997 file in procfs. Useful with kexec.
2000 bool "Build kdump crash kernel (EXPERIMENTAL)"
2002 Generate crash dump after being started by kexec. This should
2003 be normally only set in special crash dump kernels which are
2004 loaded in the main kernel with kexec-tools into a specially
2005 reserved region and then later executed after a crash by
2006 kdump/kexec. The crash dump kernel must be compiled to a
2007 memory address not used by the main kernel
2009 For more details see Documentation/kdump/kdump.txt
2011 config AUTO_ZRELADDR
2012 bool "Auto calculation of the decompressed kernel image address"
2014 ZRELADDR is the physical address where the decompressed kernel
2015 image will be placed. If AUTO_ZRELADDR is selected, the address
2016 will be determined at run-time by masking the current IP with
2017 0xf8000000. This assumes the zImage being placed in the first 128MB
2018 from start of memory.
2024 bool "UEFI runtime support"
2025 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2027 select EFI_PARAMS_FROM_FDT
2030 select EFI_RUNTIME_WRAPPERS
2032 This option provides support for runtime services provided
2033 by UEFI firmware (such as non-volatile variables, realtime
2034 clock, and platform reset). A UEFI stub is also provided to
2035 allow the kernel to be booted as an EFI application. This
2036 is only useful for kernels that may run on systems that have
2040 bool "Enable support for SMBIOS (DMI) tables"
2044 This enables SMBIOS/DMI feature for systems.
2046 This option is only useful on systems that have UEFI firmware.
2047 However, even with this option, the resultant kernel should
2048 continue to boot on existing non-UEFI platforms.
2050 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2051 i.e., the the practice of identifying the platform via DMI to
2052 decide whether certain workarounds for buggy hardware and/or
2053 firmware need to be enabled. This would require the DMI subsystem
2054 to be enabled much earlier than we do on ARM, which is non-trivial.
2058 menu "CPU Power Management"
2060 source "drivers/cpufreq/Kconfig"
2062 source "drivers/cpuidle/Kconfig"
2066 menu "Floating point emulation"
2068 comment "At least one emulation must be selected"
2071 bool "NWFPE math emulation"
2072 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2074 Say Y to include the NWFPE floating point emulator in the kernel.
2075 This is necessary to run most binaries. Linux does not currently
2076 support floating point hardware so you need to say Y here even if
2077 your machine has an FPA or floating point co-processor podule.
2079 You may say N here if you are going to load the Acorn FPEmulator
2080 early in the bootup.
2083 bool "Support extended precision"
2084 depends on FPE_NWFPE
2086 Say Y to include 80-bit support in the kernel floating-point
2087 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2088 Note that gcc does not generate 80-bit operations by default,
2089 so in most cases this option only enlarges the size of the
2090 floating point emulator without any good reason.
2092 You almost surely want to say N here.
2095 bool "FastFPE math emulation (EXPERIMENTAL)"
2096 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2098 Say Y here to include the FAST floating point emulator in the kernel.
2099 This is an experimental much faster emulator which now also has full
2100 precision for the mantissa. It does not support any exceptions.
2101 It is very simple, and approximately 3-6 times faster than NWFPE.
2103 It should be sufficient for most programs. It may be not suitable
2104 for scientific calculations, but you have to check this for yourself.
2105 If you do not feel you need a faster FP emulation you should better
2109 bool "VFP-format floating point maths"
2110 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2112 Say Y to include VFP support code in the kernel. This is needed
2113 if your hardware includes a VFP unit.
2115 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2116 release notes and additional status information.
2118 Say N if your target does not have VFP hardware.
2126 bool "Advanced SIMD (NEON) Extension support"
2127 depends on VFPv3 && CPU_V7
2129 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2132 config KERNEL_MODE_NEON
2133 bool "Support for NEON in kernel mode"
2134 depends on NEON && AEABI
2136 Say Y to include support for NEON in kernel mode.
2140 menu "Power management options"
2142 source "kernel/power/Kconfig"
2144 config ARCH_SUSPEND_POSSIBLE
2145 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2146 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2149 config ARM_CPU_SUSPEND
2150 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2151 depends on ARCH_SUSPEND_POSSIBLE
2153 config ARCH_HIBERNATION_POSSIBLE
2156 default y if ARCH_SUSPEND_POSSIBLE
2160 source "drivers/firmware/Kconfig"
2163 source "arch/arm/crypto/Kconfig"
2166 source "arch/arm/kvm/Kconfig"